Commit graph

637 commits

Author SHA1 Message Date
Yanyan Shen
d8d006fab9 armv8/hyp: Add armHSCurVCPU and armHSVCPUActive 2018-03-28 12:15:09 +11:00
Yanyan Shen
2a7076177f armv8: Use array regs in vcpu for aarch64 2018-03-28 12:15:09 +11:00
Yanyan Shen
0b71b332c1 armv8: Add VCPU_PTR and VCPU_REF 2018-03-28 12:15:09 +11:00
Yanyan Shen
942b1bd2a9 armv8: Add VCPU_SIZE_BITS for EL2 2018-03-28 12:15:09 +11:00
Yanyan Shen
e289a0526c armv8: Add tcbVCPU for EL2 arch_tcb 2018-03-28 12:15:09 +11:00
Yanyan Shen
544c73b4cb armv8: Handle SPSR_EL1 in sanitiseRegister for VMs 2018-03-28 12:15:04 +11:00
Yanyan Shen
7246586310 armv8: Define PPTR_TOP for EL2 2018-03-28 12:11:33 +11:00
Yanyan Shen
4a67506cd3 armv8: Add EL2 support for kernel exit code 2018-03-28 11:17:58 +11:00
Yanyan Shen
a47d4b8759 armv8: Generalise ESR shift and constants 2018-03-28 11:17:58 +11:00
Bruce Mitchener
b942a50441 Fix trivial comment typos. 2018-03-27 10:51:26 +11:00
Yanyan Shen
a5e683b70f armv8: Extend AttrIndx to 4-bit for stage-2 2018-03-23 17:39:49 +11:00
Yanyan Shen
894f3b9d94 armv8: Add virq types 2018-03-23 17:39:49 +11:00
Yanyan Shen
ba0da28e30 armv8: Add VGICMaintenance and VCPUFault 2018-03-23 17:39:49 +11:00
Yanyan Shen
5a8b96000c armv8: Add vcpu_cap 2018-03-23 17:39:49 +11:00
Yanyan Shen
e7c2c8b1a1 armv8: EL2 uses 48-bit base without sign extension 2018-03-23 17:39:49 +11:00
Adrian Danis
30738188db x86: modeUnmapPage returns whether or not tlb needs invalidation
Whilst it is always correct to invalidate the TLB even if no page was unampped this
provides a small optimization and makes the modeUnmapPage behaviour mirror the general
arch behaviour
2018-03-15 09:47:31 +11:00
Yanyan Shen
1157c708fa arm: Remove duplicate extern declarations. 2018-03-14 20:26:13 +11:00
Yanyan Shen
f001f7b22e armv8: Add checkTCR_EL2 function. 2018-03-14 14:02:35 +11:00
Yanyan Shen
cd4854f4de armv8: Get CPU index from TPIDR_EL2 when SMP&&HYP. 2018-03-14 14:02:35 +11:00
Yanyan Shen
56b03faeb6 armv8: Add address translation helper functions. 2018-03-14 14:02:35 +11:00
Yanyan Shen
bef8a955c1 armv8: Get ESR and FAR according to current EL. 2018-03-14 14:02:35 +11:00
Yanyan Shen
abe01d34f9 armv8: Invalidate local TLB according to EL. 2018-03-14 14:02:35 +11:00
Yanyan Shen
33bc152dc7 armv8: Add functions to invalidate all TLB entries. 2018-03-14 14:02:35 +11:00
Yanyan Shen
d4770d4d44 armv8: Set vector table according to current EL. 2018-03-14 14:02:35 +11:00
Yanyan Shen
a0a306fc83 armv8: Add getVTTBR() to read VTTBR_EL2. 2018-03-14 14:02:35 +11:00
Yanyan Shen
3ce9b94239 armv8: Use VTTBR_EL2 as user VSpaceRoot in EL2. 2018-03-14 14:02:35 +11:00
Yanyan Shen
d5e763e028 armv8: Use TTBR0_EL2 as kernel VSpaceRoot in EL2. 2018-03-14 14:02:35 +11:00
Yanyan Shen
f1849ef878 armv8: Add EL2 support for writeTPIDRPRW function. 2018-03-14 14:02:35 +11:00
Sebastian Holzapfel
60aac65c99 ARM/v7-a: Force -O2 compilation of idle thread
This fixes a problem with -O0 SMP builds on ARM visible as kernel
data aborts whenever the idle thread executes.

The idle thread receives no stack pointer. At -O2, this is fine
as the wfi() call is inlined and stack operations in idle_thread
are optimized out. At -O0, the stack operations remain and wfi()
is not inlined, resulting in stack accesses in the idle thread
that cause data aborts.

Forcing -O2 behaviour was deemed the simplest solution for now.
Giving the idle thread a stack would have had larger verification
ramifications for what is now a fairly uncommon use case.
2018-03-13 13:09:47 +11:00
Yanyan Shen
81aed11952 armv8: Add PSTATE_IDLETHREAD for EL2. 2018-03-05 14:47:12 +11:00
Yanyan Shen
ff34f8895a armv8: Add SCTLR EL1 stack alignment check field. 2018-03-05 13:42:15 +11:00
Yanyan Shen
d46d4be043 armv8: Define CNT_TVAL and CNT_CTL for EL2. 2018-03-01 16:00:39 +11:00
Yanyan Shen
0da9ff1b67 aarch64: Correct the CPUID_MASK 2018-02-27 11:52:29 +11:00
Adrian Danis
d4d1613f6c Arch abstract for postCapDeletion
Allows architectures to define their own operations for post deletion of capabilities.
The Arch_ variants could be extended to Mode_ if desired in the future, but there is
no need to do this until it is necessary.
2018-02-23 10:03:50 +11:00
Adrian Danis
2cfff40d9d Allow Arch_finaliseCap to return cleanup information
Changes Arch_finaliseCap and Mode_finaliseCap to return the same finaliseCap_ret_t type
as finaliseCap. This allows the Arch and Mode specific functions to define cleanup
information of its capabilities if necessary, just like the generic capabilities can
in finaliseCap.
2018-02-23 10:03:50 +11:00
Adrian Danis
bae90533d9 x86: Fix flush RSB
The previous assembly is syntactically wrong and managed to somehow not get tested
originally
2018-02-07 10:20:14 +11:00
Adrian Danis
b1e799a447 x86: Config option for RSB flush on context switch
This option can be enabled to prevent a user from performing a Spectre like attack on
another user through polluting the RSB.
2018-02-02 10:23:31 +11:00
Adrian Danis
2423c62015 x86: Config option for branch prediction barrier on context switch
This option can be enabled to prevent a user from performing a Spectre like attack on
another user through polluting the indirect branch predictor.
2018-02-02 10:23:31 +11:00
Adrian Danis
f0594ac917 x86: Implement IBRS based Spectre mitigations
Provides the ability to enable the IBRS hardware Spectre mitigation strategies, as well
as completes the software mitigation by disabling jump tables in compilation. The
hardware mitigations are largely provided "for completeness" in the hopes that they
eventually become less expensive. For the moment there is no reason to turn on any
beyond STIBP if running in multicore
2018-02-02 10:23:31 +11:00
Adrian Danis
3900515c45 x86: Helpers for using the speculation MSRs 2018-02-02 10:23:31 +11:00
Adrian Danis
fe1302cb65 x86: Define MSRs for speculation control
These MSRs provide access to the IBRS feature and the IBPB command
2018-02-02 10:23:31 +11:00
Adrian Danis
caf456ddca x86: Helper for flushing RSB 2018-02-02 10:23:31 +11:00
Yanyan Shen
1936323e48 armv8: Add SMP support for aarch64
(1) Use NODE_STATE() to access per-core kernel data.
(2) Allocate kernel stack in src/arch/arm/64/head.S.
(3) Use the TPIDR_EL1 to contain the kernel stack pointer
    as well as the logical core ID. The kernel stack must
    be 4-KiB aligned, and the lowest 12 bits of TPIDR_EL1
    are for the logical core ID.
(4) Define the LD_EX, ST_EX, and OP_WIDTH as "ldxr", "stxr",
    and "w".
(5) Add irq_remote_call_ipi and irq_reschedule_ipi
2018-01-24 10:26:33 +11:00
Yanyan Shen
f92af27aec arm: add LD_EX, ST_EX, OP_WIDTH macros for ARM
The macros are used in try_arch_atomic_exchange function, and
they will be replaced by "ldrex", "strex", and null.
2018-01-24 10:18:02 +11:00
Yanyan Shen
13343815e3 armv8: add macro L1_CACHE_LINE_SIZE for aarch64 2018-01-24 09:35:50 +11:00
Adrian Danis
353e2aa38d x86: Define CR4 SMEP/SMAP bits 2018-01-18 10:51:53 +11:00
Adrian Danis
06671703cc x86: CPUID feature flags definition
Define the ebx result register for the extended feature flags CPUID
2018-01-18 10:23:34 +11:00
Adrian Danis
f26853b9a4 x86: Supervisor write protection
Prevents the kernel from writing to read only memory. This shouldn't happen, but catching
such attempts aids debugging and costs nothing to have neabled.
2018-01-18 10:22:40 +11:00
Bamboo
374da850af [STYLE_FIX] 2018-01-17 05:56:38 +00:00
Adrian Danis
29695d2636 x64: SKIM window to mitigate Meltdown (CVE-2017-5754) on x86-64
Introduces a kernel option that, when enabled, reduces the kernel window in a user address
space to just be Static Kernel Image and Microstate (SKIM), instead of the full kernel
address space. This isolates the important kernel data from the user preventing a
Meltdown style attack being able to violate secrecy. The kernel text and read only data,
i.e. anything that is static from boot, is not secret and can be allowed in the SKIM window
and potentially read by the user. Additionally to switch to and from the actual kernel
address space a small amount of state needs to also be in the SKIM window.

This is only an implementation for x86-64, although the same design is applicable to ia32
2018-01-17 16:38:52 +11:00