Commit graph

918 commits

Author SHA1 Message Date
Yanyan Shen
d8d006fab9 armv8/hyp: Add armHSCurVCPU and armHSVCPUActive 2018-03-28 12:15:09 +11:00
Yanyan Shen
2a7076177f armv8: Use array regs in vcpu for aarch64 2018-03-28 12:15:09 +11:00
Yanyan Shen
0b71b332c1 armv8: Add VCPU_PTR and VCPU_REF 2018-03-28 12:15:09 +11:00
Yanyan Shen
942b1bd2a9 armv8: Add VCPU_SIZE_BITS for EL2 2018-03-28 12:15:09 +11:00
Yanyan Shen
e289a0526c armv8: Add tcbVCPU for EL2 arch_tcb 2018-03-28 12:15:09 +11:00
Yanyan Shen
544c73b4cb armv8: Handle SPSR_EL1 in sanitiseRegister for VMs 2018-03-28 12:15:04 +11:00
Yanyan Shen
7246586310 armv8: Define PPTR_TOP for EL2 2018-03-28 12:11:33 +11:00
Yanyan Shen
4a67506cd3 armv8: Add EL2 support for kernel exit code 2018-03-28 11:17:58 +11:00
Yanyan Shen
a47d4b8759 armv8: Generalise ESR shift and constants 2018-03-28 11:17:58 +11:00
Bruce Mitchener
b942a50441 Fix trivial comment typos. 2018-03-27 10:51:26 +11:00
Yanyan Shen
a5e683b70f armv8: Extend AttrIndx to 4-bit for stage-2 2018-03-23 17:39:49 +11:00
Yanyan Shen
894f3b9d94 armv8: Add virq types 2018-03-23 17:39:49 +11:00
Yanyan Shen
ba0da28e30 armv8: Add VGICMaintenance and VCPUFault 2018-03-23 17:39:49 +11:00
Yanyan Shen
5a8b96000c armv8: Add vcpu_cap 2018-03-23 17:39:49 +11:00
Yanyan Shen
e7c2c8b1a1 armv8: EL2 uses 48-bit base without sign extension 2018-03-23 17:39:49 +11:00
Adrian Danis
bce62b4e43 Check that TCB object is not larger than necessary 2018-03-23 12:28:54 +11:00
Adrian Danis
a2a2d9b937 Define tcb_t as half the TCB object size
A TCB object has two objects inside it, the cnode object and the 'actual tcb object'.
For simplicity of verification we would like the tcb_t portion of the object to also
be size aligned instead of just just being offset by the size of the cnode.
2018-03-23 12:28:54 +11:00
Adrian Danis
f5abc87894 Rename TCB_SIZE_BITS to TCB_CNODE_SIZE_BITS
This definition is used as the size of the cnode portion of the TCB object (and not the tcb_t)
portion and so this provides a much less confusing name.
2018-03-23 12:28:54 +11:00
Anna Lyons
f6ff7806dd define KERNEL_PMU_IRQ for TX1, HIKEY 2018-03-22 13:12:03 +11:00
Adrian Danis
30738188db x86: modeUnmapPage returns whether or not tlb needs invalidation
Whilst it is always correct to invalidate the TLB even if no page was unampped this
provides a small optimization and makes the modeUnmapPage behaviour mirror the general
arch behaviour
2018-03-15 09:47:31 +11:00
Yanyan Shen
1157c708fa arm: Remove duplicate extern declarations. 2018-03-14 20:26:13 +11:00
Yanyan Shen
f001f7b22e armv8: Add checkTCR_EL2 function. 2018-03-14 14:02:35 +11:00
Yanyan Shen
cd4854f4de armv8: Get CPU index from TPIDR_EL2 when SMP&&HYP. 2018-03-14 14:02:35 +11:00
Yanyan Shen
56b03faeb6 armv8: Add address translation helper functions. 2018-03-14 14:02:35 +11:00
Yanyan Shen
bef8a955c1 armv8: Get ESR and FAR according to current EL. 2018-03-14 14:02:35 +11:00
Yanyan Shen
abe01d34f9 armv8: Invalidate local TLB according to EL. 2018-03-14 14:02:35 +11:00
Yanyan Shen
33bc152dc7 armv8: Add functions to invalidate all TLB entries. 2018-03-14 14:02:35 +11:00
Yanyan Shen
d4770d4d44 armv8: Set vector table according to current EL. 2018-03-14 14:02:35 +11:00
Yanyan Shen
a0a306fc83 armv8: Add getVTTBR() to read VTTBR_EL2. 2018-03-14 14:02:35 +11:00
Yanyan Shen
3ce9b94239 armv8: Use VTTBR_EL2 as user VSpaceRoot in EL2. 2018-03-14 14:02:35 +11:00
Yanyan Shen
d5e763e028 armv8: Use TTBR0_EL2 as kernel VSpaceRoot in EL2. 2018-03-14 14:02:35 +11:00
Yanyan Shen
f1849ef878 armv8: Add EL2 support for writeTPIDRPRW function. 2018-03-14 14:02:35 +11:00
Sebastian Holzapfel
60aac65c99 ARM/v7-a: Force -O2 compilation of idle thread
This fixes a problem with -O0 SMP builds on ARM visible as kernel
data aborts whenever the idle thread executes.

The idle thread receives no stack pointer. At -O2, this is fine
as the wfi() call is inlined and stack operations in idle_thread
are optimized out. At -O0, the stack operations remain and wfi()
is not inlined, resulting in stack accesses in the idle thread
that cause data aborts.

Forcing -O2 behaviour was deemed the simplest solution for now.
Giving the idle thread a stack would have had larger verification
ramifications for what is now a fairly uncommon use case.
2018-03-13 13:09:47 +11:00
Yanyan Shen
396cfaac0e armv8/tx1: Map GIC VCPU control interface for EL2. 2018-03-05 16:05:48 +11:00
Yanyan Shen
c1bf4fe432 armv8/tx1: Introduce KDEV_PPTR.
The KDEV_PPTR is defined for EL1 and EL2 differently as the
base for kernel-device virtual addresses.
2018-03-05 15:58:37 +11:00
Yanyan Shen
28014895dd armv8/tx1: Define kernelBase and USER_TOP for EL2. 2018-03-05 15:42:36 +11:00
Yanyan Shen
151506c7bb armv8/tx1: Increase physical memory size for TX1. 2018-03-05 15:35:03 +11:00
Yanyan Shen
5d3154da80 armv8/tx1: Fix a typo
Change GIC_CONTROLLER0_PADDR to GIC_CONTROLLER_PADDR
2018-03-05 15:30:11 +11:00
Yanyan Shen
2337827e3a arm/tx1: Add device physical addresses for TX1. 2018-03-05 15:09:46 +11:00
Yanyan Shen
81aed11952 armv8: Add PSTATE_IDLETHREAD for EL2. 2018-03-05 14:47:12 +11:00
Yanyan Shen
ff34f8895a armv8: Add SCTLR EL1 stack alignment check field. 2018-03-05 13:42:15 +11:00
Yanyan Shen
d46d4be043 armv8: Define CNT_TVAL and CNT_CTL for EL2. 2018-03-01 16:00:39 +11:00
Yanyan Shen
7ce75bb2ae arm/tx1: Define the IRQs used in EL2. 2018-02-28 10:54:18 +11:00
Yanyan Shen
0da9ff1b67 aarch64: Correct the CPUID_MASK 2018-02-27 11:52:29 +11:00
Anna Lyons
33398f2191 SELFOUR-331: add seL4_TCB_SetSchedParams
This allows the prio and mcp to be set in one system call.
2018-02-26 11:24:42 +11:00
Anna Lyons
05b83acd95 SELFOUR-1016: Require auth cap to set prio/mcp
This fixes confused deputy problem when setting priorities/mcps.
2018-02-26 11:24:22 +11:00
Adrian Danis
d4d1613f6c Arch abstract for postCapDeletion
Allows architectures to define their own operations for post deletion of capabilities.
The Arch_ variants could be extended to Mode_ if desired in the future, but there is
no need to do this until it is necessary.
2018-02-23 10:03:50 +11:00
Adrian Danis
2cfff40d9d Allow Arch_finaliseCap to return cleanup information
Changes Arch_finaliseCap and Mode_finaliseCap to return the same finaliseCap_ret_t type
as finaliseCap. This allows the Arch and Mode specific functions to define cleanup
information of its capabilities if necessary, just like the generic capabilities can
in finaliseCap.
2018-02-23 10:03:50 +11:00
Adrian Danis
d258cb3107 Generic postCapDeleted definition
Moves the explicit call of `deletedIRQHandler` in `emptySlot` into a new
`postCapDeleted` function that is a generic function to call after a capability
has been deleted.

Currently `deletedCap` only implementes the IRQ case.
2018-02-23 10:03:50 +11:00
Adrian Danis
d8ae122cc8 Generalise finaliseCap to more than just IRQs
Changes finaliseCap to return a generic definition of cleanup information that
needs to be done, instead of just encoding an IRQ number. The post deletion information
is encoded as a `cap_t` due to the capability type already being a union of all
the possible information. Aside from providing a properly generic mechanism the motivation
is to support a similar cleanup phase for I/O ports in the future.
2018-02-23 10:03:50 +11:00