Commit graph

1031 commits

Author SHA1 Message Date
Yanyan Shen
7cf9aff9e9 armv8/hyp: Call VMID-based TLB functions in EL2 2018-05-01 21:18:27 +10:00
Yanyan Shen
190c44d0d8 armv8: Add invalidateLocalTLB_VMID/IPA_VMID 2018-05-01 21:18:21 +10:00
Yanyan Shen
604f70f607 armv8: Add invalidateLocalTLB_IPA function 2018-05-01 20:59:21 +10:00
Yanyan Shen
0b085a8efb armv8: Add invalidateLocalTLB_VMALLS12E1() 2018-05-01 20:59:21 +10:00
Adrian Danis
5fade8b29f x86: Hide tcbArchEPTRoot when not VTX 2018-04-30 16:08:31 +10:00
Adrian Danis
13f0a4e8d4 riscv: Implement Arch_isCapRevocable 2018-04-26 10:01:47 +10:00
Yanyan Shen
df440f4f18 armv8/hyp: Read/write MDCR_EL2 for debug control 2018-04-25 00:20:49 +10:00
Adrian Danis
de42f82691 x86: Introduce IO port control caps
Changes the way IO ports work such that instead of 'minting' IO port caps down into new
IO port caps with smaller ranges new IO port ranges must be allocated centrally from
an IO port control cap. This mechanism acts in a very similar fashion as IRQ handler/control
capabilities and ensures that allocated IO ports do not overlap. Disallowing overlapping
IO ports is necessary to ensure the CDT remains valid as capabilities are deleted.
2018-04-24 14:04:46 +10:00
Adrian Danis
8081b9ec80 x86: More efficient and verification friendly setIOPortMask
Refactors setIOPortMask to both be more efficient by never operating on individual bits,
whilst still having a structure that is more amenable to verification
2018-04-24 14:04:46 +10:00
Adrian Danis
ca1b785e58 x86: Generic setIOPortMask from VCPU code
Moves the function for manipulating a bitmap of IO ports from VCPU code into common
IO port code. This will be needed in the future by the IO Port control implementation
2018-04-24 14:04:46 +10:00
Adrian Danis
6c7d94a093 Type wrapper for a word_t that may alias 2018-04-24 14:04:46 +10:00
Adrian Danis
7641e43872 Refactor logic for cap revocability in cteInsert into new function with arch case
Revocability of a cap, with respect to its parent, is a general property on caps and
makes sense to be abstracted. This allows for the addition of an arch case without
further complicating the cteInsert function itself.
2018-04-24 14:04:46 +10:00
Yanyan Shen
9acfe72e3f arm: Split TLB functions into local & local+remote
The TLB functions with "Local" postfix only execute on the
current calling core. The functions with the postfix
perform local operations and then IPI remote cores
to perform the same operations if necessary.
2018-04-18 19:09:53 +10:00
Anna Lyons
d3feb06cdd riscv: fix licenses
- add files from elsewhere to the license ignore
- s/D61_BSD/DATA61_BSD
2018-04-18 10:52:02 +10:00
Adrian Danis
679c0b09ed Remove strlen
This is not suitable for verification and strnlen must be used instead.
2018-04-18 10:10:14 +10:00
Adrian Danis
82c997aebe Expose string functions in all builds
These are useful beyond just debug and printing builds
2018-04-18 10:10:14 +10:00
Anna Lyons
1b68590b3f riscv: use one definition of page bits 2018-04-18 10:10:14 +10:00
Adrian Danis
06a66cd1ca trivial: style 2018-04-18 10:10:14 +10:00
Adrian Danis
43e1705280 Remove strcmp
This function causes difficulties for verification and strncmp should be used instead.
2018-04-18 10:10:14 +10:00
Adrian Danis
ddd1e128ba riscv: Remove now out of date todo 2018-04-18 10:10:14 +10:00
Adrian Danis
f5fa2072a5 riscv: Guard potentially undefined page size constants
These pages don't have a defined size on rv32 (i.e. when PT_LEVELS == 2)
2018-04-18 10:10:14 +10:00
Anna Lyons
76c61025ac riscv: remove dev_pregs
We don't have any devices currently, and in future they will be
discovered, not statically specified.
2018-04-18 10:10:14 +10:00
Anna Lyons
b7d4bc1629 riscv: remove trailing whitespace line 2018-04-18 10:10:14 +10:00
Anna Lyons
f68779d76e riscv: move LOAD to hardware.h in mode
removes the #ifdef and uses the dir structure instead.
2018-04-18 10:10:14 +10:00
Adrian Danis
402cc309f1 riscv: Remove bogus L1 cache line size 2018-04-18 10:10:14 +10:00
Adrian Danis
fbe634620c riscv: Remove currently unuspported SMP code 2018-04-18 10:10:14 +10:00
Adrian Danis
eccaed9f70 riscv: Remove currently unsupported FPU 2018-04-18 10:10:14 +10:00
Anna Lyons
99d93ebe04 riscv: correct typo in comment 2018-04-18 10:10:14 +10:00
Anna Lyons
5cd0dd52be riscv: add missing fault types 2018-04-18 10:10:14 +10:00
Anna Lyons
00cf62bb09 riscv: remove unneccessary #if CONFIG_PT_LEVELS
This guard is only required for object types to avoid
seL4 thinking they are valid objects. Defining the size constants does
not need to be guarded.
2018-04-18 10:10:14 +10:00
Anna Lyons
308e8bf4d2 riscv: move machine functions to machine.h
And add memory barriers while we are at it.
2018-04-18 10:10:14 +10:00
Anna Lyons
952d305103 riscv: remove unused function 2018-04-18 10:10:14 +10:00
Adrian Danis
5ac36bcefb riscv: Move strcmp to util 2018-04-18 10:10:14 +10:00
Adrian Danis
c083919796 riscv: Move strlen to util 2018-04-18 10:10:14 +10:00
Adrian Danis
6938c98adf riscv: Fill physical memory regions from FDT
Removes the hardcoded physical memory region from the spike platform and fills it from
FDT parsing instead.
2018-04-18 10:10:14 +10:00
Adrian Danis
ee37eebcae riscv: Cleanup FDT code
Rewrites the FDT code to remove all the disallowed function pointers have attempt to perform
the equivalent functionality of query_mem in place in the main parser. With the callback
system gone all the rest of the unused FDT code is deleted as it doesn't make sense.
2018-04-18 10:10:14 +10:00
Adrian Danis
a2a6be95ca Define more freemem regions on all architectures except ARM
2 freemem regions is far to prohibitive on platforms that have fragmented initial
memory. Ultimately ARM should be changed to also have more than 2, but is being
deferred for now as it will result in trivial verification breakage.
2018-04-18 10:10:14 +10:00
Anna Lyons
f2214437ff riscv: remove unused function prototype 2018-04-18 10:10:14 +10:00
Anna Lyons
e17272fe4e riscv: remove concept of level in map functions
It is no longer required
2018-04-18 10:10:14 +10:00
Anna Lyons
a407e3ffd0 riscv: rewrite lookupPTSlot to decode bits
- instead of specifying a level, find the leaf in the page table
- this simplifies a lot of the lookup code
2018-04-18 10:10:14 +10:00
Adrian Danis
22b050c95d riscv: Redesign kernel window
Restructures the kernel window so that instead of being a single contiguous region with
a single offset to physical memory, it is two such regions. This allows us to use the
larger of the two windows as a window into physical memory, and the second smaller window
as a place to run the kernel image from. Having this additional window allows us to
link the kernel for different physical addresses without needing to change its virtual
address, or change the layout of the kernel window.
There are other ways to achieve this, but this is one of the simplest and matches how
x86-64 implements its kernel window.
2018-04-18 10:10:14 +10:00
Anna Lyons
a39ca9f15e riscv: remove safe mapping entries
This is a concept from ARM that is not required for RISCV, as we are
only mapping one page at a time.
2018-04-18 10:10:14 +10:00
Anna Lyons
4b555136ec riscv: remove incorrect comment about 4k frames
they can be other sizes too
2018-04-18 10:10:14 +10:00
Kent McLeod
a9085b3689 RISC-V: Guard __riscv_flen compiler definitions
These definitions don't exist on software floatingpoint ABI's which is
what we are currently using
2018-04-18 10:10:14 +10:00
Adrian Danis
61df56a7f3 riscv: Remove VMNoAccess mapping type
A frame cannot be mapped without any access permissions, as this encoding is used to
represent a page table mapping.
2018-04-18 10:10:14 +10:00
Anna Lyons
4f97ff1c93 riscv: remove unused benchmark code 2018-04-18 10:10:14 +10:00
Anna Lyons
23d83d6c42 riscv: remove capFTMapType
it is not used on riscv
2018-04-18 10:10:14 +10:00
Anna Lyons
0764d2ac7d riscv: build on 32 bit 2018-04-18 10:10:14 +10:00
Anna Lyons
937d042395 riscv: fix style 2018-04-18 10:10:14 +10:00
Anna Lyons
00cae0baed riscv: move STRINGIFY et al to util.h 2018-04-18 10:10:14 +10:00