Commit graph

1319 commits

Author SHA1 Message Date
Yanyan Shen
db3c4ff44f riscv: Guard SMP inlines with the macro
Guard the added SMP inline functions with the ENABLE_SMP_SUPPORT.
2019-10-10 17:22:06 +11:00
Yanyan Shen
0a6df5fc87 riscv: Remove IPI functions when SMP is off
Remove ipi_get_irq() and ipi_clear_irq() when SMP is not enabled.
2019-10-10 17:22:06 +11:00
Yanyan Shen
e7957006e5 trivial: Correct year 2019-10-10 17:22:06 +11:00
Yanyan Shen
b32c0b8dcb riscv: Add fence_r_rw() and fence_w_r()
Add more memory fences.
2019-10-10 17:22:06 +11:00
Yanyan Shen
a45f389704 trivial: Fix style 2019-10-10 17:22:06 +11:00
Yanyan Shen
4741fb6492 riscv: SMPify booting code
Add SMP support for booting code.
2019-10-10 17:22:06 +11:00
Yanyan Shen
b848e58d5a riscv: Add IPI calls and handlers
Add IPI call functions and handler functions.
2019-10-10 17:22:06 +11:00
Yanyan Shen
633412dbf1 riscv: Generalise/SMPify PLIC code
Add SMP support for PLIC code.
2019-10-10 17:22:06 +11:00
Yanyan Shen
d1a0de41ff riscv: Split IRQ init to platform and local
Split IRQ init code to platform-code and per-hart code.
2019-10-10 17:22:06 +11:00
Yanyan Shen
e1c529caa5 riscv: Add SMP code for ifence/sfence/hwASIDFlush
If SMP is enabled, sfence/ifence/hwASIDFlush also IPI other
cores.
2019-10-10 17:22:06 +11:00
Yanyan Shen
07a5a3f5d9 riscv: Add memory fences and local ifence/sfence
Add memory fences.
Add local ifence and sfence which work on the calling
core only.
2019-10-10 17:22:06 +11:00
Yanyan Shen
5a0d349845 riscv: Include header for SMP macros
Include header or SMP macros.
2019-10-10 17:22:06 +11:00
Yanyan Shen
1c53fea9d3 riscv: Add L1 cache line size and memory barrier
Add the L1 cache line size based on HiFive Unleashed.
2019-10-10 17:22:06 +11:00
Yanyan Shen
934080b7f5 riscv: Add IPI types and arch_pause() function
Add reschedule and call IPI types.
Add arch_pause() function.
2019-10-10 17:22:06 +11:00
Yanyan Shen
e92b4e68b5 riscv: Add SMP functions
Add SMP functions for RISCV.
2019-10-10 17:22:06 +11:00
Yanyan Shen
a6c9dcf8a7 riscv: Use sscratch for per-core kernel stack
When SMP is enabled, the sscratch register is used to
contain the per-core kernel stack instead of the current
running thread. We get the current running thread from the
top of the kernel stack.
2019-10-10 17:22:06 +11:00
amrzar
a4d6bf850c SELFOUR-161: Merge Page_Remap with Page_Map
- Remove Remap function from seL4 API for arm, x86, riscv and the
respective invocation implementation.
- Update Map as replacement for Remap
- Update manual

This allows a change of rights if the frame being mapped is already
mapped in at the given vaddr. To map a page to a different address,
unmap it first.

Co-authored-by: Hesham Almatary <hesham.almatary@data61.csiro.au>
Co-authored-by: Anna Lyons <Anna.Lyons@data61.csiro.au>
Co-authored-by: Victor Phan <Victor.Phan@data61.csiro.au>
Co-authored-by: Kent McLeod <Kent.Mcleod@data61.csiro.au>
2019-10-10 15:54:23 +11:00
Simon Shields
3e83f89990 x86: avoid -Waddress-of-packed-member
It's safe to take the address of this member, since it's the
first thing in a cacheline-aligned struct.
2019-09-26 15:34:26 +10:00
Curtis Millar
c25e5445fb mcs: Don't rollback time when not rescheduling
This allows ksCurTime to be monotonically increasing making proofs much
easier to construct.
2019-09-23 16:49:07 +10:00
Kent McLeod
8234026c1f aarch64: Move tpidrro_el0 from vcpu to tcb context
This register is visible to software executing at EL0 but not writeable.
Storing it in the VCPU context required custom save/restore handling as
it had to be explicitly handled when switching from a VCPU thread to a
non-VCPU thread so that it didn't become a channel. It is possible to
now update this register via seL4_TCB_WriteRegisters for software
executing at EL0.

This also fixes a potential bug where if a vcpu-thread is switched for a
non-vcpu-thread and then switched to a different vcpu-thread the
original vcpu-thread's copy of this register will get set to 0.
2019-09-19 11:39:14 +10:00
Kent McLeod
ef8b01390d KernelIRQReporting: Change reserved IRQ reporting
Reserved IRQ reporting would print on every received reserved IRQ. This
feature is supposed to report spurious interrupts, yet most cases
reserved IRQs are not spurious. We change the printing to only print if
the reserved IRQ was unhandled. The intention is to allow more app
configurations to leave this feature enabled in development builds.
2019-09-19 11:33:03 +10:00
Anna Lyons
7798b4767d aarch64: allow access to memory below physBase
On aarch64 physBase is the constant that points to the bottom of
physical memory (RAM).

Prior to this change the kernel window was mapped directly to physBase,
which is usually not a 0 paddr. As a consequence the kernel could not
access any memory below physBase.

This change fixes this issue by mapping the start of the kernel window
to 0 in the physical address space.

- add new constant PADDR_LOAD, the location of the kernel image in the
physical address space.
- add new constant PADDR_BASE, the start of the physical address space
(0).
- add new constant KERNEL_ELF_BASE, the location of the kernel image in
kernel virtual memory.

A consequence of this change is that on aarch64, the kernelBase constant
now points to the start of the kernel window in virtual memory, but
*not* to the start of the kernel image as these are now different.
2019-09-13 08:35:19 +10:00
Curtis Millar
18219bbedf mcs: RISC-V uses 39-bit addressing in stuctures.bf
RISC-V uses 39-bit virtual addressing rather than 48 bits so the
'high' bits of a pointer can be 39 or fewer bits on RISCV rather than
48.
2019-08-27 10:46:13 +10:00
Curtis Millar
af34037edb trivial: spelling of the word 'canonical' 2019-08-27 10:46:13 +10:00
Curtis Millar
7adf81f6d7 mcs: fastpath_reply_recv reply argument for RISC-V
Add the reply argument to the fastpath_reply_recv call for RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
d869b3adb7 mcs: Timeout fault and reply for RISC-V
Add fault and reply for timeout faults on RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
f100d73f9c mcs: add mcs capability variants for riscv
When building for RISC-V, capabilities should include SchedControl and
SchedContext capabilities.
2019-08-27 10:46:13 +10:00
Curtis Millar
449dcd5038 mcs: Select additional registers for RISC-V
mcs requires an additional 2 registers for performing system calls to
pass information regarding the reply capability and the destination of a
nbsend/recv.
2019-08-27 10:46:13 +10:00
Curtis Millar
210eb59d9d mcs: Implement timer functions for RISC-V
Introduce the functions needed to read the time and set the timer for
MCS in RISC-V.
2019-08-27 10:46:13 +10:00
Curtis Millar
1c4b6424d8 riscv: Fix rollover when reading time in 32-bit
If the time is being read in 32-bit mode it is read in two operations
between which the time can change. If the time causes the low bits to
roll over to 0 and the high bits to increment between reading the low
and high bits an incorrect time will be returned.

A check is added to ensure that an accurate time is returned.
2019-08-27 10:46:13 +10:00
Curtis Millar
557f8d4fb8 riscv: Relocate read time to header
Move the RISCV function to read the current time to the header file so
that it can be inlined for MCS.
2019-08-27 10:46:12 +10:00
Anna Lyons
b33d4680f2 mcs: Avoid charging invalid scheduling contexts
ChargeBudget can be called after a preemption, but the preemption may
have deleted the scheduling context. Do not charge scheduling contexts
that have been deleted (check scRefillMax).
2019-08-22 11:22:41 +10:00
Anna Lyons
86e50d0703 mcs: Avoid missing a timer tick
Preemption can be via the timer interrupt. In this case we need to
update the timestamp so we can reprogram the timer for the next timeout
and guarantee it is in the future, otherwise we will end up setting a
timeout in the past.
2019-08-22 11:22:41 +10:00
Anna Lyons
b358a1c59c trivial: move isSchedulable to header 2019-08-22 11:22:41 +10:00
Anna Lyons
257a62c73f mcs: explicitly use ksCurSC
- in refill_[budget|split]_check.
- This simplifies the code and the proofs.
2019-08-22 11:22:41 +10:00
Anna Lyons
ef4ba6b69a mcs: Introduce firstPhase flag to invocations
Some invocations contain two phases, and certain operations cannot be
allowed to run in the first phase as it could effect the currently
running thread and result in an invalid system state for the second
phase. This change filters those invocations, preventing them from being
used in the first phase of a two-phase, blocking system call.
2019-08-22 11:22:41 +10:00
Anna Lyons
483f0ae22f mcs: SchedControlConfigure: charge correct core
Previously this code would incorrectly call chargeBudget twice, where it
was intended to be charging a specific core.
2019-08-22 11:22:39 +10:00
Anna Lyons
4f00022f7d mcs: Use cancelIPC instead of reply_clear
- reply_clear only does half the job
- remove reply_clear no longer used
2019-08-22 11:22:39 +10:00
Anna Lyons
f103ac223d mcs: Refactor replies to solve revoke problems
Before this change, we set the replyObject in the thread state on recv
with no back pointer such that stray pointers would be left in the
thread state when a reply object was completed.

The new semantics are clearer and fix this problem by doing the
following:

- tcb->tcbReply is removed and the thread state field is always used,
  this was unneccessary duplication previously
- the thread state value is set to the reply object only when the thread
  is in BlockedOnReply or BlockedOnRecv
- the reply contains a back pointer, replyTCB, which points to that
  thread
- if a thread has its reply removed, it must be set to
  ThreadState_Inactive.
- deletion is easy in the blockedOnRecv case, we just unlink the reply
  and the tcb.
- deletion is complicated for blockedOnReply. If we are deleing a tcb,
  we remove the actual reply object and the call chain is broken. If we
  are deleting a reply, we maintain the call chain by moving the tcb to
  the next reply.
- we refactor the reply object interface to solve the above.
    * reply_clear: removes the reply from any connections (tcb, sc)
    * reply_unlink: just unlinks the tcb and reply, and sets the thread
      state to inactive
    * reply_remove: removes the reply from the call chain
    * reply_remove_tcb: removes the exact reply that a tcb is bound to,
      as we are removing that tcb. Breaks the call chain.
2019-08-22 11:22:39 +10:00
Adrian Danis
4768465027 mcs: allow kernel WCET estimate to be scaled
This configuration option allows for building images destined for
simulators, which may not simulate as fast as hardware, to still be
used.
2019-08-22 11:22:39 +10:00
Anna Lyons
2329cd81dc mcs: add seL4_SchedContext_YieldTo
Implement seL4_SchedContext_YieldTo, which allows users to manipulate
the scheduling queues up to their MCP and can be used for user level
scheduling.
2019-08-22 11:22:38 +10:00
Anna Lyons
a38e62f2f9 mcs: timeout exceptions
- Add seL4_TCB_SetTimeoutEndpoint
- implement timeout exceptions
2019-08-22 11:22:38 +10:00
Anna Lyons
c405ef53d2 mcs: install fault endpoint into tcb cnode
- seL4_TCB_Configure no longer takes a fault endpoint.
- seL4_TCB_SetSpace takes a cap in the callers cspace for the
  fault endpoint, not the target tcbs.
- seL4_TCB_SetSchedParams now also takes a fault endpoint as above.

This change installs the fault endpoint cap into the tcb cnode
first validating it.

This means either of the functions that set it will now return an error
if the cap is not either a null cap or an endpoint with send and
grant rights.

Significantly, the cap passed to the function should be in the callers
cspace, not the target tcbs.
2019-08-22 11:22:38 +10:00
Anna Lyons
106b893ee0 mcs: configurable scheduling context size
This allows users to define custom amounts of refills without
increasing the scheduling context size system wide.

also add libsel4 functions for refill size
2019-08-22 11:22:38 +10:00
Anna Lyons
96798066f6 mcs: avoid rolling back time if acted upon
Otherwise strange things can happen where threads are in the future.
2019-08-22 11:22:37 +10:00
Anna Lyons
9253704d2c mcs: update refills based on spec
This is a list of fixes that came up while working on the verification
spec for the mcs changes.

- trigger a timer tick if we are unable to split a refill
due to the refill list being full.
- make refill_ordered more useful
- pull the thread out of the scheduler before updating it
- simplify refill logic at verifications request
- Add unused to refill_sum
- Don't refill_split_check if consumed is empty
- sched_control: fix double increment bug
- sched-control: charge before reconfiguring ksCurSC
- Charge round robin threads differently

Sporadic server refill rules do not behave correctly for round robin
threads, instead, change the logic. Round robin threads have 2 refills:
current and next.
2019-08-22 11:22:37 +10:00
Rafal Kolanski
e04dbb9594 mcs: verification spec for clzll
This is required for the proofs.
2019-08-22 11:22:37 +10:00
Anna Lyons
a22cb3d102 mcs: associate scheduling context + ntfn
This commit allows scheduling contexts to be bound
to notification objects. When a passive server
receives a notification it will receive the scheduling
context from the notification. When the server
blocks the scheduling context is returned.
2019-08-22 11:22:37 +10:00
Anna Lyons
554f812da3 mcs: scheduling context donation over ipc
After this commit, threads blocked on an endpoint can recieve a
scheduling context from the thread that wakes the blocked thread.
2019-08-22 11:22:37 +10:00
Anna Lyons
5fe1890a83 mcs: order EP and NTFN queues
Previously IPC signal queues were FIFO, as of this change they are
ordered by priority (FIFO for same prio threads).
2019-08-22 11:22:35 +10:00