* commit '3ffa58aa1fb75c65fac4d1351bc6e014bdda2b64':
Verification: don't translate functions that are re-implemented from assembly to C
ARM Hyp: Fix fastpath_restore on ARM Hyp and implement slowpath and restore in C
SELFOUR-526: ARM - Implement slowpath and restore_user_context in C
Fixes a bug where previously MODEL_ID() was defined as:
`#define MODEL_ID(x) ( ((x & 0xf0000) >> 16) + (x & 0xf0) )`
This was incorrect because (1) it didn't take into account the conditional
nature of the extended_model_ID, and (2) it's actually shifting the
extended_model_ID into the low bits and keeping the model_ID in the high bits,
when it should be the other way around.
This patch also introduces a foundation for more sane testing of CPU vendor,
family, model and brand_ID.
* commit 'cee1268e9bf9619b60bd85cfda0a5d5306e8cf8a':
[VER-619] Pass verification related to newly added built-in unreachable
SELFOUR-545: x86 - cleanup c_traps.c file and use new traps.h
SELFOUR-526: ARM - dummy unreachable statements after fastpath calls
SELFOUR-526: ARM - Unify C entry point for system calls
This commit moves setThreadState outside the 'perform' stage of the
invocation, and renames decodeARMIOUnmapInvocation to
performPageInvocationUnmapIO as it is actually doing a perform
and not a decode
Previously the return value of cap_get_capPtr was compared to 0 in
sameRegionAs to emulate a check in the abstract specification that
tests if the cap is a physical cap or not. Overloading 0 results
in a scenario where a legitimate deviceUntyped's children do not
get considered to be children because they have a capPtr of 0.
This change adds and explicit function that returns whether or not
a capability is physical or not, and uses that in sameRegionAs
The XSAVE feature set is the future proof way for x86 CPUs to
manage extended CPU state. Extended state is MMX, FPU, SSE, AVX etc
registers. This is a replacement for the current FXSAVE and the
512 byte FPU region.
XSAVE introduces a few problems that this commit has to address
* The alignment of the XSAVE region is 64bytes, instead of the 16
bytes of the FXSAVE region
* XSAVE region size is dependent on the desired features, which
are detected at run time
* There are multiple variants of the XSAVE instruction that have
different potential optimizations, but are not always supported
The solutions to these are
* Re-order the FPU state and user registers in the user context
struct so that the new XSAVE region is first, and is thus
aligned to 64bytes without needing lots of padding
* Provide config options for desired features (including XSAVE
instruction variant) and required XSAVE region size. These
are checked at boot time to ensure the CPU meets these
requirements
The address being calculated is the end of the user context array.
There is no need for this to be done as a magic number offset
from the tcb_t, this commit takes an index into the actual array,
using the constant that is defined as the length of that array.
