652 lines
25 KiB
Text
652 lines
25 KiB
Text
/*
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* Copyright Linux Kernel Team
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* Copyright 2020, HENSOLDT Cyber GmbH
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*
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* This file is derived from an intermediate build stage of the
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* Linux kernel. The licenses of all input files to this process
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* are compatible with GPL-2.0-only.
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*/
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/dts-v1/;
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/ {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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model = "Boundary Devices i.MX6 SoloX Nitrogen6sx Board";
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compatible = "boundary,imx6sx-nitrogen6sx\0fsl,imx6sx";
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chosen {
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stdout-path = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000";
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};
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memory@80000000 {
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device_type = "memory";
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reg = < 0x80000000 0x40000000 >;
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = < 0x01 >;
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#size-cells = < 0x00 >;
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regulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "3P3V";
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regulator-min-microvolt = < 0x325aa0 >;
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regulator-max-microvolt = < 0x325aa0 >;
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regulator-always-on;
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phandle = < 0x35 >;
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};
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};
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aliases {
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gpio0 = "/soc/aips-bus@2000000/gpio@209c000";
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gpio1 = "/soc/aips-bus@2000000/gpio@20a0000";
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gpio2 = "/soc/aips-bus@2000000/gpio@20a4000";
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gpio3 = "/soc/aips-bus@2000000/gpio@20a8000";
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gpio4 = "/soc/aips-bus@2000000/gpio@20ac000";
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gpio5 = "/soc/aips-bus@2000000/gpio@20b0000";
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gpio6 = "/soc/aips-bus@2000000/gpio@20b4000";
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i2c0 = "/soc/aips-bus@2100000/i2c@21a0000";
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i2c1 = "/soc/aips-bus@2100000/i2c@21a4000";
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i2c2 = "/soc/aips-bus@2100000/i2c@21a8000";
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serial0 = "/soc/aips-bus@2000000/spba-bus@2000000/serial@2020000";
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serial1 = "/soc/aips-bus@2100000/serial@21e8000";
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serial2 = "/soc/aips-bus@2100000/serial@21ec000";
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serial3 = "/soc/aips-bus@2100000/serial@21f0000";
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serial4 = "/soc/aips-bus@2100000/serial@21f4000";
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serial5 = "/soc/aips-bus@2100000/serial@22a0000";
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ethernet0 = "/soc/aips-bus@2100000/ethernet@2188000";
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ethernet1 = "/soc/aips-bus@2100000/ethernet@21b4000";
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};
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cpus {
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#address-cells = < 0x01 >;
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#size-cells = < 0x00 >;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = < 0x00 >;
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next-level-cache = < 0x67 >;
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operating-points = < 0xf32a0 0x1312d0 0xc15c0 0x11edd8 0x60ae0 0x106738 0x30570 0xee098 >;
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fsl,soc-operating-points = < 0xf32a0 0x11edd8 0xc15c0 0x11edd8 0x60ae0 0x11edd8 0x30570 0x11edd8 >;
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clock-latency = < 0xee6c >;
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#cooling-cells = < 0x02 >;
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clocks = < 0x04 0x81 0x04 0x14 0x04 0x23 0x04 0x24 0x04 0x04 >; /* TODO: &clks */
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clock-names = "arm\0pll2_pfd2_396m\0step\0pll1_sw\0pll1_sys"; /* TODO */
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arm-supply = < 0x68 >;
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soc-supply = < 0x69 >;
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nvmem-cells = < 0xd1 >;
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nvmem-cell-names = "speed_grade";
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};
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};
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clocks {
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ckil {
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compatible = "fixed-clock";
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#clock-cells = < 0x00 >;
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clock-frequency = < 0x8000 >;
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clock-output-names = "ckil";
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phandle = < 0xd2 >;
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};
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osc {
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compatible = "fixed-clock";
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#clock-cells = < 0 >;
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clock-frequency = < 0x16e3600 >;
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clock-output-names = "osc";
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phandle = < 0xd3 >;
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};
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ipp_di0 {
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compatible = "fixed-clock";
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#clock-cells = < 0x00 >;
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clock-frequency = < 0x00 >;
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clock-output-names = "ipp_di0";
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phandle = < 0xd4 >;
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};
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ipp_di1 {
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compatible = "fixed-clock";
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#clock-cells = < 0x00 >;
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clock-frequency = < 0x00 >;
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clock-output-names = "ipp_di1";
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phandle = < 0xd5 >;
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};
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anaclk1 {
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compatible = "fixed-clock";
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#clock-cells = < 0x00 >;
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clock-frequency = < 0x00 >;
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clock-output-names = "anaclk1";
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phandle = < 0xd6 >;
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};
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anaclk2 {
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compatible = "fixed-clock";
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#clock-cells = < 0x00 >;
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clock-frequency = < 0x00 >;
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clock-output-names = "anaclk2";
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phandle = < 0xd7 >;
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};
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};
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soc {
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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compatible = "simple-bus";
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interrupt-parent = < 0x01 >;
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ranges;
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/* taken from seL4 sabre.dts */
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timer@a00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = < 0xa00600 0x20 >;
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interrupts = < 0x01 0x0d 0xf01 >;
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interrupt-parent = < 0x16 >;
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clocks = < 0x04 0x1e >;
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};
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interrupt-controller@a01000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = < 0x03 >;
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interrupt-controller;
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reg = < 0xa01000 0x1000 0xa00100 0x100 >;
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interrupt-parent = < 0x16 >;
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phandle = < 0x16 >;
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};
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l2-cache@a02000 {
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compatible = "arm,pl310-cache";
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reg = < 0x00a02000 0x1000 >;
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interrupts = < 0x00 0x5c 0x04 >;
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cache-unified;
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cache-level = < 0x02 >;
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arm,tag-latency = < 0x04 0x02 0x03 >;
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arm,data-latency = < 0x04 0x02 0x03 >;
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phandle = < 0x67 >;
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};
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aips-bus@2000000 {
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compatible = "fsl,aips-bus\0simple-bus";
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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reg = < 0x2000000 0x100000 >;
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ranges;
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spba-bus@2000000 {
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compatible = "fsl,spba-bus\0simple-bus";
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#address-cells = < 0x01 >;
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#size-cells = < 0x01 >;
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reg = < 0x2000000 0x40000 >;
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ranges;
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serial@2020000 {
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compatible = "fsl,imx6sx-uart\0fsl,imx6q-uart\0fsl,imx21-uart";
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reg = < 0x2020000 0x4000 >;
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interrupts = < 0x00 0x1a 0x04 >;
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clocks = < 0x04 0xcc 0x04 0xcd >;
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clock-names = "ipg\0per";
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dmas = < 0x17 0x19 0x04 0x00 0x17 0x1a 0x04 0x00 >;
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dma-names = "rx\0tx";
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pinctrl-names = "default";
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pinctrl-0 = < 0x1a >;
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status = "okay";
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};
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};
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gpt@2098000 {
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compatible = "fsl,imx6sx-gpt\0fsl,imx6dl-gpt\0fsl,imx31-gpt";
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reg = < 0x2098000 0x4000 >;
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interrupts = < 0x00 0x37 0x04 >;
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clocks = < 0x04 0x9a 0x04 0xe3 >;
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clock-names = "ipg\0per";
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};
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gpio@209c000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x209c000 0x4000 >;
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interrupts = < 0x00 0x42 0x04 0x00 0x43 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 5 26 >;
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phandle = < 0x43 >;
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};
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gpio@20a0000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x20a0000 0x4000 >;
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interrupts = < 0x00 0x44 0x04 0x00 0x45 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 31 20 >;
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phandle = < 0x37 >;
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};
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gpio@20a4000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x20a4000 0x4000 >;
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interrupts = < 0x00 0x46 0x04 0x00 0x47 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 51 29 >;
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phandle = < 0x18 >;
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};
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gpio@20a8000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x20a8000 0x4000 >;
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interrupts = < 0x00 0x48 0x04 0x00 0x49 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 80 32 >;
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phandle = < 0x76 >;
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};
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gpio@20ac000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x20ac000 0x4000 >;
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interrupts = < 0x00 0x4a 0x04 0x00 0x4b 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 112 24 >;
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};
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gpio@20b0000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x20b0000 0x4000 >;
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interrupts = < 0x00 0x4c 0x04 0x00 0x4d 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 136 12 0x22 12 158 11 >;
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phandle = < 0x40 >;
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};
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gpio@20b4000 {
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compatible = "fsl,imx6sx-gpio\0fsl,imx35-gpio";
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reg = < 0x20b4000 0x4000 >;
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interrupts = < 0x00 0x4e 0x04 0x00 0x4f 0x04 >;
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gpio-controller;
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#gpio-cells = < 0x02 >;
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interrupt-controller;
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#interrupt-cells = < 0x02 >;
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gpio-ranges = < 0x22 0 148 10 0x22 10 169 2 >;
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phandle = < 0x34 >;
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};
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ccm@20c4000 {
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compatible = "fsl,imx6sx-ccm";
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reg = < 0x20c4000 0x4000 >;
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interrupts = < 0x00 0x57 0x04 0x00 0x58 0x04 >;
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#clock-cells = < 0x01 >;
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clocks = < 0xd1 0xd2 0xd3 0xd4 0xd5 0xd6 0xd7 >;
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clock-names = "ckil", "osc", "ipp_di0", "ipp_di1", "anaclk1", "anaclk2";
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phandle = < 0x04 >;
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};
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src@20d8000 {
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compatible = "fsl,imx6sx-src\0fsl,imx51-src";
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reg = < 0x20d8000 0x4000 >;
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interrupts = < 0x00 0x5b 0x04 0x00 0x60 0x04 >;
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#reset-cells = < 0x01 >;
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phandle = < 0x1b >; /* TODO */
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};
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epit@20d0000 {
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reg = < 0x20d0000 0x4000 >;
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interrupts = < 0x00 0x38 0x04 >;
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};
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epit@20d4000 {
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reg = < 0x20d4000 0x4000 >;
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interrupts = < 0x00 0x39 0x04 >;
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};
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anatop@20c8000 {
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compatible = "fsl,imx6sx-anatop\0fsl,imx6q-anatop\0syscon\0simple-mfd";
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reg = < 0x20c8000 0x1000 >;
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interrupts = < 0x00 0x31 0x04 0x00 0x36 0x04 0x00 0x7f 0x04 >;
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phandle = < 0x02 >; /* TODO */
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regulator-vddcore {
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compatible = "fsl,anatop-regulator";
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regulator-name = "vddarm";
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regulator-min-microvolt = < 0xb1008 >;
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regulator-max-microvolt = < 0x162010 >;
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regulator-always-on;
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anatop-reg-offset = < 0x140 >;
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anatop-vol-bit-shift = < 0x00 >;
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anatop-vol-bit-width = < 0x05 >;
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anatop-delay-reg-offset = < 0x170 >;
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anatop-delay-bit-shift = < 0x18 >;
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anatop-delay-bit-width = < 0x02 >;
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anatop-min-bit-val = < 0x01 >;
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anatop-min-voltage = < 0xb1008 >;
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anatop-max-voltage = < 0x162010 >;
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phandle = < 0x68 >;
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};
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regulator-vddsoc {
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compatible = "fsl,anatop-regulator";
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regulator-name = "vddsoc";
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regulator-min-microvolt = < 0xb1008 >;
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regulator-max-microvolt = < 0x162010 >;
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regulator-always-on;
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anatop-reg-offset = < 0x140 >;
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anatop-vol-bit-shift = < 0x12 >;
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anatop-vol-bit-width = < 0x05 >;
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anatop-delay-reg-offset = < 0x170 >;
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anatop-delay-bit-shift = < 0x1c >;
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anatop-delay-bit-width = < 0x02 >;
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anatop-min-bit-val = < 0x01 >;
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anatop-min-voltage = < 0xb1008 >;
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anatop-max-voltage = < 0x162010 >;
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phandle = < 0x69 >;
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};
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};
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gpc@20dc000 {
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compatible = "fsl,imx6sx-gpc\0fsl,imx6q-gpc";
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reg = < 0x20dc000 0x4000 >;
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interrupt-controller;
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#interrupt-cells = < 0x03 >;
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interrupts = < 0x00 0x59 0x04 >;
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interrupt-parent = < 0x16 >;
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clocks = < 0x04 0x52 >;
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clock-names = "ipg";
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phandle = < 0x01 >;
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pgc {
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#address-cells = < 0x01 >;
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#size-cells = < 0x00 >;
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power-domain@0 {
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reg = < 0x00 >;
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#power-domain-cells = < 0x00 >;
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};
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power-domain@1 {
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reg = < 0x01 >;
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#power-domain-cells = < 0x00 >;
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power-supply = < 0x69 >;
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clocks = < 0x04 0x9c >;
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phandle = < 0x15 >;
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};
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power-domain@2 {
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reg = < 0x02 >;
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#power-domain-cells = < 0x00 >;
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clocks = < 0x04 0xaa 0x04 0xad 0x04 0xaf 0x04 0xa9 0x04 0xae 0x04 0x9f 0x04 0xd7 >;
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};
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power-domain@3 {
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reg = < 0x03 >;
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#power-domain-cells = < 0x00 >;
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power-supply = < 0x24 >;
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};
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};
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};
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iomuxc@20e0000 {
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compatible = "fsl,imx6sx-iomuxc";
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reg = <0x020e0000 0x4000>;
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pinctrl-names = "default";
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pinctrl-0 = < 0x2b >;
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phandle = < 0x22 >;
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imx6sx-nitrogen6 {
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hoggrp {
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fsl,pins = < 0x0144 0x048C 0x0000 0x5 0x0 0x1b0b0
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0x014C 0x0494 0x0000 0x5 0x0 0x1b0b0
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0x0170 0x04B8 0x0000 0x5 0x0 0x1b0b0
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0x0178 0x04C0 0x0000 0x5 0x0 0x1b0b0
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0x017C 0x04C4 0x0000 0x5 0x0 0x1b0b0
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0x0174 0x04BC 0x0000 0x5 0x0 0x1b0b0
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0x0180 0x04C8 0x0000 0x5 0x0 0x1b0b0
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0x0184 0x04CC 0x0000 0x5 0x0 0x1b0b0
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0x0188 0x04D0 0x0000 0x5 0x0 0x1b0b0
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0x018C 0x04D4 0x0000 0x5 0x0 0x1b0b0
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0x0224 0x056C 0x0000 0x7 0x0 0x000b0
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0x026C 0x05B4 0x0000 0x5 0x0 0x1b0b0
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0x0160 0x04A8 0x0000 0x5 0x0 0x1b0b0
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0x01A4 0x04EC 0x0000 0x5 0x0 0x1b0b0
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>;
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phandle = < 0x2b >;
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};
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uart1grp {
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fsl,pins = < 0x0024 0x036C 0x0000 0x0 0x0 0x1b0b1 0x0028 0x0370 0x0830 0x0 0x1 0x1b0b1 >;
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phandle = < 0x1a >;
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};
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i2c1grp {
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fsl,pins = < 0x0014 0x035C 0x07A8 0x0 0x1 0x4001b8b1 0x0018 0x0360 0x07AC 0x0 0x1 0x4001b8b1 >;
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phandle = < 0x38 >;
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};
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i2c2grp {
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fsl,pins = < 0x001C 0x0364 0x07B0 0x0 0x1 0x4001b8b1 0x0020 0x0368 0x07B4 0x0 0x1 0x4001b8b1 >;
|
|
phandle = < 0x3a >;
|
|
};
|
|
|
|
i2c3grp {
|
|
fsl,pins = < 0x00B4 0x03FC 0x07B8 0x2 0x2 0x4001b8b1 0x00C8 0x0410 0x07BC 0x2 0x2 0x4001b8b1 >;
|
|
phandle = < 0x45 >;
|
|
};
|
|
enetgrp {
|
|
fsl,pins = < 0x0088 0x03D0 0x0764 0x0 0x1 0x1b0b0 0x0084 0x03CC 0x0000 0x0 0x0 0x1b0b0 0x01D8 0x0520 0x0000 0x0 0x0 0x30b1 0x01DC 0x0524 0x0000 0x0 0x0 0x30b1 0x01E0 0x0528 0x0000 0x0 0x0 0x30b1 0x01E4 0x052C 0x0000 0x0 0x0 0x30b1 0x01EC 0x0534 0x0000 0x0 0x0 0x30b1 0x01E8 0x0530 0x0000 0x0 0x0 0x30b1 0x01C0 0x0508 0x0000 0x0 0x0 0x3081 0x01C4 0x050C 0x0000 0x0 0x0 0x3081 0x01D0 0x0518 0x0000 0x0 0x0 0x3081 0x01C8 0x0510 0x0000 0x0 0x0 0x3081 0x01CC 0x0514 0x0000 0x0 0x0 0x3081 0x01D4 0x051C 0x0768 0x0 0x1 0x3081 0x0098 0x03E0 0x0000 0x5 0x0 0xb0b0 0x008C 0x03D4 0x0000 0x5 0x0 0xb0b0 0x0090 0x03D8 0x0000 0x5 0x0 0xb0b0 >;
|
|
phandle = < 0x32 >;
|
|
};
|
|
enetgrp2 {
|
|
fsl,pins = < 0x0208 0x0550 0x0000 0x0 0x0 0x30b1 0x020C 0x0554 0x0000 0x0 0x0 0x30b1 0x0210 0x0558 0x0000 0x0 0x0 0x30b1 0x0214 0x055C 0x0000 0x0 0x0 0x30b1 0x021C 0x0564 0x0000 0x0 0x0 0x30b1 0x0218 0x0560 0x0000 0x0 0x0 0x30b1 0x01F0 0x0538 0x0000 0x0 0x0 0x3081 0x01F4 0x053C 0x0000 0x0 0x0 0x3081 0x0200 0x0548 0x0000 0x0 0x0 0x3081 0x01F8 0x0540 0x0000 0x0 0x0 0x3081 0x01FC 0x0544 0x0000 0x0 0x0 0x3081 0x0204 0x054C 0x0774 0x0 0x1 0x3081 0x0094 0x03DC 0x0000 0x5 0x0 0xb0b0 0x009C 0x03E4 0x0000 0x5 0x0 0xb0b0 0x00A0 0x03E8 0x0000 0x5 0x0 0xb0b0 >;
|
|
phandle = < 0x33 >;
|
|
};
|
|
};
|
|
};
|
|
|
|
iomuxc-gpr@20e4000 {
|
|
compatible = "fsl,imx6sx-iomuxc-gpr\0fsl,imx6q-iomuxc-gpr\0syscon";
|
|
reg = <0x020e4000 0x4000>;
|
|
phandle = < 0x05 >;
|
|
};
|
|
|
|
sdma@20ec000 {
|
|
compatible = "fsl,imx6sx-sdma\0fsl,imx6q-sdma";
|
|
reg = < 0x20ec000 0x4000 >;
|
|
interrupts = < 0x00 0x02 0x04 >;
|
|
clocks = < 0x04 0x52 0x04 0xc3 >;
|
|
clock-names = "ipg\0ahb";
|
|
#dma-cells = < 0x03 >;
|
|
/* imx6sx reuses imx6q sdma firmware */
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
|
phandle = < 0x17 >;
|
|
};
|
|
};
|
|
|
|
aips-bus@2100000 {
|
|
compatible = "fsl,aips-bus\0simple-bus";
|
|
#address-cells = < 0x01 >;
|
|
#size-cells = < 0x01 >;
|
|
reg = < 0x2100000 0x100000 >;
|
|
ranges;
|
|
|
|
ocotp@21bc000 {
|
|
#address-cells = < 0x01 >;
|
|
#size-cells = < 0x01 >;
|
|
compatible = "fsl,imx6sx-ocotp\0syscon";
|
|
reg = < 0x21bc000 0x4000 >;
|
|
clocks = < 0x04 0xa3 >;
|
|
|
|
cpu_speed_grade {
|
|
reg = < 0x10 4 >;
|
|
phandle = < 0xd1 >;
|
|
};
|
|
};
|
|
|
|
i2c@21a0000 {
|
|
#address-cells = < 0x01 >;
|
|
#size-cells = < 0x00 >;
|
|
compatible = "fsl,imx6sx-i2c\0fsl,imx21-i2c";
|
|
reg = < 0x21a0000 0x4000 >;
|
|
interrupts = < 0x00 0x24 0x04 >;
|
|
clocks = < 0x04 0xa0 >;
|
|
clock-frequency = < 0x186a0 >;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = < 0x38 >;
|
|
status = "okay";
|
|
|
|
/* ignored codec: sgtl5000@a */
|
|
};
|
|
|
|
i2c@21a4000 {
|
|
#address-cells = < 0x01 >;
|
|
#size-cells = < 0x00 >;
|
|
compatible = "fsl,imx6sx-i2c\0fsl,imx21-i2c";
|
|
reg = < 0x21a4000 0x4000 >;
|
|
interrupts = < 0x00 0x25 0x04 >;
|
|
clocks = < 0x04 0xa1 >;
|
|
clock-frequency = < 0x186a0 >;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = < 0x3a >;
|
|
phandle = < 0x10 >;
|
|
status = "okay";
|
|
};
|
|
|
|
i2c@21a8000 {
|
|
#address-cells = < 0x01 >;
|
|
#size-cells = < 0x00 >;
|
|
compatible = "fsl,imx6sx-i2c\0fsl,imx21-i2c";
|
|
reg = < 0x21a8000 0x4000 >;
|
|
interrupts = < 0x00 0x26 0x04 >;
|
|
clocks = < 0x04 0xa2 >;
|
|
clock-frequency = < 0x186a0 >;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = < 0x45 >;
|
|
status = "okay";
|
|
};
|
|
|
|
serial@21e8000 {
|
|
compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
|
|
reg = < 0x21e8000 0x4000 >;
|
|
interrupts = < 0x00 0x1b 0x04 >;
|
|
clocks = < 0x04 0xa0 0x04 0xa1 >;
|
|
clock-names = "ipg\0per";
|
|
dmas = < 0x17 0x1b 0x04 0x00 0x17 0x1c 0x04 0x00 >;
|
|
dma-names = "rx\0tx";
|
|
status = "okay";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = < 0x50 >;
|
|
};
|
|
|
|
serial@21ec000 {
|
|
compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
|
|
reg = < 0x21ec000 0x4000 >;
|
|
interrupts = < 0x00 0x1c 0x04 >;
|
|
clocks = < 0x04 0xa0 0x04 0xa1 >;
|
|
clock-names = "ipg\0per";
|
|
dmas = < 0x17 0x1d 0x04 0x00 0x17 0x1e 0x04 0x00 >;
|
|
dma-names = "rx\0tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@21f0000 {
|
|
compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
|
|
reg = < 0x21f0000 0x4000 >;
|
|
interrupts = < 0x00 0x1d 0x04 >;
|
|
clocks = < 0x04 0xa0 0x04 0xa1 >;
|
|
clock-names = "ipg\0per";
|
|
dmas = < 0x17 0x1f 0x04 0x00 0x17 0x20 0x04 0x00 >;
|
|
dma-names = "rx\0tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@21f4000 {
|
|
compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
|
|
reg = < 0x21f4000 0x4000 >;
|
|
interrupts = < 0x00 0x1e 0x04 >;
|
|
clocks = < 0x04 0xa0 0x04 0xa1 >;
|
|
clock-names = "ipg\0per";
|
|
dmas = < 0x17 0x21 0x04 0x00 0x17 0x22 0x04 0x00 >;
|
|
dma-names = "rx\0tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
serial@22a0000 {
|
|
compatible = "fsl,imx6q-uart\0fsl,imx21-uart";
|
|
reg = < 0x21f4000 0x4000 >;
|
|
interrupts = < 0x00 0x1e 0x04 >;
|
|
clocks = < 0x04 0xa0 0x04 0xa1 >;
|
|
clock-names = "ipg\0per";
|
|
dmas = < 0x17 0x21 0x04 0x00 0x17 0x22 0x04 0x00 >;
|
|
dma-names = "rx\0tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
ethernet@2188000 {
|
|
compatible = "fsl,imx6sx-fec\0fsl,imx6q-fec";
|
|
reg = < 0x2188000 0x4000 >;
|
|
interrupt-names = "int0\0pps";
|
|
interrupts = < 0x00 0x76 0x04 0x00 0x77 0x04 >;
|
|
clocks = < 0x04 0xac 0x04 0xe1 0x04 0xe4 0x04 0x11 0x04 0xe4 >;
|
|
clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out";
|
|
fsl,num-tx-queues = < 0x03 >;
|
|
fsl,num-rx-queues = < 0x03 >;
|
|
fsl,stop-mode = <0x05 0x10 0x03>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = < 0x32 >;
|
|
phy-mode = "rgmii";
|
|
phy-handle = < ðphy1 >;
|
|
phy-supply = < 0x35 >;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ethphy1: ethernet-phy@4 {
|
|
reg = <4>;
|
|
};
|
|
|
|
ethphy2: ethernet-phy@5 {
|
|
reg = <5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
ethernet@21b4000 {
|
|
compatible = "fsl,imx6sx-fec\0fsl,imx6q-fec";
|
|
reg = < 0x021b4000 0x4000 >;
|
|
interrupt-names = "int0\0pps";
|
|
interrupts = < 0x00 0x66 0x04 0x00 0x67 0x04 >;
|
|
clocks = < 0x04 0xac 0x04 0xe1 0x04 0xe4 0x04 0xe7 0x04 0xe4 >;
|
|
clock-names = "ipg\0ahb\0ptp\0enet_clk_ref\0enet_out";
|
|
fsl,stop-mode = < 0x05 0x10 0x04>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = < 0x33 >;
|
|
phy-mode = "rgmii";
|
|
phy-handle = < ðphy2 >;
|
|
phy-supply = < 0x35 >;
|
|
fsl,magic-packet;
|
|
status = "okay";
|
|
};
|
|
};
|
|
};
|
|
};
|