00a9ba9123
This register is visible to software executing at PL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at PL0. This also fixes a bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0. Signed-off-by: Kent McLeod <Kent.Mcleod@data61.csiro.au> |
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| .. | ||
| arch_include | ||
| include | ||
| mode_include | ||
| sel4_arch_include | ||
| sel4_plat_include | ||
| src | ||
| tools | ||
| CMakeLists.txt | ||