b544529615
Enable the timer only at initialization and since it is always enabled. It is not needed to be re-enabled. Signed-off-by: JorgeMVP <jorgepereira89@gmail.com>
61 lines
1.6 KiB
C
61 lines
1.6 KiB
C
/*
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* Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#pragma once
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#include <config.h>
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#include <mode/machine.h>
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/* ARM generic timer implementation */
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#ifdef CONFIG_KERNEL_MCS
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#include <model/statedata.h>
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#include <api/types.h>
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/** DONT_TRANSLATE **/
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static inline ticks_t getCurrentTime(void)
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{
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ticks_t time;
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SYSTEM_READ_64(CNT_CT, time);
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return time;
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}
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/** DONT_TRANSLATE **/
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static inline void setDeadline(ticks_t deadline)
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{
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assert(deadline >= NODE_STATE(ksCurTime));
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SYSTEM_WRITE_64(CNT_CVAL, deadline);
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}
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static inline void ackDeadlineIRQ(void)
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{
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ticks_t deadline = UINT64_MAX;
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setDeadline(deadline);
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/* Ensure that the timer deasserts the IRQ before GIC EOIR/DIR.
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* This is sufficient to remove the pending state from the GICR
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* and avoid the interrupt happening twice because of the level
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* sensitive configuration. */
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isb();
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}
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#else /* CONFIG_KERNEL_MCS */
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#include <arch/machine/timer.h>
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static inline void resetTimer(void)
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{
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SYSTEM_WRITE_WORD(CNT_TVAL, TIMER_RELOAD);
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/* Ensure that the timer deasserts the IRQ before GIC EOIR/DIR.
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* This is sufficient to remove the pending state from the GICR
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* and avoid the interrupt happening twice because of the level
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* sensitive configuration. */
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isb();
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}
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#endif /* !CONFIG_KERNEL_MCS */
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BOOT_CODE void initGenericTimer(void);
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#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
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static uint64_t read_cntpct(void) UNUSED;
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static void save_virt_timer(vcpu_t *vcpu);
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static void restore_virt_timer(vcpu_t *vcpu);
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#endif /* CONFIG_ARM_HYPERVISOR_SUPPORT */
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