Kent McLeod 8234026c1f aarch64: Move tpidrro_el0 from vcpu to tcb context ... This register is visible to software executing at EL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at EL0. This also fixes a potential bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0.		2019-09-19 11:39:14 +10:00
..
aarch32	mcs: add seL4_SchedContext_YieldTo	2019-08-22 11:22:38 +10:00
aarch64	aarch64: Move tpidrro_el0 from vcpu to tcb context	2019-09-19 11:39:14 +10:00
ia32	mcs: add seL4_SchedContext_YieldTo	2019-08-22 11:22:38 +10:00
riscv32	mcs: Update size constants for RISC-V	2019-08-27 10:46:13 +10:00
riscv64	mcs: Update size constants for RISC-V	2019-08-27 10:46:13 +10:00
x86_64	libsel4: Correct call for seL4_X86DangerousRDMSR	2019-08-22 13:24:52 +10:00
arm_hyp	Merge branch master into arm_hyp	2016-02-01 14:57:37 +11:00