375a98c8b3
The DTS compilation was arm platforms only. Moving it to the top level config file, making it available to RISCV platforms. The generated files are almost identical with minor differences. A new argument(--arch) is added to the hardware_gen.py for the differences.
56 lines
1.3 KiB
Text
56 lines
1.3 KiB
Text
/*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*
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* @TAG(OTHER_GPL)
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*/
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/dts-v1/;
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/ {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "ucbbar,spike-bare-dev";
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model = "ucbbar,spike-bare,qemu";
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chosen {
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bootargs = "";
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};
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cpus {
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#address-cells = <0x00000001>;
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#size-cells = <0x00000000>;
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timebase-frequency = <0x00989680>;
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cpu@0 {
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device_type = "cpu";
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reg = <0x00000000>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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mmu-type = "riscv,sv48";
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clock-frequency = <0x3b9aca00>;
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interrupt-controller {
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#interrupt-cells = <0x00000001>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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linux,phandle = <0x00000001>;
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phandle = <0x00000001>;
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};
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x00000000 0xfff00000>;
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};
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soc {
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#address-cells = <0x00000002>;
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#size-cells = <0x00000002>;
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compatible = "simple-bus";
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ranges;
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};
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htif {
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compatible = "ucb,htif0";
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};
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};
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