18a3fb3bae
At the end of the physical address range, the last address isn't turned into an UT object. The scripts generating the memory regions unnecessarily round down to a small page size when they could instead round down to the smallest UT size and this memory could be used for smaller kernel objects. Signed-off-by: Kent McLeod <kent@kry10.com>
112 lines
3.8 KiB
Python
112 lines
3.8 KiB
Python
#
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# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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#
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# SPDX-License-Identifier: GPL-2.0-only
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#
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from typing import List, Set
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from hardware.memory import Region
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class Config:
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''' Abstract config class '''
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arch = 'unknown'
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def __init__(self, addrspace_max):
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self.addrspace_max = addrspace_max
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def get_kernel_phys_align(self) -> int:
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''' Used to align the base of physical memory. Returns alignment size in bits. '''
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return 0
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def get_bootloader_reserve(self) -> int:
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''' Used to reserve a fixed amount of memory for the bootloader. Offsets
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the kernel load address by the amount returned in bytes. '''
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return 0
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def get_page_bits(self) -> int:
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''' Get page size in bits for this arch '''
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return 12 # 4096-byte pages
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def get_smallest_kernel_object_alignment(self) -> int:
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return 4 # seL4_MinUntypedBits is 4 for all configurations
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def get_device_page_bits(self) -> int:
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''' Get page size in bits for mapping devices for this arch '''
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return self.get_page_bits()
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def align_memory(self, regions: Set[Region]) -> List[Region]:
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''' Given a set of regions, sort them and align the first so that the
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ELF loader will be able to load the kernel into it. Will return the
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aligned memory region list, a set of any regions of memory that were
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aligned out and the physBase value that the kernel will use. memory
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region list, a set of any regions of memory that were aligned out and
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the physBase value that the kernel will use. '''
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pass
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class ARMConfig(Config):
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''' Config class for ARM '''
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SUPERSECTION_BITS = 24
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arch = 'arm'
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def get_kernel_phys_align(self) -> int:
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''' on ARM the ELF loader expects to be able to map a supersection page to load the kernel. '''
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return self.SUPERSECTION_BITS
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def align_memory(self, regions: Set[Region]) -> List[Region]:
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''' Arm wants physBase to be the physical load address of the kernel. '''
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ret = sorted(regions)
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extra_reserved = set()
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new = ret[0].align_base(self.get_kernel_phys_align())
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resv = Region(ret[0].base, new.base - ret[0].base, None)
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extra_reserved.add(resv)
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ret[0] = new
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physBase = ret[0].base
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return ret, extra_reserved, physBase
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class RISCVConfig(Config):
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''' Config class for RISCV '''
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MEGA_PAGE_SIZE = 0x200000
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arch = 'riscv'
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def get_bootloader_reserve(self) -> int:
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''' on RISC-V OpenSBI is loaded at the start
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of physical memory. Mark it as unavailable. '''
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return self.MEGA_PAGE_SIZE
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def align_memory(self, regions: Set[Region]) -> List[Region]:
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''' Currently the RISC-V port expects physBase to be the address that the
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bootloader is loaded at. To be generalised in the future. '''
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ret = sorted(regions)
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extra_reserved = set()
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physBase = ret[0].base
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resv = Region(ret[0].base, self.get_bootloader_reserve(), None)
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extra_reserved.add(resv)
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ret[0].base += self.get_bootloader_reserve()
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ret[0].size -= self.get_bootloader_reserve()
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return ret, extra_reserved, physBase
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def get_device_page_bits(self) -> int:
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''' Get page size in bits for mapping devices for this arch '''
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if self.addrspace_max > (1 << 32):
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# rv39 and rv48 use 2MiB device pages
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return 21
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else:
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# rv32 uses 4MiB device pages
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return 22
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def get_arch_config(arch: str, addrspace_max: int) -> Config:
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''' Return an appropriate Config object for the given architecture '''
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if arch == 'arm':
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return ARMConfig(addrspace_max)
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elif arch == 'riscv':
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return RISCVConfig(addrspace_max)
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raise ValueError('Unsupported arch specified.')
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