Kent McLeod 8234026c1f aarch64: Move tpidrro_el0 from vcpu to tcb context ... This register is visible to software executing at EL0 but not writeable. Storing it in the VCPU context required custom save/restore handling as it had to be explicitly handled when switching from a VCPU thread to a non-VCPU thread so that it didn't become a channel. It is possible to now update this register via seL4_TCB_WriteRegisters for software executing at EL0. This also fixes a potential bug where if a vcpu-thread is switched for a non-vcpu-thread and then switched to a different vcpu-thread the original vcpu-thread's copy of this register will get set to 0.		2019-09-19 11:39:14 +10:00
..
__init__.py	python2 --> python3	2019-08-08 10:19:24 +10:00
bitfield_gen.py	Release snapshot	2014-07-18 05:03:59 +10:00
changed.sh	Release snapshot	2014-07-18 05:03:59 +10:00
invocation_header_gen.py	Release snapshot	2014-07-18 05:03:59 +10:00
sel4_idl.dtd	manual: Added <docref> XML Tag to Doxygen	2018-05-01 12:28:03 +10:00
syscall_header_gen.py	Release snapshot	2014-07-18 05:03:59 +10:00
syscall_stub_gen.py	aarch64: Move tpidrro_el0 from vcpu to tcb context	2019-09-19 11:39:14 +10:00
xmllint.sh	Release snapshot	2014-07-18 05:03:59 +10:00