seL4/include/arch
Julia Vassiliki 3977e12b8b arm,gic-v3: fix GICD_CTLR_ARE_NS bit value
This reverts https://github.com/seL4/seL4/pull/1490 as the
change that was made in that PR was reading the wrong part
of the GIC specification, because ARM decided that the
register layouts are different in non-secure vs secure mode.

Fixes (again) https://github.com/seL4/seL4/issues/1489

Signed-off-by: Julia Vassiliki <julia.vassiliki@unsw.edu.au>
2025-10-30 13:20:40 +00:00
..
arm arm,gic-v3: fix GICD_CTLR_ARE_NS bit value 2025-10-30 13:20:40 +00:00
riscv/arch Make fastpath_restore match restore_user_context 2025-10-09 10:31:01 +01:00
x86/arch Make fastpath_restore match restore_user_context 2025-10-09 10:31:01 +01:00