512a0200de
All the kernel header files now use pargma once rather than the ifndef, as the pre-processed C files do not change while header files are protected with pargma once. This will also solve any naming issues caused by ifndef.
573 lines
15 KiB
C
573 lines
15 KiB
C
/*
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* Copyright 2014, General Dynamics C4 Systems
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#pragma once
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#include <config.h>
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#include <stdint.h>
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#include <arch/types.h>
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#include <arch/object/structures.h>
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#include <arch/machine/hardware.h>
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#include <plat/machine/hardware.h>
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#include <armv/machine.h>
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#include <arch/model/smp.h>
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#include <machine/io.h>
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#include <mode/machine_pl2.h>
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#include <mode/hardware.h>
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#include <kernel/stack.h>
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/* The new spec requires the use of vmsr/vmrs to access floating point
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* registers (including control registers).
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*
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* GCC will still accept the old MRC/MCR instructions but Clang will not.
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* Both result in the same encoding and are here only to satisfy compilers. */
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#define VMRS(vfp_reg, v) asm volatile(".fpu vfp\n" \
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"vmrs %0, " vfp_reg : "=r"(v))
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#define VMSR(vfp_reg, v) \
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do { \
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word_t _v = v; \
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asm volatile(".fpu vfp\n" \
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"vmsr " vfp_reg ", %0" :: "r"(_v)); \
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} while(0)
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/* VFP registers. */
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#define FPEXC "fpexc" /* 32-bit Floating-Point Exception Control register */
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#define FPSCR "fpscr" /* 32-bit Floating-Point Status and Control register */
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/** Generic timer CP15 registers **/
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#define CNTFRQ " p15, 0, %0, c14, c0, 0" /* 32-bit RW Counter Frequency register */
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#define CNTPCT " p15, 0, %Q0, %R0, c14 " /* 64-bit RO Physical Count register */
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#define CNTKCTL " p15, 0, %0, c14, c1, 0" /* 32-bit RW Timer PL1 Control register */
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#define CNTP_TVAL " p15, 0, %0, c14, c2, 0" /* 32-bit RW PL1 Physical TimerValue register */
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#define CNTP_CTL " p15, 0, %0, c14, c2, 1" /* 32-bit RW PL1 Physical Timer Control register */
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#define CNTV_TVAL " p15, 0, %0, c14, c3, 0" /* 32-bit RW Virtual TimerValue register */
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#define CNTV_CTL " p15, 0, %0, c14, c3, 1" /* 32-bit RW Virtual Timer Control register */
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#define CNTVCT " p15, 1, %Q0, %R0, c14 " /* 64-bit RO Virtual Count register */
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#define CNTP_CVAL " p15, 2, %Q0, %R0, c14 " /* 64-bit RW PL1 Physical Timer CompareValue register */
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#define CNTV_CVAL " p15, 3, %Q0, %R0, c14 " /* 64-bit RW Virtual Timer CompareValue register */
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#define CNTVOFF " p15, 4, %Q0, %R0, c14 " /* 64-bit RW Virtual Offset register */
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#define CNTHCTL " p15, 4, %0, c14, c1, 0" /* 32-bit RW Timer PL2 Control register */
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#define CNTHP_TVAL " p15, 4, %0, c14, c2, 0" /* 32-bit RW PL2 Physical TimerValue register */
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#define CNTHP_CTL " p15, 4, %0, c14, c2, 1" /* 32-bit RW PL2 Physical Timer Control register */
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#define CNTHP_CVAL " p15, 6, %Q0, %R0, c14 " /* 64-bit RW PL2 Physical Timer CompareValue register */
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#define PMUSERENR " p15, 0, %0, c9, c14, 0" /* 32-bit RW PMU PL0 enable */
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#define ID_DFR0 " p15, 0, %0, c0, c1, 2" /* 32-bit RO Debug feature register */
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#define ID_PFR1 " p15, 0, %0, c0, c1, 1" /* 32-bit RO CPU feature register */
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#define CPACR " p15, 0, %0, c1, c0, 2" /* 32-bit Architectural Feature Access Control Register */
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#define VMPIDR " p15, 4, %0, c0, c0, 5" /* 32-bit RW Virtualization Multiprocessor ID Register */
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/* Use Hypervisor Physical timer */
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#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
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#define CNT_TVAL CNTHP_TVAL
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#define CNT_CT CNTPCT
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#define CNT_CTL CNTHP_CTL
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#define CNT_CVAL CNTHP_CVAL
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#else
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/* Use virtual timer */
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#define CNT_TVAL CNTV_TVAL
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#define CNT_CT CNTVCT
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#define CNT_CTL CNTV_CTL
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#define CNT_CVAL CNTV_CVAL
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#endif
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#ifdef ENABLE_SMP_SUPPORT
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/* Use the first two SGI (Software Generated Interrupt) IDs
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* for seL4 IPI implementation. SGIs are per-core banked.
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*/
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#define irq_remote_call_ipi 0
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#define irq_reschedule_ipi 1
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#endif /* ENABLE_SMP_SUPPORT */
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word_t PURE getRestartPC(tcb_t *thread);
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void setNextPC(tcb_t *thread, word_t v);
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/* Architecture specific machine operations */
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static inline word_t getProcessorID(void)
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{
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word_t processor_id;
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MRC("p15, 0, %0, c0, c0, 0", processor_id);
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return processor_id;
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}
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static inline word_t readSystemControlRegister(void)
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{
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word_t scr;
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MRC("p15, 0, %0, c1, c0, 0", scr);
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return scr;
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}
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static inline void writeSystemControlRegister(word_t scr)
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{
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MCR("p15, 0, %0, c1, c0, 0", scr);
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}
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static inline word_t readAuxiliaryControlRegister(void)
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{
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word_t acr;
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MRC("p15, 0, %0, c1, c0, 1", acr);
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return acr;
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}
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static inline void writeAuxiliaryControlRegister(word_t acr)
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{
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MCR("p15, 0, %0, c1, c0, 1", acr);
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}
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/** MODIFIES: [*] */
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/** DONT_TRANSLATE */
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static inline void clearExMonitor(void)
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{
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word_t tmp;
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asm volatile("strex r0, r1, [%0]" : : "r"(&tmp) : "r0");
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}
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static inline void flushBTAC(void)
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{
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asm volatile("mcr p15, 0, %0, c7, c5, 6" : : "r"(0));
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}
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static inline void writeContextID(word_t id)
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{
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if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
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writeContextIDPL2(id);
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} else {
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asm volatile("mcr p15, 0, %0, c13, c0, 1" : : "r"(id));
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isb();
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}
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}
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/* Address space control */
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static inline word_t readTTBR0(void)
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{
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word_t val = 0;
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asm volatile("mrc p15, 0, %0, c2, c0, 0":"=r"(val):);
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return val;
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}
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static inline void writeTTBR0(word_t val)
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{
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asm volatile("mcr p15, 0, %0, c2, c0, 0":: "r"(val));
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}
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static inline void writeTTBR0Ptr(paddr_t addr)
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{
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/* Mask supplied address (retain top 19 bits). Set the lookup cache bits:
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* outer write-back cacheable, no allocate on write, inner non-cacheable.
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*/
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writeTTBR0((addr & 0xffffe000) | 0x18);
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}
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static inline word_t readTTBR1(void)
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{
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word_t val = 0;
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asm volatile("mrc p15, 0, %0, c2, c0, 1":"=r"(val):);
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return val;
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}
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static inline void writeTTBR1(word_t val)
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{
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asm volatile("mcr p15, 0, %0, c2, c0, 1":: "r"(val));
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}
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static inline word_t readTTBCR(void)
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{
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word_t val = 0;
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asm volatile("mrc p15, 0, %0, c2, c0, 2":"=r"(val):);
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return val;
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}
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static inline void writeTTBCR(word_t val)
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{
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asm volatile("mcr p15, 0, %0, c2, c0, 2":: "r"(val));
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}
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static inline void writeTPIDRURW(word_t reg)
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{
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#ifdef CONFIG_KERNEL_GLOBALS_FRAME
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armKSGlobalsFrame[GLOBALS_TPIDRURW] = reg;
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#else
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asm volatile("mcr p15, 0, %0, c13, c0, 2" :: "r"(reg));
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#endif
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}
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static inline word_t readTPIDRURW(void)
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{
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#ifdef CONFIG_KERNEL_GLOBALS_FRAME
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return armKSGlobalsFrame[GLOBALS_TPIDRURW];
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#else
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word_t reg;
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asm volatile("mrc p15, 0, %0, c13, c0, 2" : "=r"(reg));
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return reg;
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#endif
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}
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static inline void writeTPIDRPRW(word_t reg)
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{
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asm volatile("mcr p15, 0, %0, c13, c0, 4" :: "r"(reg));
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}
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static inline word_t readTPIDRPRW(void)
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{
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word_t reg;
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asm volatile("mrc p15, 0, %0, c13, c0, 4" :"=r"(reg));
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return reg;
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}
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static void arm_save_thread_id(tcb_t *thread)
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{
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#ifndef CONFIG_KERNEL_GLOBALS_FRAME
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/* TPIDRURW is writeable from EL0 but not with globals frame. */
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setRegister(thread, TPIDRURW, readTPIDRURW());
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#endif /* CONFIG_KERNEL_GLOBALS_FRAME */
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}
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static void arm_load_thread_id(tcb_t *thread)
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{
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writeTPIDRURW(getRegister(thread, TPIDRURW));
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}
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static inline word_t readMPIDR(void)
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{
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word_t reg;
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asm volatile("mrc p15, 0, %0, c0, c0, 5" : "=r"(reg));
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return reg;
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}
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static inline void writeDACR(word_t reg)
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{
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asm volatile("mcr p15, 0, %0, c3, c0, 0" :: "r"(reg));
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}
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static inline word_t readDACR(void)
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{
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word_t reg;
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asm volatile("mrc p15, 0, %0, c3, c0, 0" : "=r"(reg));
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return reg;
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}
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static inline void setCurrentPD(paddr_t addr)
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{
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/* Before changing the PD ensure all memory stores have completed */
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if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
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setCurrentPDPL2(addr);
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} else {
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dsb();
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writeTTBR0Ptr(addr);
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/* Ensure the PD switch completes before we do anything else */
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isb();
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}
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}
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static inline void setKernelStack(word_t stack_address)
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{
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#ifndef CONFIG_ARCH_ARM_V6
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/* Setup kernel stack pointer.
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* Load the (per-core) kernel stack pointer to TPIDRPRW for faster reloads on traps.
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*/
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if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
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writeHTPIDR(stack_address);
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} else {
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writeTPIDRPRW(stack_address);
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}
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#endif /* CONFIG_ARCH_ARM_V6 */
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}
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static inline word_t getKernelStack(void)
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{
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#ifndef CONFIG_ARCH_ARM_V6
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if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
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return readHTPIDR();
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} else {
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return readTPIDRPRW();
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}
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#else
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return ((word_t) kernel_stack_alloc[0]) + BIT(CONFIG_KERNEL_STACK_BITS);
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#endif /* CONFIG_ARCH_ARM_V6 */
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}
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#ifdef ENABLE_SMP_SUPPORT
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static inline word_t getHWCPUID(void)
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{
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/* See ARM Referce Manual (ARMv7-A and ARMv7-R edition), Section B4.1.106
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* for more details about MPIDR register.
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*/
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return readMPIDR() & 0xff;
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}
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#endif /* ENABLE_SMP_SUPPORT */
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/* TLB control */
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static inline void invalidateLocalTLB(void)
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{
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dsb();
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asm volatile("mcr p15, 0, %0, c8, c7, 0" : : "r"(0));
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dsb();
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isb();
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}
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static inline void invalidateLocalTLB_ASID(hw_asid_t hw_asid)
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{
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if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
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invalidateLocalTLB();
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} else {
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dsb();
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asm volatile("mcr p15, 0, %0, c8, c7, 2" : : "r"(hw_asid));
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dsb();
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isb();
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}
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}
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static inline void invalidateLocalTLB_VAASID(word_t mva_plus_asid)
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{
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if (config_set(CONFIG_ARM_HYPERVISOR_SUPPORT)) {
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invalidateLocalTLB();
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} else {
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dsb();
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asm volatile("mcr p15, 0, %0, c8, c7, 1" : : "r"(mva_plus_asid));
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dsb();
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isb();
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}
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}
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void lockTLBEntry(vptr_t vaddr);
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static inline void cleanByVA(vptr_t vaddr, paddr_t paddr)
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{
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#ifdef CONFIG_ARM_CORTEX_A8
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/* Erratum 586324 -- perform a dummy cached load before flushing. */
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asm volatile("ldr r0, [sp]" : : : "r0");
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/* Erratum 586320 -- clean twice with interrupts disabled. */
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#else
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#endif
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/* Erratum 586323 - end with DMB to ensure the write goes out. */
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dmb();
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}
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/* D-Cache clean to PoU (L2 cache) (v6/v7 common) */
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static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr)
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{
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#ifdef CONFIG_ARM_CORTEX_A8
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/* Erratum 586324 -- perform a dummy cached load before flushing. */
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asm volatile("ldr r0, [sp]" : : : "r0");
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asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr));
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#elif defined(CONFIG_ARCH_ARM_V6)
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/* V6 doesn't distinguish PoU and PoC, so use the basic flush. */
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#elif defined(CONFIG_PLAT_EXYNOS5)
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/* Flush to coherency for table walks... Why? */
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#elif defined(CONFIG_PLAT_IMX7)
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#elif defined(CONFIG_PLAT_TK1)
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#elif defined(CONFIG_ARM_CORTEX_A53)
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asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
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#else
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asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr));
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#endif
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/* Erratum 586323 - end with DMB to ensure the write goes out. */
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dmb();
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}
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/* D-Cache invalidate to PoC (v6/v7 common) */
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static inline void invalidateByVA(vptr_t vaddr, paddr_t paddr)
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{
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#ifdef CONFIG_ARM_CORTEX_A8
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/* Erratum 586324 -- perform a dummy cached load before flushing. */
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asm volatile("ldr r0, [sp]" : : : "r0");
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asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r"(vaddr));
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#else
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asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r"(vaddr));
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#endif
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dmb();
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}
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/* I-Cache invalidate to PoU (L2 cache) (v6/v7 common) */
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static inline void invalidateByVA_I(vptr_t vaddr, paddr_t paddr)
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{
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#ifdef CONFIG_ARM_CORTEX_A8
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/* On A8, we just invalidate the lot. */
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asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r"(0));
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#else
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asm volatile("mcr p15, 0, %0, c7, c5, 1" : : "r"(vaddr));
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#endif
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isb();
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}
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/* I-Cache invalidate all to PoU (L2 cache) (v6/v7 common) */
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static inline void invalidate_I_PoU(void)
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{
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#ifdef CONFIG_ARM_CORTEX_A8
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/* Erratum 586324 -- perform a dummy cached load before flushing. */
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asm volatile("ldr r0, [sp]" : : : "r0");
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#endif
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asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r"(0));
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isb();
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}
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/* D-Cache clean & invalidate to PoC (v6/v7 common) */
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static inline void cleanInvalByVA(vptr_t vaddr, paddr_t paddr)
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{
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#ifdef CONFIG_ARM_CORTEX_A8
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/* Erratum 586324 -- perform a dummy cached load before flushing. */
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asm volatile("ldr r0, [sp]" : : : "r0");
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/* Erratum 586320 -- clean twice with interrupts disabled. */
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asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r"(vaddr));
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asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r"(vaddr));
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#else
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asm volatile("mcr p15, 0, %0, c7, c14, 1" : : "r"(vaddr));
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#endif
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dsb();
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}
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/* Invalidate branch predictors by VA (v6/v7 common) */
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static inline void branchFlush(vptr_t vaddr, paddr_t paddr)
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{
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asm volatile("mcr p15, 0, %0, c7, c5, 7" : : "r"(vaddr));
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}
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/* Fault status */
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static inline word_t PURE getIFSR(void)
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{
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word_t IFSR;
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asm volatile("mrc p15, 0, %0, c5, c0, 1" : "=r"(IFSR));
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return IFSR;
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}
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static inline void setIFSR(word_t ifsr)
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{
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asm volatile("mcr p15, 0, %0, c5, c0, 1" : : "r"(ifsr));
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}
|
|
|
|
static inline word_t PURE getDFSR(void)
|
|
{
|
|
word_t DFSR;
|
|
asm volatile("mrc p15, 0, %0, c5, c0, 0" : "=r"(DFSR));
|
|
return DFSR;
|
|
}
|
|
|
|
static inline void setDFSR(word_t dfsr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c5, c0, 0" : : "r"(dfsr));
|
|
}
|
|
|
|
static inline word_t PURE getADFSR(void)
|
|
{
|
|
word_t ADFSR;
|
|
asm volatile("mrc p15, 0, %0, c5, c1, 0" : "=r"(ADFSR));
|
|
return ADFSR;
|
|
}
|
|
|
|
static inline void setADFSR(word_t adfsr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c5, c1, 0" : : "r"(adfsr));
|
|
}
|
|
|
|
static inline word_t PURE getAIFSR(void)
|
|
{
|
|
word_t AIFSR;
|
|
asm volatile("mrc p15, 0, %0, c5, c1, 1" : "=r"(AIFSR));
|
|
return AIFSR;
|
|
}
|
|
|
|
static inline void setAIFSR(word_t aifsr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c5, c1, 1" : : "r"(aifsr));
|
|
}
|
|
|
|
static inline word_t PURE getDFAR(void)
|
|
{
|
|
word_t DFAR;
|
|
asm volatile("mrc p15, 0, %0, c6, c0, 0" : "=r"(DFAR));
|
|
return DFAR;
|
|
}
|
|
|
|
static inline void setDFAR(word_t dfar)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c6, c0, 0" : : "r"(dfar));
|
|
}
|
|
|
|
static inline word_t PURE getIFAR(void)
|
|
{
|
|
word_t IFAR;
|
|
asm volatile("mrc p15, 0, %0, c6, c0, 2" : "=r"(IFAR));
|
|
return IFAR;
|
|
}
|
|
|
|
static inline void setIFAR(word_t ifar)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c6, c0, 2" : : "r"(ifar));
|
|
}
|
|
|
|
static inline word_t getPRRR(void)
|
|
{
|
|
word_t PRRR;
|
|
asm volatile("mrc p15, 0, %0, c10, c2, 0" : "=r"(PRRR));
|
|
return PRRR;
|
|
}
|
|
|
|
static inline void setPRRR(word_t prrr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c10, c2, 0" : : "r"(prrr));
|
|
}
|
|
|
|
static inline word_t getNMRR(void)
|
|
{
|
|
word_t NMRR;
|
|
asm volatile("mrc p15, 0, %0, c10, c2, 1" : "=r"(NMRR));
|
|
return NMRR;
|
|
}
|
|
|
|
static inline void setNMRR(word_t nmrr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c10, c2, 1" : : "r"(nmrr));
|
|
}
|
|
|
|
static inline word_t PURE getFAR(void)
|
|
{
|
|
word_t FAR;
|
|
asm volatile("mrc p15, 0, %0, c6, c0, 0" : "=r"(FAR));
|
|
return FAR;
|
|
}
|
|
|
|
static inline word_t getCIDR(void)
|
|
{
|
|
word_t CIDR;
|
|
asm volatile("mrc p15, 0, %0, c13, c0, 1" : "=r"(CIDR));
|
|
return CIDR;
|
|
}
|
|
|
|
static inline void setCIDR(word_t cidr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c13, c0, 1" : : "r"(cidr));
|
|
}
|
|
|
|
static inline word_t getACTLR(void)
|
|
{
|
|
word_t ACTLR;
|
|
asm volatile("mrc p15, 0, %0, c1, c0, 1" : "=r"(ACTLR));
|
|
return ACTLR;
|
|
}
|
|
|
|
static inline void setACTLR(word_t actlr)
|
|
{
|
|
asm volatile("mcr p15, 0, %0, c1, c0, 1" :: "r"(actlr));
|
|
}
|
|
|
|
void arch_clean_invalidate_caches(void);
|
|
void arch_clean_invalidate_L1_caches(word_t type);
|