seL4/include/arch
Adrian Danis 93bca86e40 x86: Introduce support for XSAVE feature set
The XSAVE feature set is the future proof way for x86 CPUs to
manage extended CPU state. Extended state is MMX, FPU, SSE, AVX etc
registers. This is a replacement for the current FXSAVE and the
512 byte FPU region.

XSAVE introduces a few problems that this commit has to address

* The alignment of the XSAVE region is 64bytes, instead of the 16
  bytes of the FXSAVE region
* XSAVE region size is dependent on the desired features, which
  are detected at run time
* There are multiple variants of the XSAVE instruction that have
  different potential optimizations, but are not always supported

The solutions to these are

* Re-order the FPU state and user registers in the user context
  struct so that the new XSAVE region is first, and is thus
  aligned to 64bytes without needing lots of padding
* Provide config options for desired features (including XSAVE
  instruction variant) and required XSAVE region size. These
  are checked at boot time to ensure the CPU meets these
  requirements
2016-06-02 11:06:37 +10:00
..
arm Merge pull request #192 in SEL4/sel4 from ~HALMATARY/sel4:feature/syscall_bench2 to master 2016-06-02 00:53:20 +00:00
x86/arch x86: Introduce support for XSAVE feature set 2016-06-02 11:06:37 +10:00