a39c9b6a76
This change alters RISC-V fault handling to pass all non-VM faults as user exceptions. As we cannot guarantee what the hardware will send us in the scause register, we must handle all possible values. It also makes fault handling more consistent with other architectures in c_traps.c. |
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| .. | ||
| arm | ||
| riscv/arch | ||
| x86/arch | ||