79da079239
This commit also converts our own copyright headers to directly use SPDX, but leaves all other copyright header intact, only adding the SPDX ident. As far as possible this commit also merges multiple Data61 copyright statements/headers into one for consistency.
303 lines
9.4 KiB
C
303 lines
9.4 KiB
C
/*
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* Copyright 2014, General Dynamics C4 Systems
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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/*
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* ARM Generic Interrupt Controller PL-390
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*/
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#ifndef __ARCH_MACHINE_GIC_V2_H
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#define __ARCH_MACHINE_GIC_V2_H
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/* tell the kernel we have the set trigger feature */
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#define HAVE_SET_TRIGGER 1
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#include <stdint.h>
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#include <util.h>
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#include <linker.h>
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#include <mode/smp/smp.h>
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#include <model/statedata.h>
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#include "gic_common.h"
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#define IRQ_MASK MASK(10u)
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/* Helpers for VGIC */
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#define VGIC_HCR_EOI_INVALID_COUNT(hcr) (((hcr) >> 27) & 0x1f)
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#define VGIC_HCR_VGRP1DIE (1U << 7)
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#define VGIC_HCR_VGRP1EIE (1U << 6)
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#define VGIC_HCR_VGRP0DIE (1U << 5)
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#define VGIC_HCR_VGRP0EIE (1U << 4)
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#define VGIC_HCR_NPIE (1U << 3)
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#define VGIC_HCR_LRENPIE (1U << 2)
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#define VGIC_HCR_UIE (1U << 1)
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#define VGIC_HCR_EN (1U << 0)
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#define VGIC_MISR_VGRP1D VGIC_HCR_VGRP1DIE
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#define VGIC_MISR_VGRP1E VGIC_HCR_VGRP1EIE
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#define VGIC_MISR_VGRP0D VGIC_HCR_VGRP0DIE
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#define VGIC_MISR_VGRP0E VGIC_HCR_VGRP0EIE
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#define VGIC_MISR_NP VGIC_HCR_NPIE
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#define VGIC_MISR_LRENP VGIC_HCR_LRENPIE
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#define VGIC_MISR_U VGIC_HCR_UIE
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#define VGIC_MISR_EOI VGIC_HCR_EN
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#define VGIC_VTR_NLISTREGS(vtr) ((((vtr) >> 0) & 0x3f) + 1)
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#define VGIC_VTR_NPRIOBITS(vtr) ((((vtr) >> 29) & 0x07) + 1)
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#define VGIC_VTR_NPREBITS(vtr) ((((vtr) >> 26) & 0x07) + 1)
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/* Memory map for GIC distributor */
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struct gic_dist_map {
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uint32_t enable; /* 0x000 */
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uint32_t ic_type; /* 0x004 */
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uint32_t dist_ident; /* 0x008 */
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uint32_t res1[29]; /* [0x00C, 0x080) */
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uint32_t security[32]; /* [0x080, 0x100) */
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uint32_t enable_set[32]; /* [0x100, 0x180) */
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uint32_t enable_clr[32]; /* [0x180, 0x200) */
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uint32_t pending_set[32]; /* [0x200, 0x280) */
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uint32_t pending_clr[32]; /* [0x280, 0x300) */
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uint32_t active[32]; /* [0x300, 0x380) */
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uint32_t res2[32]; /* [0x380, 0x400) */
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uint32_t priority[255]; /* [0x400, 0x7FC) */
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uint32_t res3; /* 0x7FC */
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uint32_t targets[255]; /* [0x800, 0xBFC) */
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uint32_t res4; /* 0xBFC */
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uint32_t config[64]; /* [0xC00, 0xD00) */
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uint32_t spi[32]; /* [0xD00, 0xD80) */
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uint32_t res5[20]; /* [0xD80, 0xDD0) */
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uint32_t res6; /* 0xDD0 */
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uint32_t legacy_int; /* 0xDD4 */
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uint32_t res7[2]; /* [0xDD8, 0xDE0) */
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uint32_t match_d; /* 0xDE0 */
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uint32_t enable_d; /* 0xDE4 */
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uint32_t res8[70]; /* [0xDE8, 0xF00) */
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uint32_t sgi_control; /* 0xF00 */
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uint32_t res9[3]; /* [0xF04, 0xF10) */
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uint32_t sgi_pending_clr[4]; /* [0xF10, 0xF20) */
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uint32_t res10[40]; /* [0xF20, 0xFC0) */
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uint32_t periph_id[12]; /* [0xFC0, 0xFF0) */
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uint32_t component_id[4]; /* [0xFF0, 0xFFF] */
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};
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/* Memory map for GIC cpu interface */
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struct gic_cpu_iface_map {
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uint32_t icontrol; /* 0x000 */
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uint32_t pri_msk_c; /* 0x004 */
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uint32_t pb_c; /* 0x008 */
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uint32_t int_ack; /* 0x00C */
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uint32_t eoi; /* 0x010 */
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uint32_t run_priority; /* 0x014 */
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uint32_t hi_pend; /* 0x018 */
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uint32_t ns_alias_bp_c; /* 0x01C */
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uint32_t ns_alias_ack; /* 0x020 GIC400 only */
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uint32_t ns_alias_eoi; /* 0x024 GIC400 only */
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uint32_t ns_alias_hi_pend; /* 0x028 GIC400 only */
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uint32_t res1[5]; /* [0x02C, 0x040) */
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uint32_t integ_en_c; /* 0x040 PL390 only */
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uint32_t interrupt_out; /* 0x044 PL390 only */
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uint32_t res2[2]; /* [0x048, 0x050) */
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uint32_t match_c; /* 0x050 PL390 only */
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uint32_t enable_c; /* 0x054 PL390 only */
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uint32_t res3[30]; /* [0x058, 0x0FC) */
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uint32_t active_priority[4]; /* [0x0D0, 0xDC] GIC400 only */
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uint32_t ns_active_priority[4]; /* [0xE0,0xEC] GIC400 only */
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uint32_t res4[3];
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uint32_t cpu_if_ident; /* 0x0FC */
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uint32_t res5[948]; /* [0x100. 0xFC0) */
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uint32_t periph_id[8]; /* [0xFC0, 9xFF0) PL390 only */
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uint32_t component_id[4]; /* [0xFF0, 0xFFF] PL390 only */
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};
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extern volatile struct gic_dist_map *const gic_dist;
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extern volatile struct gic_cpu_iface_map *const gic_cpuiface;
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/* Helpers */
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static inline int is_irq_edge_triggered(word_t irq)
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{
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int word = irq >> 4;
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int bit = ((irq & 0xf) * 2);
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return !!(gic_dist->config[word] & BIT(bit + 1));
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}
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static inline void dist_pending_clr(word_t irq)
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{
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int word = IRQ_REG(irq);
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int bit = IRQ_BIT(irq);
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/* Using |= here is detrimental to your health */
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gic_dist->pending_clr[word] = BIT(bit);
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}
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static inline void dist_enable_clr(word_t irq)
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{
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int word = IRQ_REG(irq);
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int bit = IRQ_BIT(irq);
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/* Using |= here is detrimental to your health */
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gic_dist->enable_clr[word] = BIT(bit);
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}
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static inline void dist_enable_set(word_t irq)
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{
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int word = IRQ_REG(irq);
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int bit = IRQ_BIT(irq);
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gic_dist->enable_set[word] = BIT(bit);
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}
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static inline irq_t getActiveIRQ(void)
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{
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irq_t irq;
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if (!IS_IRQ_VALID(active_irq[CURRENT_CPU_INDEX()])) {
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active_irq[CURRENT_CPU_INDEX()] = gic_cpuiface->int_ack;
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}
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if (IS_IRQ_VALID(active_irq[CURRENT_CPU_INDEX()])) {
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irq = CORE_IRQ_TO_IRQT(CURRENT_CPU_INDEX(), active_irq[CURRENT_CPU_INDEX()] & IRQ_MASK);
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} else {
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irq = irqInvalid;
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}
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return irq;
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}
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/*
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* GIC has 4 states: pending->active(+pending)->inactive
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* seL4 expects two states: active->inactive.
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* We ignore the active state in GIC to conform
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*/
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static inline bool_t isIRQPending(void)
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{
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return IS_IRQ_VALID(gic_cpuiface->hi_pend);
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}
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static inline void maskInterrupt(bool_t disable, irq_t irq)
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{
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#if defined ENABLE_SMP_SUPPORT && defined CONFIG_ARCH_ARM
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assert(!(IRQ_IS_PPI(irq)) || (IRQT_TO_CORE(irq) == getCurrentCPUIndex()));
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#endif
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if (disable) {
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dist_enable_clr(IRQT_TO_IRQ(irq));
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} else {
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dist_enable_set(IRQT_TO_IRQ(irq));
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}
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}
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static inline void ackInterrupt(irq_t irq)
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{
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assert(IS_IRQ_VALID(active_irq[CURRENT_CPU_INDEX()])
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&& (active_irq[CURRENT_CPU_INDEX()] & IRQ_MASK) == IRQT_TO_IRQ(irq));
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if (is_irq_edge_triggered(IRQT_TO_IRQ(irq))) {
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dist_pending_clr(IRQT_TO_IRQ(irq));
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}
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gic_cpuiface->eoi = active_irq[CURRENT_CPU_INDEX()];
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active_irq[CURRENT_CPU_INDEX()] = IRQ_NONE;
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}
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#ifdef CONFIG_ARM_HYPERVISOR_SUPPORT
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/* GIC VCPU Control Interface */
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struct gich_vcpu_ctrl_map {
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uint32_t hcr; /* 0x000 RW 0x00000000 Hypervisor Control Register */
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uint32_t vtr; /* 0x004 RO IMPLEMENTATION DEFINED VGIC Type Register */
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/* Save restore on VCPU switch */
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uint32_t vmcr; /* 0x008 RW IMPLEMENTATION DEFINED Virtual Machine Control Register */
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uint32_t res1[1];
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/* IRQ pending flags */
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uint32_t misr; /* 0x010 RO 0x00000000 Maintenance Interrupt Status Register */
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uint32_t res2[3];
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/* Bitfield of list registers that have EOI */
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uint32_t eisr0; /* 0x020 RO 0x00000000 End of Interrupt Status Registers 0 and 1, see EISRn */
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uint32_t eisr1; /* 0x024 RO 0x00000000 */
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uint32_t res3[2];
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/* Bitfield of list registers that are empty */
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uint32_t elsr0; /* 0x030 RO IMPLEMENTATION DEFINED a */
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uint32_t elsr1; /* 0x034 RO IMPLEMENTATION DEFINED a Empty List Register Status Registers 0 and 1, see ELRSRn */
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uint32_t res4[46];
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/* Active priority: bitfield of active priorities */
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uint32_t apr; /* 0x0F0 RW 0x00000000 Active Priorities Register */
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uint32_t res5[3];
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uint32_t lr[64]; /* 0x100 RW 0x00000000 List Registers 0-63, see LRn */
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};
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extern volatile struct gich_vcpu_ctrl_map *gic_vcpu_ctrl;
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extern unsigned int gic_vcpu_num_list_regs;
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static inline uint32_t get_gic_vcpu_ctrl_hcr(void)
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{
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return gic_vcpu_ctrl->hcr;
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}
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static inline void set_gic_vcpu_ctrl_hcr(uint32_t hcr)
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{
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gic_vcpu_ctrl->hcr = hcr;
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}
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static inline uint32_t get_gic_vcpu_ctrl_vmcr(void)
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{
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return gic_vcpu_ctrl->vmcr;
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}
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static inline void set_gic_vcpu_ctrl_vmcr(uint32_t vmcr)
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{
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gic_vcpu_ctrl->vmcr = vmcr;
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}
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static inline uint32_t get_gic_vcpu_ctrl_apr(void)
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{
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return gic_vcpu_ctrl->apr;
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}
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static inline void set_gic_vcpu_ctrl_apr(uint32_t apr)
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{
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gic_vcpu_ctrl->apr = apr;
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}
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static inline uint32_t get_gic_vcpu_ctrl_vtr(void)
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{
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return gic_vcpu_ctrl->vtr;
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}
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static inline uint32_t get_gic_vcpu_ctrl_eisr0(void)
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{
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return gic_vcpu_ctrl->eisr0;
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}
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static inline uint32_t get_gic_vcpu_ctrl_eisr1(void)
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{
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return gic_vcpu_ctrl->eisr1;
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}
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static inline uint32_t get_gic_vcpu_ctrl_misr(void)
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{
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return gic_vcpu_ctrl->misr;
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}
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static inline virq_t get_gic_vcpu_ctrl_lr(int num)
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{
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virq_t virq;
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virq.words[0] = gic_vcpu_ctrl->lr[num];
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return virq;
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}
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static inline void set_gic_vcpu_ctrl_lr(int num, virq_t lr)
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{
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gic_vcpu_ctrl->lr[num] = lr.words[0];
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}
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#endif /* End of CONFIG_ARM_HYPERVISOR_SUPPORT */
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#endif /* !__ARCH_MACHINE_GIC_V2_H */
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