seL4/include/arch
Bill Nguyen 744104654d x86/vcpu: expose VMX-preemption timer scale MSR
Currently, the kernel permits userspace VMMs to enable and use the
VMX-preemption timer by allowing writes to the following VMCS fields:
- VMX_GUEST_PREEMPTION_TIMER_VALUE (count)
- VMX_CONTROL_PIN_EXECUTION_CONTROLS (timer enable bit)
- VMX_CONTROL_EXIT_CONTROLS (save current count on context switch bit)

It also forwards the timer expiry event as a VM exit.

But it does not tell userspace how fast the timer will count down,
making it impossible to use. This commit exposes the timer's scale
via `seL4_X86_VCPU_ReadMSR`.

Signed-off-by: Bill Nguyen <bill.nguyen@unsw.edu.au>
2026-05-09 10:54:59 +02:00
..
arm aarch64,fpu,hyp: do not trap CPACR_EL1 acceses 2026-03-10 12:19:42 +00:00
riscv/arch bf structs: eliminate BF_CANONICAL_RANGE #ifdefs 2026-01-09 09:00:43 +11:00
x86/arch x86/vcpu: expose VMX-preemption timer scale MSR 2026-05-09 10:54:59 +02:00