897aaf5b13
The SBI memory was mapped outside the kernel window. This would trigger an instruction access fault on some hardware, when the bootloader has set up PMP to protect the SBI memory. Instead of protecting a particular memory region, the PMP locks the entire page table entry that covers the region. The PADDR_LOAD and kernel base are adjusted to have the SBI memory included in the kernel window. So that the SBI memory can be mapped as part of the kernel image to a separate page table entry. This also avoids the kernel to allocate untyped memory from the SBI region.
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
/*
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* Copyright 2018, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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* ABN 41 687 119 230.
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*
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* Copyright 2018, DornerWorks
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*
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* This software may be distributed and modified according to the terms of
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* the GNU General Public License version 2. Note that NO WARRANTY is provided.
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* See "LICENSE_GPLv2.txt" for details.
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*
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* @TAG(DATA61_DORNERWORKS_GPL)
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*/
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/*
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*
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* Copyright 2016, 2017 Hesham Almatary, Data61/CSIRO <hesham.almatary@data61.csiro.au>
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* Copyright 2015, 2016 Hesham Almatary <heshamelmatary@gmail.com>
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*/
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#ifndef __ARCH_MODEL_STATEDATA_H
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#define __ARCH_MODEL_STATEDATA_H
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#include <config.h>
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#include <types.h>
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#include <util.h>
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#include <object/structures.h>
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#include <arch/types.h>
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#include <plat/machine/devices.h>
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NODE_STATE_BEGIN(archNodeState)
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/* TODO: add RISCV-dependent fields here */
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/* Bitmask of all cores should receive the reschedule IPI */
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NODE_STATE_DECLARE(word_t, ipiReschedulePending);
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NODE_STATE_END(archNodeState);
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extern asid_pool_t *riscvKSASIDTable[BIT(asidHighBits)];
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/* Kernel Page Tables */
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extern pte_t kernel_root_pageTable[BIT(PT_INDEX_BITS)] VISIBLE;
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/* We need to introduce a level2 pagetable in order to map the BBL to a separate
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* page entry to avoid PMP exception. */
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#if __riscv_xlen != 32
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extern pte_t kernel_image_level2_pt[BIT(PT_INDEX_BITS)];
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#endif
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#endif
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