bfb45ec550
Only call the command on CMake files that may be the first file evaluated from the project. Remove from all other files. Signed-off-by: Kent McLeod <kent@kry10.com>
313 lines
11 KiB
CMake
313 lines
11 KiB
CMake
#
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# Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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#
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# SPDX-License-Identifier: GPL-2.0-only
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#
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if(KernelSel4ArchAarch32)
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set_property(
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TARGET kernel_config_target
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APPEND
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PROPERTY TOPLEVELTYPES pde_C
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)
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endif()
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set(KernelArmPASizeBits40 OFF)
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set(KernelArmPASizeBits44 OFF)
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if(KernelArmCortexA35)
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set(KernelArmICacheVIPT ON)
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set(KernelArmPASizeBits40 ON)
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math(EXPR KernelPaddrUserTop "(1 << 40)")
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elseif(KernelArmCortexA53)
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set(KernelArmICacheVIPT ON)
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set(KernelArmPASizeBits40 ON)
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math(EXPR KernelPaddrUserTop "(1 << 40)")
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elseif(KernelArmCortexA55)
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set(KernelArmICacheVIPT ON)
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set(KernelArmPASizeBits40 ON)
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math(EXPR KernelPaddrUserTop "(1 << 40)")
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elseif(KernelArmCortexA57)
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set(KernelArmPASizeBits44 ON)
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math(EXPR KernelPaddrUserTop "(1 << 44)")
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elseif(KernelArmCortexA72)
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# For Cortex-A72 in AArch64 state, the physical address range is 44 bits
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# (https://developer.arm.com/documentation/100095/0001/memory-management-unit/about-the-mmu)
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set(KernelArmPASizeBits44 ON)
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math(EXPR KernelPaddrUserTop "(1 << 44)")
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endif()
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config_set(KernelArmPASizeBits40 ARM_PA_SIZE_BITS_40 "${KernelArmPASizeBits40}")
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config_set(KernelArmPASizeBits44 ARM_PA_SIZE_BITS_44 "${KernelArmPASizeBits44}")
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config_set(KernelArmICacheVIPT ARM_ICACHE_VIPT "${KernelArmICacheVIPT}")
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if(KernelSel4ArchAarch32)
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# 64-bit targets may be building in 32-bit mode,
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# so make sure maximum paddr is 32-bit.
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math(EXPR KernelPaddrUserTop "(1 << 32) - 1")
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endif()
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include(src/arch/arm/armv/armv7-a/config.cmake)
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include(src/arch/arm/armv/armv8-a/config.cmake)
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config_option(
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KernelDebugDisableL2Cache DEBUG_DISABLE_L2_CACHE
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"Do not enable the L2 cache on startup for debugging purposes."
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DEFAULT OFF
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DEPENDS "KernelArchARM"
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)
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config_option(
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KernelDebugDisableL1ICache DEBUG_DISABLE_L1_ICACHE
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"Do not enable the L1 instruction cache on startup for debugging purposes."
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DEFAULT OFF
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DEPENDS "KernelArchARM;KernelDebugDisableL2Cache"
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)
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config_option(
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KernelDebugDisableL1DCache DEBUG_DISABLE_L1_DCACHE
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"Do not enable the L1 data cache on startup for debugging purposes."
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DEFAULT OFF
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DEPENDS "KernelArchARM;KernelDebugDisableL2Cache"
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)
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config_option(
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KernelDebugDisableBranchPrediction
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DEBUG_DISABLE_BRANCH_PREDICTION
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"Do not enable branch prediction (also called program flow control) on startup. \
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This makes execution time more deterministic at the expense of dramatically decreasing \
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performance. Primary use is for debugging."
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DEFAULT OFF
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DEPENDS "KernelArchARM"
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)
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if(NOT DEFINED KernelSel4ArchArmHyp)
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# the current CMake scripts ensure that KernelSel4ArchArmHyp is always set
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# to either ON or OFF. If it is not set, something is either broken or the
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# CMake files are used wrongly. Or support for KernelSel4ArchArmHyp has
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# finally been removed - and then this check here should be removed and the
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# KernelArmHypervisorSupport below can be OFF by default.
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message(FATAL_ERROR "KernelSel4ArchArmHyp must be ON or OFF")
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endif()
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config_option(
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KernelArmHypervisorSupport ARM_HYPERVISOR_SUPPORT
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"Build as Hypervisor. Utilise ARM virtualisation extensions to build the kernel as a hypervisor"
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DEFAULT ${KernelSel4ArchArmHyp}
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DEPENDS
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"KernelArmCortexA15 OR KernelArmCortexA35 OR KernelArmCortexA57 OR KernelArmCortexA53 OR KernelArmCortexA55 OR KernelArmCortexA72"
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)
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config_option(KernelArmGicV3 ARM_GIC_V3_SUPPORT "Build support for GICv3" DEFAULT OFF)
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if(KernelArmPASizeBits40 AND ARM_HYPERVISOR_SUPPORT)
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config_set(KernelAarch64VspaceS2StartL1 AARCH64_VSPACE_S2_START_L1 "ON")
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else()
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config_set(KernelAarch64VspaceS2StartL1 AARCH64_VSPACE_S2_START_L1 "OFF")
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endif()
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config_option(
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KernelArmHypEnableVCPUCP14SaveAndRestore
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ARM_HYP_ENABLE_VCPU_CP14_SAVE_AND_RESTORE
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"Trap, but don't save/restore VCPUs' CP14 accesses \
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This allows us to turn off the save and restore of VCPU threads' CP14 \
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context for performance (or other) reasons, we can just turn them off \
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and trap them instead, and have the VCPUs' accesses to CP14 \
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intercepted and delivered to the VM Monitor as fault messages"
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DEFAULT ON
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DEPENDS "KernelSel4ArchArmHyp;NOT KernelVerificationBuild"
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DEFAULT_DISABLED OFF
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)
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config_option(
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KernelArmErrata430973
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ARM_ERRATA_430973
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"Enable workaround for 430973 Cortex-A8 (r1p0..r1p2) erratum \
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Enables a workaround for the 430973 Cortex-A8 (r1p0..r1p2) erratum. Error occurs \
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if code containing ARM/Thumb interworking branch is replaced by different code \
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at the same virtual address."
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DEFAULT OFF
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DEPENDS "KernelArchARM;KernelArmCortexA8"
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)
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config_option(
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KernelArmErrata773022
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ARM_ERRATA_773022
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"Enable workaround for 773022 Cortex-A15 (r0p0..r0p4) erratum \
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Enables a workaround for the 773022 Cortex-A15 (r0p0..r0p4) erratum. Error occurs \
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on rare sequences of instructions and results in the loop buffer delivering \
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incorrect instructions. The work around is to disable the loop buffer"
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DEFAULT ON
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DEPENDS "KernelArchARM;KernelArmCortexA15"
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DEFAULT_DISABLED OFF
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)
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config_option(
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KernelArmSMMU ARM_SMMU "Enable SystemMMU"
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DEFAULT ON
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DEPENDS "KernelPlatformTx2"
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DEFAULT_DISABLED OFF
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)
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config_option(
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KernelTk1SMMU TK1_SMMU "Enable SystemMMU for the Tegra TK1 SoC"
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DEFAULT OFF
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DEPENDS "KernelPlatformTK1"
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)
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config_option(
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KernelArmEnableA9Prefetcher
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ENABLE_A9_PREFETCHER
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"Enable Cortex-A9 prefetcher \
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Cortex-A9 has an L1 and L2 prefetcher. By default \
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they are disabled. This config options allows \
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them to be turned on. Enabling the prefetchers \
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requires that the kernel be in secure mode. ARM \
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documents indicate that as of r4p1 version of \
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Cortex-A9 the bits used to enable the prefetchers \
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no longer exist, it is not clear if this is just \
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a document error or not."
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DEFAULT OFF
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DEPENDS "KernelArmCortexA9"
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)
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config_option(
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KernelArmExportPMUUser
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EXPORT_PMU_USER
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"PL0 access to PMU. \
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Grant user access to Performance Monitoring Unit. \
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WARNING: While useful for evaluating performance, \
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this option opens timing and covert channels."
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DEFAULT OFF
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DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;NOT KernelArmCortexA8"
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)
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config_option(
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KernelArmDisableWFIWFETraps DISABLE_WFI_WFE_TRAPS "Disable the trapping of WFI \
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and WFE instructions when configuring the \
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Hyp Configuration Registor (HCR) of a VCPU"
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DEFAULT OFF
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DEPENDS "KernelArchArmV7a OR KernelArchArmV8a;KernelArmHypervisorSupport"
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)
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config_option(
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KernelTk1SMMUInterruptEnable
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SMMU_INTERRUPT_ENABLE
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"Enable SMMU interrupts. \
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SMMU interrupts currently only serve a debug purpose as \
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they are not forwarded to user level. Enabling this will \
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cause some fault types to print out a message in the kernel. \
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WARNING: Printing fault information is slow and rapid faults \
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can result in all time spent in the kernel printing fault \
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messages"
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DEFAULT "${KernelDebugBuild}"
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DEPENDS "KernelTk1SMMU"
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DEFAULT_DISABLED OFF
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)
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config_option(
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KernelAArch32FPUEnableContextSwitch
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AARCH32_FPU_ENABLE_CONTEXT_SWITCH
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"Enable hardware VFP and SIMD context switch \
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This enables the VFP and SIMD context switch on platforms with \
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hardware support, allowing the user to execute hardware VFP and SIMD \
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operations in a multithreading environment, instead of relying on \
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software emulation of FPU/VFP from the C library (e.g. mfloat-abi=soft)."
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DEFAULT ON
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DEPENDS "KernelSel4ArchAarch32"
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DEFAULT_DISABLED OFF
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)
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config_option(
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KernelAArch64UserCacheEnable
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AARCH64_USER_CACHE_ENABLE
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"Enable any attempt to execute a DC CVAU, DC CIVAC, DC CVAC, or IC IVAU \
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instruction or access to CTR_EL0 at EL0 using AArch64. \
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When disabled, these operations will be trapped."
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DEFAULT ON
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DEPENDS "KernelSel4ArchAarch64"
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)
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config_option(
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KernelAArch64SErrorIgnore
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AARCH64_SERROR_IGNORE
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"By default any SError interrupt will halt the kernel. SErrors may \
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be caused by e.g. writes to read-only device registers or ECC errors. \
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When this option is enabled SErrors will be ignored."
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DEFAULT OFF
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DEPENDS "KernelSel4ArchAarch64;NOT KernelVerificationBuild"
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)
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mark_as_advanced(KernelAArch64SErrorIgnore)
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config_option(
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KernelAllowSMCCalls
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ALLOW_SMC_CALLS
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"Allow components to make SMC calls. \
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WARNING: Allowing SMC calls causes a couple of issues. Since seL4 cannot \
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pre-empt the secure monitor, the WCET is no longer guaranteed. Also, since the \
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secure monitor is a higher privilege level and can make any change in the \
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system, the proofs can no longer be guaranteed."
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DEFAULT OFF
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DEPENDS "KernelSel4ArchAarch64"
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)
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config_choice(
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KernelArmTLSReg
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ARM_TLS_REG
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"Which TLS register is used for Kernel TLS syscalls and invocations. \
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The usual registers used by gnu-elf ABIs are: \
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- on aarch32: tpidruro \
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- on aarch64: tpidru."
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"tpidru;KernelArmTLSRegTPIDRU;ARM_TLS_REG_TPIDRU;KernelArchARM"
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"tpidruro;KernelArmTLSRegTPIDRURO;ARM_TLS_REG_TPIDRURO;KernelArchARM"
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)
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if(KernelArmTLSRegTPIDRURO)
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set(KernelSetTLSBaseSelf ON)
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endif()
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if(KernelAArch32FPUEnableContextSwitch OR KernelSel4ArchAarch64)
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set(KernelHaveFPU ON)
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endif()
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if(KernelArmCortexA7
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OR KernelArmCortexA8
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OR KernelArmCortexA15
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OR KernelArmCortexA35
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OR KernelArmCortexA53
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OR KernelArmCortexA55
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OR KernelArmCortexA57
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OR KernelArmCortexA72
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)
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# According to https://developer.arm.com/documentation/100095/0001/functional-description/about-the-cortex-a72-processor-functions/components-of-the-processor
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# the L1 instruction on the Cortex-A72 cache has a 64-byte cache line.
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# Thus, 6 bits are needed.
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config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "6")
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elseif(KernelArmCortexA9)
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config_set(KernelArmCacheLineSizeBits L1_CACHE_LINE_SIZE_BITS "5")
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endif()
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if(KernelArmCortexA8)
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config_set(KernelArmHasTlbLock ARM_HAS_TLB_LOCK ON)
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else()
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config_set(KernelArmHasTlbLock ARM_HAS_TLB_LOCK OFF)
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endif()
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add_sources(
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DEP "KernelArchARM"
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PREFIX src/arch/arm
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CFILES c_traps.c
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api/faults.c
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benchmark/benchmark.c
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kernel/boot.c
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kernel/thread.c
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machine/cache.c
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machine/errata.c
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machine/debug.c
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machine/hardware.c
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machine/io.c
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object/interrupt.c
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object/tcb.c
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object/iospace.c
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object/vcpu.c
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object/smmu.c
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object/smc.c
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smp/ipi.c
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)
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add_bf_source_old("KernelArchARM" "structures.bf" "include/arch/arm" "arch/object")
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include(src/arch/arm/${KernelWordSize}/config.cmake)
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