437 lines
20 KiB
C
437 lines
20 KiB
C
/*
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* Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#pragma once
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#include <plat/machine/devices_gen.h>
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/*the paddr address of the TX2 SMMU*/
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#define SMMU_TX2_PADDR 0x12000000
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#define SMMU_PAGE_4KB 0x1000
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#define SMMU_PAGE_64KB 0x10000
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/*the high-level physical address layout according to SMMU definition*/
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#define SMMU_GLOBAL_SIZE(num_page, page_size) ((num_page) * (page_size))
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#define SMMU_CB_SIZE(num_page, page_size) ((num_page) * (page_size))
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#define SMMU_CB_BASE_PADDR(global_size) (SMMU_TX2_PADDR + (global_size))
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/*SMMU's physical address space layout, defined by SMMU v2 standard*/
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#define SMMU_GR0_PADDR SMMU_TX2_PADDR
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#define SMMU_GR1_PADDR(page_size) ((SMMU_GR0_PADDR) + 1 * (page_size))
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#define SMMU_GID_PADDR(page_size) ((SMMU_GR0_PADDR) + 2 * (page_size))
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#define SMMU_PM_PADDR(page_size) ((SMMU_GR0_PADDR) + 3 * (page_size))
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#define SMMU_SSD_PADDR(page_size) ((SMMU_GR0_PADDR) + 4 * (page_size))
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#define SMMU_CBn_PADDR(cb_base, n ,page_size) ((cb_base) + n * (page_size))
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/* SMMU's virtual address space layout in kernel address space,
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* mapped by boot code.*/
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#define SMMU_GR0_PPTR SMMU_PPTR
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#define SMMU_GR1_PPTR (SMMU_PPTR + 1 * (SMMU_PAGE_4KB))
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#define SMMU_GID_PPTR (SMMU_PPTR + 2 * (SMMU_PAGE_4KB))
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#define SMMU_PM_PPTR (SMMU_PPTR + 3 * (SMMU_PAGE_4KB))
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#define SMMU_SSD_PPTR (SMMU_PPTR + 4 * (SMMU_PAGE_4KB))
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#define SSMU_CB_BASE_PPTR (SMMU_PPTR + 5 * (SMMU_PAGE_4KB))
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#define SMMU_CBn_BASE_PPTR(n) ((SSMU_CB_BASE_PPTR) + (n) * (SMMU_PAGE_4KB))
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/*global register space 0 registers*/
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#define SMMU_sCR0 0x000
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#define SMMU_SCR1 0x004
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#define SMMU_sCR2 0x008
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#define SMMU_sACR 0x010
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#define SMMU_IDR0 0x020
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#define SMMU_IDR1 0x024
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#define SMMU_IDR2 0x028
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#define SMMU_IDR3 0x02c
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#define SMMU_IDR4 0x030
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#define SMMU_IDR5 0x034
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#define SMMU_IDR6 0x038
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#define SMMU_IDR7 0x03c
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#define SMMU_sGFAR 0x040
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#define SMMU_sGFSR 0x048
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#define SMMU_sGFSRRESTORE 0x04c
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#define SMMU_sGFSYNR0 0x050
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#define SMMU_sGFSYNR1 0x054
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#define SMMU_sGFSYNR2 0x058
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#define SMMU_STLBIALL 0x060
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#define SMMU_TLBIVMID 0x064
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#define SMMU_TLBIALLNSNH 0x068
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#define SMMU_TLBIALLH 0x06c
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#define SMMU_sTLBGSYNC 0x070
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#define SMMU_sTLBGSTATUS 0x074
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#define SMMU_TLBIVAH 0x078
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#define SMMU_STLBIVALM 0x0a0
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#define SMMU_STLBIVAM 0x0a8
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#define SMMU_TLBIVALH64 0x0b0
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#define SMMU_TLBIVMIDS1 0x0b8
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#define SMMU_STLBIALLM 0x0bc
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#define SMMU_TLBIVAH64 0x0c0
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#define SMMU_sGATS1UR 0x100
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#define SMMU_sGATS1UW 0x108
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#define SMMU_sGATS1PR 0x110
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#define SMMU_sGATS1PW 0x118
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#define SMMU_sGATS12UR 0x120
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#define SMMU_sGATS12UW 0x128
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#define SMMU_sGATS12PR 0x130
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#define SMMU_sGATS12PW 0x138
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#define SMMU_sGPAR 0x180
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#define SMMU_sGATSR 0x188
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/*SMMU_SMRn, stream matching register 0 to 127*/
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#define SMMU_SMRn(n) (0x800 + (n) * 0x4)
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/*SMMU_S2CRn, stream-to-context register 0 to 127*/
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#define SMMU_S2CRn(n) (0xc00 + (n) * 0x4)
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/*global register space 1*/
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/*SMMU_CBARn, context bank attribute register 0 to 127*/
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#define SMMU_CBARn(n) (0x000 + (n) * 0x4)
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/*SMMU_CBFRSYNRAn, context bank fault restricted syndrome register A 0 to 127*/
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#define SMMU_CBFRSYNRAn(n) (0x400 + (n) * 0x4)
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/*SMMU_CBA2Rn, context bank attribute registers 0 to 127*/
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#define SMMU_CBA2Rn(n) (0x800 + (n) * 0x4)
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/*stage 1 and stage 2 translation context bank address space*/
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#define SMMU_CBn_SCTLR 0x000
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#define SMMU_CBn_ACTLR 0x004
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#define SMMU_CBn_RESUME 0x008
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#define SMMU_CBn_TCR2 0x010
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#define SMMU_CBn_TTBR0 0x020
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#define SMMU_CBn_TTBR1 0x028
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#define SMMU_CBn_TCR 0x030
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#define SMMU_CBn_CONTEXTIDR 0x034
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/*the SMMU_CBn_MAIRm registers are used for AArch32 Long-descriptor or the AArch64*/
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#define SMMU_CBn_MAIR0 0x038
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#define SMMU_CBn_MAIR1 0x03c
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/*the SMMU_CBn_PRRR and SMMU_CBn_NMRR registers are used for AArch32*/
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#define SMMU_CBn_PRRR 0x038
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#define SMMU_CBn_NMRR 0x03c
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#define SMMU_CBn_PAR 0x050
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#define SMMU_CBn_FSR 0x058
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#define SMMU_CBn_FSRRESTORE 0x05c
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#define SMMU_CBn_FAR 0x060
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#define SMMU_CBn_FSYNR0 0x068
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#define SMMU_CBn_FSYNR1 0x06c
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#define SMMU_CBn_IPAFAR 0x070
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#define SMMU_CBn_TLBIVA 0x600
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#define SMMU_CBn_TLBIVAA 0x608
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#define SMMU_CBn_TLBIASID 0x610
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#define SMMU_CBn_TLBIALL 0x618
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#define SMMU_CBn_TLBIVAL 0x620
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#define SMMU_CBn_TLBIVAAL 0x628
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#define SMMU_CBn_TLBIIPAS2 0x630
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#define SMMU_CBn_TLBIIPAS2L 0x638
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#define SMMU_CBn_TLBSYNC 0x7f0
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#define SMMU_CBn_TLBSTATUS 0x7f4
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/*SMMU_CR0 non-secure register 0 bit assignments*/
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#define CR0_VMID16EN BIT(31)
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#define CR0_HYPMODE BIT(30)
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#define CR0_WACFG(v) ((v) & 0x3 << 26)
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#define CR0_RACFG(v) ((v) & 0x3 << 24)
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#define CR0_SHCFG(v) ((v) & 0x3 << 22)
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#define CR0_SMCFCFG BIT(21)
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#define CR0_MTCFG BIT(20)
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#define CR0_MemAttr(v) ((v) & 0xf << 16)
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#define CR0_BSU(v) ((v) & 0x3 << 14)
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#define CR0_FB BIT(13)
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#define CR0_PTM BIT(12)
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#define CR0_VMIDPNE BIT(11)
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#define CR0_USFCFG BIT(10)
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#define CR0_GSE BIT(9)
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#define CR0_STALLD BIT(8)
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#define CR0_TRANSIENTCFG(v) ((v) & 0x3 << 6)
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#define CR0_GCFGFIE BIT(5)
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#define CR0_GCFGFRE BIT(4)
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#define CR0_EXIDENABLE BIT(3)
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#define CR0_GFIE BIT(2)
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#define CR0_GFRE BIT(1)
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#define CR0_CLIENTPD BIT(0)
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#define CR0_BSU_ALL 3
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/*SMMU_IDR0 (read only) read mask*/
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#define IDR0_SES BIT(31)
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#define IDR0_S1TS BIT(30)
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#define IDR0_S2TS BIT(29)
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#define IDR0_NTS BIT(28)
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#define IDR0_SMS BIT(27)
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#define IDR0_ATOSNS BIT(26)
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#define IDR0_PTFS (0x3 << 24)
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#define IDR0_PTFS_VAL(v) ((v) >> 24)
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#define IDR0_NUMIRPT (0xff << 16)
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#define IDR0_NUMIRPT_VAL(v) ((v) >> 16)
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#define IDR0_EXSMRGS BIT(15)
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#define IDR0_CTTW BIT(14)
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#define IDR0_BTM BIT(13)
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#define IDR0_NUMSIDB (0xf << 9)
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#define IDR0_NUMSIDB_VAL(v) ((v) >> 9)
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#define IDR0_EXIDS BIT(8)
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#define IDR0_NUMSMRG 0xff
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/*PTFS bits*/
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#define PTFS_AARCH32S_AARCH32L 0x0
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#define PTFS_AARCH32L_ONLY 0x1
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#define PTFS_NO_AARCH32 0x2
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/*SMMU_IDR1 (read only) read mask*/
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#define IDR1_PAGESIZE BIT(31)
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#define IDR1_NUMPAGENDXB (0x7 << 28)
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#define IDR1_NUMPAGENDXB_VAL(v) ((v) >> 28)
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#define IDR1_HAFDBS (0x3 << 24)
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#define IDR1_NUMS2CB (0xff << 16)
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#define IDR1_NUMS2CB_VAL(v) ((v) >> 16)
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#define IDR1_SMCD BIT(15)
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#define IDR1_SSDTP (0x3 << 12)
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#define IDR1_NUMSSDNDXB (0xf << 8)
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#define IDR1_NUMCB 0xff
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/*SMMU_IDR2 (read only) read mask*/
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#define IDR2_VMID16S BIT(15)
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#define IDR2_PTFSV8_64 BIT(14)
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#define IDR2_PTFSV8_16 BIT(13)
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#define IDR2_PTFSV8_4 BIT(12)
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#define IDR2_UBS (0xf << 8)
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#define IDR2_UBS_VAL(v) ((v) >> 8)
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#define IDR2_OAS (0xf << 4)
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#define IDR2_OAS_VAL(v) ((v) >> 4)
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#define IDR2_IAS 0xf
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/*OAS bits*/
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#define IDR2_OAS_32 0x0
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#define IDR2_OAS_36 0x1
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#define IDR2_OAS_40 0x2
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#define IDR2_OAS_42 0x3
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#define IDR2_OAS_44 0x4
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#define IDR2_OAS_48 0x5
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/*IAS bits*/
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#define IDR2_IAS_32 0x0
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#define IDR2_IAS_36 0x1
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#define IDR2_IAS_40 0x2
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#define IDR2_IAS_42 0x3
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#define IDR2_IAS_44 0x4
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#define IDR2_IAS_48 0x5
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/*SMMU_IDR7*/
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#define IDR7_MAJOR (0xf << 4)
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#define IDR7_MAJOR_VAL(v) ((v) >> 4)
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#define IDR7_MINOR (0xf)
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/*SMMU_sGFSR r/w bit mask, write 1 to clear*/
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#define GFSR_MULTI BIT(31)
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#define GFSR_UUT BIT(8)
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#define GFSR_PF BIT(7)
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#define GFSR_EF BIT(6)
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#define GFSR_CAF BIT(5)
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#define GFSR_UCIF BIT(4)
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#define GFSR_UCBF BIT(3)
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#define GFSR_SMCF BIT(2)
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#define GFSR_USF BIT(1)
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#define GFSR_ICF BIT(0)
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/*SMMU_S2CRn, r/w bit mask for translation context*/
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#define S2CR_TRANSIENTCFG_SET(v) ((v) << 28)
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#define S2CR_INSTCFG_SET(v) ((v) << 26)
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#define S2CR_PRIVCFG_SET(v) ((v) << 24)
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#define S2CR_WACFG_SET(v) ((v) << 22)
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#define S2CR_RACFG_SET(v) ((v) << 20)
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#define S2CR_NSCFG_SET(v) ((v) << 18)
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#define S2CR_TYPE_SET(v) ((v) << 16)
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#define S2CR_MemAttr_SET(v) ((v) << 12)
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#define S2CR_MTCFG_SET(v) ((v) << 11)
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#define S2CR_EXIDVALID_SET(v) ((v) << 10)
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#define S2CR_SHCFG_SET(v) ((v) << 8)
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#define S2CR_CBNDX_SET(v) ((v) & 0xff)
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/*SMMU_S2CRn PRIVCFG values*/
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#define S2CR_PRIVCFG_DEFAULT 0x0
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/*SMMU_S2CRn type values*/
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#define S2CR_TYPE_CB 0x0
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#define S2CR_TYPE_BYPASS 0x1
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#define S2CR_TYPE_FAULT 0x2
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/*SMMU_SMRn, r/w bit mask for stream match*/
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#define SMR_VALID_SET(v) ((v) << 31)
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#define SMR_MASK_SET(v) ((v) & 0x7fff << 16)
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#define SMR_ID_SET(v) ((v) & 0x7fff)
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/*valid /invalid*/
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#define SMR_VALID_EN 0x1
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#define SMR_VALID_DIS 0x0
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/*SMMU_ACR, SMMU-500*/
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#define ACR_CACHE_LOCK BIT(26)
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#define ACR_S2CRB_TLBEN BIT(10)
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#define ACR_SMTNMB_TLBEN BIT(8)
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/*SMMU_CBn_FSR, write 1 to clear*/
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#define CBn_FSR_MULTI BIT(31)
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#define CBn_FSR_SS BIT(30)
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#define CBn_FSR_UUT BIT(8)
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#define CBn_FSR_ASF BIT(7)
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#define CBn_FSR_TLBLKF BIT(6)
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#define CBn_FSR_TLBLMCF BIT(5)
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#define CBn_FSR_EF BIT(4)
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#define CBn_FSR_PF BIT(3)
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#define CBn_FSR_AFF BIT(2)
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#define CBn_FSR_TF BIT(1)
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#define CBn_FSR_CLEAR_ALL (CBn_FSR_MULTI | CBn_FSR_SS | \
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CBn_FSR_UUT | CBn_FSR_ASF | CBn_FSR_TLBLKF | \
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CBn_FSR_TLBLMCF | CBn_FSR_EF | CBn_FSR_PF | \
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CBn_FSR_AFF | CBn_FSR_TF)
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/*SMMU_CBn_ACTLR defined in SMMU500*/
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#define CBn_ACTLR_CPRE BIT(1)
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#define CBn_ACTLR_CMTLB BIT(0)
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/*mask for invalidate all TLB entries, used by GR0 registers*/
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#define SMMU_TLB_INVALL_MASK 0xffffffff
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/*mask for init the TLB sync msg*/
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#define SMMU_TLB_SYNC_MASK 0xffffffff
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/*TLB sync status used in SMMU_sTLBGSTATUS and SMMU_CBn_TLBSTATUS*/
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#define TLBSTATUS_GSACTIVE BIT(0)
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/*the kernel loops N times before declear a TLB invalidation failure*/
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#define TLBSYNC_LOOP 1000
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/*SMMU_CBARn*/
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#define CBARn_TYPE_SET(v) ((v) << 16)
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#define CBARn_BPSHCFG_SET(v) ((v) << 8)
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#define CBARn_VMID_SET(v) ((v) & 0xff)
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#define CBARn_TYPE_STAGE2 0
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#define CBARn_TYPE_STAGE1 1 /*stage 1 with stage 2 by pass*/
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#define CBARn_BPSHCFG_OUTER 1
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#define CBARn_BPSHCFG_INNER 2
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#define CBARn_BPSHCFG_NONE 3
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#define CBARn_MemAttr_SET(v) ((v) << 12)
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#define MemAttr_OWB_IWB 0xf /*outer & inner write-back cacheable*/
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/*SMMU_CBA2Rn*/
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#define CBA2Rn_VMID_SET(v) (((v) & 0xffff) << 16)
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#define CBA2Rn_VA64_SET 1
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/*SMMU_CBn_TCR stage1/2 when SMMU_CBn_CBA2R.VA64 is 1*/
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#define CBn_TCR_TG1_SET(v) ((v) << 30)
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#define CBn_TCR_SH1_SET(v) ((v) << 28)
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#define CBn_TCR_ORGN1_SET(v) ((v) << 26)
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#define CBn_TCR_IRGN1_SET(v) ((v) << 24)
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#define CBn_TCR_EPD1_DIS (1 << 23) /*translation disabled for TTBR1 region*/
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#define CBn_TCR_A1_EN (1 << 22)
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#define CBn_TCR_T1SZ_SET(v) (((v) & 0x3f) << 16)
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#define CBn_TCR_TG0_SET(v) ((v) << 14)
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#define CBn_TCR_SH0_SET(v) ((v) << 12)
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#define CBn_TCR_ORGN0_SET(v) ((v) << 10)
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#define CBn_TCR_IRGN0_SET(v) ((v) << 8)
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#define CBn_TCR_T0SZ_SET(v) ((v) & 0x3f)
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#define CBn_TCR_TG_4K 0
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#define CBn_TCR_TG_64K 1
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#define CBn_TCR_TG_16K 2
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#define CBn_TCR_SH_NONE 0
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#define CBn_TCR_SH_OUTER 2
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#define CBn_TCR_SH_INNER 3
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#define CBn_TCR_GN_NCACHE 0
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#define CBn_TCR_GN_WB_WA_CACHE 1
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#define CBn_TCR_GN_WT_CACHE 2
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#define CBn_TCR_GN_WB_NWA_CACHE 3
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/*SMMU_CBn_TCR stage 2 when SMMU_CBn_CBA2R.VA64 is 1*/
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#define CBn_TCR_PASize_SET(v) ((v) << 16)
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#define CBn_TCR_SL0_SET(v) ((v) << 6)
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#define CBn_TCR_SL0_4KB_L2 0
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#define CBn_TCR_SL0_4KB_L1 1
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#define CBn_TCR_SL0_4KB_L0 2
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/*SMMU_CBn_TCR2*/
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#define CBn_TCR2_SEP_SET(v) ((v) << 15)
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#define CBn_TCR2_AS_SET(v) ((v) << 4)
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#define CBn_TCR2_PASize_SET(v) (v)
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#define CBn_TCR2_SEP_UPSTREAM_SIZE 7
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#define CBn_TCR2_AS_16 1
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#define CBn_TCR2_PASize_32 0
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#define CBn_TCR2_PASize_36 1
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#define CBn_TCR2_PASize_40 2
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#define CBn_TCR2_PASize_42 3
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#define CBn_TCR2_PASize_44 4
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#define CBn_TCR2_PASize_48 5
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/*SMMU_CBn_TTBRm*/
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#define CBn_TTBRm_ASID_SET(v) (((v) & 0xffffull) << 48)
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/*SMMU_CBn_MAIRm,
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this is the same as the MAIR in core*/
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/*MAIR0*/
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#define CBn_MAIRm_ATTR_DEVICE_nGnRnE 0x00
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#define CBn_MAIRm_ATTR_ID_DEVICE_nGnRnE 0
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#define CBn_MAIRm_ATTR_DEVICE_nGnRE 0x04
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#define CBn_MAIRm_ATTR_ID_DEVICE_nGnRE 1
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#define CBn_MAIRm_ATTR_DEVICE_GRE 0xc
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#define CBn_MAIRm_ATTR_ID_DEVICE_GRE 2
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#define CBn_MAIRm_ATTR_NC 0x44 /*non-cacheable normal memory*/
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#define CBn_MAIRm_ATTR_ID_NC 3 /*index for non-cacheable attribute*/
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/*MAIR1*/
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/*R/W allocate, normal memory, outer/innner write back*/
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#define CBn_MAIRm_ATTR_CACHE 0xff
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#define CBn_MAIRm_ATTR_ID_CACHE 0
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/*8 bit per attribute*/
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#define CBn_MAIRm_ATTR_SHIFT(n) ((n) << 3)
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/*SMMU_CBn_SCTLR*/
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#define CBn_SCTLR_CFIE (1 << 6)
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#define CBn_SCTLR_CFRE (1 << 5)
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#define CBn_SCTLR_AFE (1 << 2)
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#define CBn_SCTLR_TRE (1 << 1)
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#define CBn_SCTLR_M 1
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/*SMMU_CBn_TLBIASID*/
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#define CBn_TLBIASID_SET(v) ((v) & 0xffff)
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/*SMMU_TLBIVMID*/
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#define TLBIVMID_SET(v) ((v) & 0xffff)
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/*SMMU_CBn_TLBIVA*/
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#define CBn_TLBIVA_SET(asid, vaddr) (((asid) & 0xffff) << 48 | ((vaddr) >> 12 & 0xfffffffffff))
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/*SMMU_CBn_TLBIIPAS2*/
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#define CBn_TLBIIPAS2_SET(vaddr) ((vaddr) >> 12 & 0xfffffffff)
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void smmu_cb_assign_vspace(word_t cb, vspace_root_t *vspace, asid_t asid);
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void smmu_sid_bind_cb(word_t sid, word_t cb);
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void plat_smmu_init(void);
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void smmu_tlb_invalidate_all(void);
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void smmu_tlb_invalidate_cb(int cb, asid_t asid);
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void smmu_tlb_invalidate_cb_va(int cb, asid_t asid, vptr_t vaddr);
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void smmu_cb_disable(word_t cb, asid_t asid);
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void smmu_sid_unbind(word_t sid);
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void smmu_read_fault_state(uint32_t *status, uint32_t *syndrome_0, uint32_t *syndrome_1);
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void smmu_clear_fault_state(void);
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void smmu_cb_read_fault_state(int cb, uint32_t *status, word_t *address);
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void smmu_cb_clear_fault_state(int cb);
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