f12d6fdc98
The alignment of the tcb_t portion of a TCB object is going to be increased, this will cause the total TCB size to overflow in some cases. This updates the definition of seL4_TCBBits such that TCBs will be large enough after the alignment change.
101 lines
5.7 KiB
Text
101 lines
5.7 KiB
Text
Revision history for seL4
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For more information see the release notes at https://wiki.sel4.systems/ReleaseNotes
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This file should be word wrapped to 120 characters
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The upcoming release notes should indicate whether it is a SOURCE COMPATIBLE, BINARY COMPATIBLE or BREAKING change. As
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changes are added the compatibility information should be updated.
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upcoming release BREAKING
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BREAKING CHANGE
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= Changes =
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* Debugging option on x86 for syscall interface to read/write MSRs (this is an, equally dangerous, alternative to
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dangerous code injection)
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* Mitigation for Meltdown (https://meltdownattack.com) on x86-64 implemented. Mitigation is via a form of kernel
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page table isolation through the use of a Static Kernel Image with Microstate (SKIM) window that is used for
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trapping to and from the kernel address space. This can be enabled/disabled through the build configuration
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depending on whether you are running on vulnerable hardware or not.
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* Mitigation for Spectre (https://spectreattack.com) on x86 against the kernel implemented. Default is software
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mitigation and is the best performing so users need to do nothing. This does *not* prevent user processes from
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exploiting each other.
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* x86 configuration option for performing branch prediction barrier on context switch to prevent Spectre style
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attacks between user processes using the indirect branch predictor
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* x86 configuration option for flushing the RSB on context switch to prevent Spectre style attacks between user
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processes using the RSB
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* Define extended bootinfo header for the x86 TSC frequency
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* x86 TSC frequency exported in extended bootinfo header
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* `archInfo` is no longer a member of the bootinfo struct. Its only use was for TSC frequency on x86, which
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can now be retrieved through the extended bootinfo
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* Invocations to set thread priority and maximum control priority (MCP) have changed.
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- For both invocations, users must now provide a TCB capability `auth`
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- The requested MCP/priority is checked against the MCP of the `auth` capability.
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- Previous behavior checked against the invoked TCB, which could be subject to the confused deputy
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problem.
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* seL4_TCB_Configure no longer takes prio, mcp as an argument. Instead these fields must be set separately
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with seL4_TCB_SetPriority and seL4_TCB_SetMCPriority.
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* seL4_TCB_SetPriority and seL4_TCB_SetMCPriority now take seL4_Word instead of seL4_Uint8.
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- seL4_MaxPrio remains at 255.
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* seL4_TCB_SetSchedParams is a new method where MCP and priority can be set in the same sytsem call.
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* Size of the TCB object is increased for some build configurations
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= Upgrade notes =
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* seL4_TCB_Configure calls that set priority should be changed to explicitly call seL4_TCB_SetSchedParams
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or SetPriority
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* seL4_TCB_Configure calls that set MCP should be changed to explicitly call seL4_TCB_SetSchedParams
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or seL4_TCB_SetMCPriority
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---
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8.0.0 2018-01-17
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= Changes =
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* Support for additional zynq platform Zynq UltraScale+ MPSoC (Xilinx ZCU102, ARMv8a, Cortex A53)
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* Support for multiboot2 bootloaders on x86 (contributed change from Genode Labs)
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* Deprecate seL4_CapData_t type and functions related to it
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* A fastpath improvement means that when there are two runnable threads and the target thread is the highest priority
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in the scheduler, the fastpath will be hit. Previously the fastpath would not be used on IPC from a high priority
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thread to a low priority thread.
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* As a consequence of the above change, scheduling behaviour has changed in the case where a non-blocking IPC is sent
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between two same priority threads: the sender will be scheduled, rather than the destination.
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* Benchmarking support for armv8/aarch64 is now available.
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* Additional x86 extra bootinfo type for retrieving frame buffer information from multiboot 2
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* Debugging option to export x86 Performance-Monitoring Counters to user level
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= Upgrade notes =
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* seL4_CapData_t should be replaced with just seL4_Word. Construction of badges should just be `x` instead of
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`seL4_CapData_Badge_new(x)` and guards should be `seL4_CNode_CapData_new(x, y)` instead of
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`seL4_CapData_Guard_new(x, y)`
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* Code that relied on non-blocking IPC to switch between threads of the same priority may break.
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---
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7.0.0 2017-09-05
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= Changes =
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* Support for building standalone ia32 kernel added
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* ia32: Set sensible defaults for FS and GS selectors
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* aarch64: Use tpidrro_el0 for IPC buffer instead of tpidr_el0
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* More seL4 manual documentation added for aarch64 object invocations
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* Default NUM_DOMAINS set to 16 for x86-64 standalone builds
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* libsel4: Return seL4_Error in invocation stubs in 8fb06eecff9 ''' This is a source code level breaking change '''
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* Add a CMake based build system
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* x86: Increase TCB size for debug builds
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* libsel4: x86: Remove nested struct declarations ''' This is a source code level breaking change '''
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* Bugfix: x86: Unmap pages when delete non final frame caps
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= Upgrade notes =
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* This release is not source compatible with previous releases.
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* seL4 invocations that previously returned long now return seL4_Error which is an enum. Our libraries have already
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been updated to reflect this change, but in other places where seL4 invocations are used directly, the return types
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will need to be updated to reflect this change.
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* On x86 some structs in the Bootinfo have been rearranged. This only affects seL4_VBEModeInfoBlock_t which is used if
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VESA BIOS Extensions (VBE) information is being used.
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= Known issues =
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* One of our tests is non-deterministicly becoming unresponsive on the SMP release build on the Sabre IMX.6 platform,
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which is a non verified configuration of the kernel. We are working on fixing this problem, and will likely do a
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point release once it is fixed.
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---
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For previous releases see https://wiki.sel4.systems/ReleaseNotes
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