db2b2be64c
The GIC platforms use irq_t for irqInvalid -- bring remaining AArch32 platforms in line with that. irq_t is an unsigned type (when it is an integer) and enum constants are signed. For the proofs to treat these platforms uniformly, they need to be the same kind. They can't all be enums, because irq_t can be a more complex type for SMP platforms. Signed-off-by: Gerwin Klein <gerwin.klein@proofcraft.systems>
151 lines
6.5 KiB
C
151 lines
6.5 KiB
C
/*
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* Copyright 2020, Data61, CSIRO (ABN 41 687 119 230)
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*
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* SPDX-License-Identifier: GPL-2.0-only
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*/
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#pragma once
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#include <plat/machine/devices_gen.h>
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#include <machine/io.h>
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#include <machine/interrupt.h>
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/* SGI not supported on this platform. */
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#define NUM_SGIS 0
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#define BASIC_IRQ_OFFSET 32
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#define NORMAL_IRQ_OFFSET (BASIC_IRQ_OFFSET + 32)
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enum {
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INTERRUPT_CORE_CNTPSIRQ = 0,
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INTERRUPT_CORE_CNTPNSIRQ = 1,
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INTERRUPT_CORE_CNTHPIRQ = 2,
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INTERRUPT_CORE_CNTVIRQ = 3,
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INTERRUPT_CORE_MAILBOX_0 = 4,
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INTERRUPT_CORE_MAILBOX_1 = 5,
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INTERRUPT_CORE_MAILBOX_2 = 6,
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INTERRUPT_CORE_MAILBOX_3 = 7,
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INTERRUPT_CORE_GPU = 8,
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INTERRUPT_CORE_PMU = 9,
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INTERRUPT_CORE_AXI = 10,
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INTERRUPT_CORE_LOCAL_TIMER = 11,
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//17:12 Peripheral 1..15 interrupt (Currently not used)
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//31:28 <Reserved>
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INTERRUPT_BASIC_IRQ_ARM_TIMER = (BASIC_IRQ_OFFSET + 0),
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INTERRUPT_BASIC_IRQ_ARM_MAILBOX = (BASIC_IRQ_OFFSET + 1),
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INTERRUPT_BASIC_IRQ_ARM_DOORBELL0 = (BASIC_IRQ_OFFSET + 2),
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INTERRUPT_BASIC_IRQ_ARM_DOORBELL1 = (BASIC_IRQ_OFFSET + 3),
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INTERRUPT_BASIC_IRQ_GPU0_HALTED = (BASIC_IRQ_OFFSET + 4),
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INTERRUPT_BASIC_IRQ_GPU1_HALTED = (BASIC_IRQ_OFFSET + 5),
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INTERRUPT_BASIC_IRQ_ILLEGAL_ACCESS_TYPE1 = (BASIC_IRQ_OFFSET + 6),
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INTERRUPT_BASIC_IRQ_ILLEGAL_ACCESS_TYPE0 = (BASIC_IRQ_OFFSET + 7),
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INTERRUPT_BASIC_IRQ_PENDING_REGISTER1 = (BASIC_IRQ_OFFSET + 8),
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INTERRUPT_BASIC_IRQ_PENDING_REGISTER2 = (BASIC_IRQ_OFFSET + 9),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_7 = (BASIC_IRQ_OFFSET + 10),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_9 = (BASIC_IRQ_OFFSET + 11),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_10 = (BASIC_IRQ_OFFSET + 12),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_18 = (BASIC_IRQ_OFFSET + 13),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_19 = (BASIC_IRQ_OFFSET + 14),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_53 = (BASIC_IRQ_OFFSET + 15),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_54 = (BASIC_IRQ_OFFSET + 16),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_55 = (BASIC_IRQ_OFFSET + 17),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_56 = (BASIC_IRQ_OFFSET + 18),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_57 = (BASIC_IRQ_OFFSET + 19),
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INTERRUPT_BASIC_IRQ_GPU_IRQ_62 = (BASIC_IRQ_OFFSET + 20),
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// 31:21 <unused>
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INTERRUPT_IRQ_AUX = (NORMAL_IRQ_OFFSET + 29),
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INTERRUPT_IRQ_I2C_SPI_SLV = (NORMAL_IRQ_OFFSET + 43),
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INTERRUPT_IRQ_PWA0 = (NORMAL_IRQ_OFFSET + 45),
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INTERRUPT_IRQ_PWA1 = (NORMAL_IRQ_OFFSET + 46),
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INTERRUPT_IRQ_SMI = (NORMAL_IRQ_OFFSET + 48),
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INTERRUPT_IRQ_GPIO0 = (NORMAL_IRQ_OFFSET + 49),
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INTERRUPT_IRQ_GPIO1 = (NORMAL_IRQ_OFFSET + 50),
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INTERRUPT_IRQ_GPIO2 = (NORMAL_IRQ_OFFSET + 51),
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INTERRUPT_IRQ_GPIO3 = (NORMAL_IRQ_OFFSET + 52),
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INTERRUPT_IRQ_I2C = (NORMAL_IRQ_OFFSET + 53),
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INTERRUPT_IRQ_SPI = (NORMAL_IRQ_OFFSET + 54),
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INTERRUPT_IRQ_PCM = (NORMAL_IRQ_OFFSET + 55),
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INTERRUPT_IRQ_UART = (NORMAL_IRQ_OFFSET + 57),
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};
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#define FIQCTRL_FIQ_ENABLE BIT(7)
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#define FIQCTRL_FIQ_SRC_GPU_IRQ(x) (x)
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#define FIQCTRL_FIQ_SRC_ARM_TIMER 64
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#define FIQCTRL_FIQ_SRC_ARM_MAILBOX 65
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#define FIQCTRL_FIQ_SRC_ARM_DOORBELL0 66
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#define FIQCTRL_FIQ_SRC_ARM_DOORBELL1 67
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#define FIQCTRL_FIQ_SRC_GPU0_HALTED 68
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#define FIQCTRL_FIQ_SRC_GPU1_HALTED 69
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#define FIQCTRL_FIQ_SRC_ILLEGAL_ACCESS_TYPE1 70
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#define FIQCTRL_FIQ_SRC_ILLEGAL_ACCESS_TYPE0 71
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#define FIQCTRL_FIQ_SRC(src) (FIQCTRL_FIQ_SRC_##src)
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volatile struct intc_regs {
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uint32_t bfIRQBasicPending; /* 0x200 R */
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uint32_t bfGPUIRQPending[2]; /* 0x204 R */
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uint32_t FIQ_control; /* 0x20C R/W */
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uint32_t bfEnableIRQs[2]; /* 0x210 R/Wbs */
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uint32_t bfEnableBasicIRQs; /* 0x218 R/Wbs */
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uint32_t bfDisableIRQs[2]; /* 0x21C R/Wbc */
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uint32_t bfDisableBasicIRQs; /* 0x224 R/Wbc */
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} *intc_regs = (volatile struct intc_regs *)INTC_PPTR;
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volatile struct core_regs {
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uint32_t controlRegister; /* 0x00 */
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uint32_t unused0; /* 0x04 */
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uint32_t coreTimerPrescaler; /* 0x08 */
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uint32_t gpuInterruptsRouting; /* 0x0C */
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uint32_t pmirSet; /* 0x10 */
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uint32_t pmirClear; /* 0x14 */
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uint32_t unused1; /* 0x18 */
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uint32_t coreTimerAccessLS; /* 0x1C */
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uint32_t coreTimerAccessMS; /* 0x20 */
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uint32_t localInterrupt0Routing; /* 0x24 */
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uint32_t unused2; /* 0x28 */
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uint32_t axiOutstandingCounters; /* 0x2C */
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uint32_t axiOutstandingIRQ; /* 0x30 */
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uint32_t localTimerCtl; /* 0x34 */
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uint32_t localTimerFlags; /* 0x38 */
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uint32_t unused3; /* 0x3C */
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uint32_t coreTimersIrqCtrl[4]; /* 0x40 Timers interrupt control registers */
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uint32_t coreMailboxesIrqCtrl[4]; /* 0x50 Mailbox interrupt control */
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uint32_t coreIRQSource[4]; /* 0x60 IRQ source registers */
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uint32_t coreFIQSource[4]; /* 0x70 FIQ source registers */
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uint32_t coreMailboxWriteset[4][4]; /* 0x80 Mailbox write-set registers (Write only) */
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uint32_t coreMailboxRW[4][4]; /* 0xC0 Mailbox write-clear registers (Read & Write) */
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} *core_regs = (volatile struct core_regs *) ARM_LOCAL_PPTR;
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#define LOCAL_TIMER_IRQ_STATUS 31
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#define LOCAL_TIMER_CTRL_IRQ_BIT 29
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#define LOCAL_TIMER_CTRL_EN_BIT 28
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#define LOCAL_TIMER_CTRL_RL_MASK MASK(28)
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irq_t irqInvalid = 255;
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static inline bool_t isIRQPending(void)
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{
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uint32_t pending;
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pending = core_regs->coreIRQSource[0];
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/* Mask out invalid bits */
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pending &= MASK(12);
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return pending != 0;
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}
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static inline void ackInterrupt(UNUSED irq_t irq)
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{
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/* No way to ACK an interrupt */
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}
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static inline void handleSpuriousIRQ(void)
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{
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/* Nothing to do here */
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}
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static inline void plat_sendSGI(word_t irq, word_t target)
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{
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/* Unreachable; not supported on this platform. */
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halt();
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}
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