48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/*
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* Copyright 2017, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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* ABN 41 687 119 230.
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*
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* This software may be distributed and modified according to the terms of
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* the GNU General Public License version 2. Note that NO WARRANTY is provided.
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* See "LICENSE_GPLv2.txt" for details.
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*
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* @TAG(DATA61_GPL)
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*/
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#ifndef __DRIVER_TIMER_AM335X_H
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#define __DRIVER_TIMER_AM335X_H
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#define TISR_OVF_FLAG (BIT(0) | BIT(1) | BIT(2))
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struct timer {
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uint32_t tidr; // 00h TIDR Identification Register
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uint32_t padding1[3];
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uint32_t cfg; // 10h TIOCP_CFG Timer OCP Configuration Register
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uint32_t padding2[3];
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uint32_t tieoi; // 20h IRQ_EOI Timer IRQ End-Of-Interrupt Register
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uint32_t tisrr; // 24h IRQSTATUS_RAW Timer IRQSTATUS Raw Register
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uint32_t tisr; // 28h IRQSTATUS Timer IRQSTATUS Register
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uint32_t tier; // 2Ch IRQSTATUS_SET Timer IRQENABLE Set Register
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uint32_t ticr; // 30h IRQSTATUS_CLR Timer IRQENABLE Clear Register
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uint32_t twer; // 34h IRQWAKEEN Timer IRQ Wakeup Enable Register
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uint32_t tclr; // 38h TCLR Timer Control Register
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uint32_t tcrr; // 3Ch TCRR Timer Counter Register
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uint32_t tldr; // 40h TLDR Timer Load Register
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uint32_t ttgr; // 44h TTGR Timer Trigger Register
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uint32_t twps; // 48h TWPS Timer Write Posted Status Register
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uint32_t tmar; // 4Ch TMAR Timer Match Register
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uint32_t tcar1; // 50h TCAR1 Timer Capture Register
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uint32_t tsicr; // 54h TSICR Timer Synchronous Interface Control Register
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uint32_t tcar2; // 58h TCAR2 Timer Capture Register
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};
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typedef volatile struct timer timer_t;
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extern timer_t *timer;
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static inline void resetTimer(void)
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{
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timer->tisr = TISR_OVF_FLAG;
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ackInterrupt(KERNEL_TIMER_IRQ);
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}
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#endif /* __DRIVER_TIMER_AM335X_H */
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