Axel Heider e6fbbbb065 CI: do simulation and HW build with LLVM on RISCV ... Signed-off-by: Axel Heider <axelheider@gmx.de>		2024-01-12 07:50:50 +11:00
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compilation-checks.yml	CI: build standalone kernel for RISCV64 with LLVM	2024-01-12 07:50:50 +11:00
cparser.yml	github: run C parser on push/PR	2021-06-30 14:04:00 +10:00
manual.yml	github: bump action deps to node16 actions	2022-11-21 15:59:06 +11:00
pr.yml	github: add AARCH64 to preprocess test	2022-02-03 17:19:58 +11:00
preprocess-deploy.yml	github: add AARCH64 to preprocess test	2022-02-03 17:19:58 +11:00
proof.yml	github: add MCS C proofs to proof check	2023-10-24 14:19:54 +11:00
push.yml	Refactor github workflows; add preprocess test	2020-06-18 12:47:54 +10:00
sel4bench-pr.yml	github: fix sel4bench trigger in GitHub workflow	2023-11-01 08:43:06 +11:00
sel4test-deploy.yml	CI: do simulation and HW build with LLVM on RISCV	2024-01-12 07:50:50 +11:00
sel4test-hw.yml	CI: do simulation and HW build with LLVM on RISCV	2024-01-12 07:50:50 +11:00
sel4test-sim.yml	CI: do simulation and HW build with LLVM on RISCV	2024-01-12 07:50:50 +11:00
trigger.yml	github: run actions with secrets only in seL4 org	2021-10-18 14:47:07 +11:00
xml_lint.yml	github: bump action deps to node16 actions	2022-11-21 15:59:06 +11:00