6294225ca7
Having a different name for the FLAGS register creates an unnecessary difference between ia32 and x86_64 code since regardless of the name/size the bits in the register mean exactly the same thing
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
/*
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* Copyright 2016, Data61
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* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
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* ABN 41 687 119 230.
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*
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* This software may be distributed and modified according to the terms of
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* the GNU General Public License version 2. Note that NO WARRANTY is provided.
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* See "LICENSE_GPLv2.txt" for details.
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*
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* @TAG(D61_GPL)
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*/
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#include <object.h>
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#include <machine.h>
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#include <arch/model/statedata.h>
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#include <arch/kernel/vspace.h>
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#include <arch/kernel/thread.h>
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#include <arch/linker.h>
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extern word_t irq_stack[6];
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void
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Arch_switchToThread(tcb_t* tcb)
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{
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word_t base;
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/* set PD */
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setVMRoot(tcb);
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/* update the GDT_TLS entry with the thread's TLS_BASE address */
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base = getRegister(tcb, TLS_BASE);
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x86_write_fs_base(base);
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/* update the GDT_IPCBUF entry with the thread's IPC buffer address */
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base = tcb->tcbIPCBuffer;
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x86_write_gs_base(base);
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}
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BOOT_CODE void
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Arch_configureIdleThread(tcb_t* tcb)
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{
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setRegister(tcb, FLAGS, BIT(9) | BIT(1));
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setRegister(tcb, NextIP, (uint64_t)idleThreadStart);
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setRegister(tcb, CS, SEL_CS_0);
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setRegister(tcb, SS, SEL_DS_0);
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/* In 64-bit mode the CPU unconditionally pushes to the stack when
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* taking an exception. Therefore we need to provide the idle thread
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* with a stack */
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setRegister(tcb, RSP, (uint64_t)&irq_stack[6]);
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}
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void
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Arch_switchToIdleThread(void)
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{
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/* Don't need to do anything */
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}
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void CONST
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Arch_activateIdleThread(tcb_t* tcb)
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{
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/* Don't need to do anything */
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}
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