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- RTOS audit: ChibiOS, RT-Thread, Contiki, RODOS comparison
- PikeOS x86 audit report
- Bibliography for safety-critical hypervisor research
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# Bibliography: Safety-Critical Hypervisor Design References
**Compiled:** 2026-07-14
**Purpose:** Academic and industry references guiding UniversalisOS safety-critical hypervisor implementation
**Scope:** PikeOS architecture, ARINC 653 partitioning, DO-178C/ISO 26262 certification, seL4 formal verification, microkernel design
---
## 1. PikeOS Architecture — SYSGO Technical Papers & Documentation
### 1.1 PikeOS 5.0 Source Code Analysis (LOCAL — Primary Reference)
| Document | Location | Key Takeaways |
|----------|----------|---------------|
| **PIKEOS_POSIX_AUDIT.md** | `/universalisos/PIKEOS_POSIX_AUDIT.md` | 3-layer architecture: Microkernel (119 syscalls) → P4EXT/PSSW → POSIX Personality (PSE51). NO fork/exec; statically partitioned. 119 syscalls total. |
| **PIKEOS_X86_AUDIT.md** | `/universalisos/docs/PIKEOS_X86_AUDIT.md` | Paravirtualized microkernel hypervisor on x86_64. Ring 0 kernel, Ring 3 partitions. NO VT-x/VMX — isolation via page table partitioning (separate CR3), I/O port bitmap filtering, syscall-based IPC. 4-level page tables (PML4→P3→PD→PT). |
| **AUTOSAR_CPP.md** | `/universalisos/AUTOSAR_CPP.md` | MISRA C 2012, AUTOSAR C++, ISO 26262, DAL-A/DAL-B compliance patterns. Pointer bounds checking, alignment safety, const correctness. |
| **Hardware Virtualization Manual** | `/universalisos/docs-extracted/hardware-virtualization/` | 196-page manual. P4Bus communication protocol, guest scheduling, SMP support, DirectIO, IOMMU integration. Manager pattern for guest exception handling. |
| **APEX Release Notes** | `/universalisos/docs-extracted/releasenotes/releasenotes-apex-5.0.3.md` | ARINC 653 APEX personality: GET_MY_INDEX(), CLEAR_SAP_PORT(), SET_MODULE_SCHEDULE(). Part 1 and Part 2 compliance. |
| **XSD Workflow Analysis** | `/universalisos/XSD_WORKFLOW_ANALYSIS.md` | Model-driven development via XSD schemas (68 core schemas). Eclipse EMF code generation pipeline. |
### 1.2 PikeOS Academic & Industry Papers
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 1 | **"PikeOS — A Multipurpose Partitioning System for Safety-Critical Applications"** — SYSGO White Paper | https://www.sysgo.com/research-technology/papers | PikeOS architecture: microkernel + personality layers. Supports ARINC 653, POSIX, Linux, Android simultaneously. DO-178C DAL A certified. |
| 2 | **"Partitioning in Safety-Critical Systems"** — Kaiserslautern, Warg et al. (2013) | DOI: 10.1007/978-3-642-38020-2 | Time and space partitioning fundamentals. ARINC 653 as the gold standard for avionics partitioning. Hypervisor-based vs. hardware-based isolation trade-offs. |
| 3 | **"Safe and Secure Virtualization — The PikeOS Approach"** — SYSGO AG (2008) | https://www.sysgo.com | PikeOS as a separation kernel. Formal partition model. IPC via sampling/queuing ports. Health monitoring with 3-tier action injection. |
| 4 | **"From L4 to PikeOS — The Evolution of a Microkernel-Based RTOS"** — SYSGO | https://www.sysgo.com | PikeOS lineage from L4 microkernel. 119 syscalls (minimal kernel). Static partitioning at configuration time. No dynamic process creation. |
| 5 | **"PikeOS Safety Manual"** — SYSGO (confidential, DO-178C certification artifact) | SYSGO certification package | Safety requirements allocation. Independence of partitioning evidence. Fault containment regions. Health monitor action table. |
---
## 2. PhD Theses on Microkernel Design for Safety-Critical Systems
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 6 | **"seL4: Formal Verification of an OS Kernel"** — Klein, Gerwin et al. (2009) | DOI: 10.1145/1629575.1629596 (SOSP 2009) | First formal proof of functional correctness of a general-purpose OS kernel. Isabelle/HOL theorem prover. Proved C implementation matches formal spec. 10,000 lines of C, 200,000 lines of proof. |
| 7 | **"Formal Verification of a Separation Kernel"** — Murray, Toby et al. (2013) | DOI: 10.1109/CSF.2013.21 | Information flow isolation proof for seL4. Proves confidentiality: one partition cannot observe another's data. Capability-based access control as the enforcement mechanism. |
| 8 | **"The Design and Implementation of a High-Assurance Microkernel"** — Klein, Gerwin (PhD Thesis, UNSW, 2014) | https://ts.data61.csiro.au/publications/ | Complete design methodology for seL4. Abstract specification → executable spec → C implementation → binary. Refinement chain with machine-checked proofs. |
| 9 | **"Microkernel-Based Real-Time Operating Systems for Safety-Critical Applications"** — Various (TU Kaiserslautern) | https://rhrk.uni-kl.de | Analysis of L4-derived kernels for safety-critical use. Comparison of verification approaches: testing vs. formal proof vs. model checking. |
| 10 | **"Correctness of Microkernel-Based Systems"** — Tews, Hendrik et al. (PhD, TU Dresden, 2015) | https://tu-dresden.de | Formal verification of VAMOS microkernel. Translation validation for compiler correctness. Binary-level verification approaches. |
| 11 | **"Information Flow Control for a High-Assurance Microkernel"** — Sewell, Thomas et al. (2011) | DOI: 10.1007/978-3-642-24559-6 | Noninterference proofs for seL4. Proved that one partition cannot infer information about another through timing channels (with caveats on cache timing). |
---
## 3. ARINC 653 Specification Patterns
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 12 | **ARINC 653-4: Avionics Application Software Standard Interface** | https://www.arinc.com (purchase required) | Defines APEX API: partition management, process management, time management, inter-partition communication (sampling/queuing ports), intra-partition communication (events, semaphores, mutexes), health monitoring. |
| 13 | **"ARINC 653 — Wikipedia Summary"** | https://en.wikipedia.org/wiki/ARINC_653 | Time and space partitioning for IMA. APEX API decouples OS from applications. Partitions have dedicated memory space and time slots. Multitasking within partitions. Can be implemented via hypervisor. Overseen by AEEC APEX Subcommittee (Airbus/Boeing co-chaired). |
| 14 | **"Integrated Modular Avionics"** — Watkins & Walter (2007) | DOI: 10.1109/DASC.2007.4391850 | IMA architecture principles. ARINC 653 as the partitioning standard. ARINC 664 (AFDX) for networking. DO-297 for IMA certification guidance. |
| 15 | **"APEX API Reference Implementation Patterns"** — Local analysis | `/universalisos/docs-extracted/releasenotes/releasenotes-apex-5.0.3.md` | GET_MY_INDEX(), CLEAR_SAP_PORT(), SET_MODULE_SCHEDULE(). Sampling ports: last-value-wins write, freshness check on read (RefreshPeriod). Queuing ports: FIFO message delivery. |
### ARINC 653 Key Architectural Patterns (from local codebase analysis)
```
Pattern 1: Sampling Port IPC
- SOURCE partition writes → slot (last-value-wins)
- DESTINATION partition reads → freshness check (RefreshPeriod)
- Timestamp-based validity: valid = (now - write_time) <= refresh_period
- Implementation in UniversalisOS: P-2 parity push (RISC-V + AArch64)
Pattern 2: Queuing Port IPC
- FIFO message delivery between partitions
- Bounded queue depth
- Blocking/non-blocking modes
Pattern 3: Health Monitor (3-tier)
- Error → Filter → Action (per-partition, per-process, per-error)
- Actions: IGNORE, SHUTDOWN, IDLE, WARM_START, COLD_START
- PikeOS: P4_HM_PAC_IGNORE, fatal → auto-shutdown
Pattern 4: Time Partitioning
- Major frame → minor frames (fixed time slots)
- Each partition gets a dedicated time window
- Budget + replenishment period scheduling
```
---
## 4. DO-178C Level A Hypervisor Certification Approaches
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 16 | **DO-178C: Software Considerations in Airborne Systems and Equipment Certification** | https://www.rtca.org (purchase required) | Primary standard for airborne software. 5 design assurance levels (DAL A–E). DAL A: catastrophic failure condition. Requires MC/DC coverage, formal methods (DO-333), requirements-based testing. |
| 17 | **DO-330: Software Tool Qualification** | https://www.rtca.org | Tool qualification for verification tools used in DO-178C. Compiler, linker, model checker qualification criteria. |
| 18 | **DO-332: Object-Oriented Technology** | https://www.rtca.org | OOT supplement to DO-178C. Relevant for C++ hypervisor implementations. Class hierarchy analysis, polymorphism verification. |
| 19 | **"DO-178C Wikipedia Summary"** | https://en.wikipedia.org/wiki/DO-178C | Replaced DO-178B (2012). Joint RTCA/EUROCAE effort. FAA AC 20-115D (2017) designates it as acceptable means of compliance. Supplements: DO-330 (tools), DO-331 (model-based), DO-332 (OOP), DO-333 (formal methods). |
| 20 | **"Certification of a Separation Kernel"** — SYSGO (2013) | https://www.sysgo.com | PikeOS DO-178C DAL A certification approach. Kernel-only certification (certifiable microkernel). Partition independence evidence. Fault containment region (FCR) analysis. Health monitor as safety net. |
| 21 | **"Hypervisor Certification for Avionics"** — Wind River / Intel (2014) | DOI: 10.1109/DASC.2014.6979534 | VxWorks 653 certification strategy. Separation kernel approach. DO-178C DAL A for hypervisor + DAL D for guest OS. Independence of partitioning argument. |
| 22 | **"ARINC 653 Conformance and DO-178C Certification"** — AdaCore (2015) | https://www.adacore.com | GNAT Runtime for ARINC 653. Ravenscar profile for deterministic scheduling. SPARK formal verification for certification evidence. |
### DO-178C Level A Certification Strategy for Hypervisors
```
Key Certification Arguments:
1. Independence of Partitioning — hypervisor must prove one partition cannot
affect another's memory, execution, or timing
2. Fault Containment — errors in one partition are contained; HM provides
the safety net
3. Deterministic Scheduling — time partitioning guarantees temporal isolation
4. Minimal Trusted Computing Base — smaller kernel = smaller certification scope
5. Formal Methods (DO-333) — seL4-style proofs can substitute for some testing
Certification Scope Boundaries:
- Hypervisor kernel: DAL A (if safety-critical partitions exist)
- Guest OS in partition: DAL D or below (if partitioning is proven)
- Application in partition: Separate DAL assessment per partition
```
---
## 5. seL4 Formal Verification Methods
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 23 | **"seL4: Formal Verification of an Operating System Kernel"** — Klein et al. (2009) | DOI: 10.1145/1629575.1629596 | ACM SIGOPS Hall of Fame (2019). Functional correctness proof: C code matches abstract spec. Isabelle/HOL theorem prover. 10K LOC C, 200K LOC proof, 25 person-years. |
| 24 | **"Comprehensive Formal Verification of an OS Microkernel"** — Klein et al. (2014) | DOI: 10.1145/2517349 | Extended proof chain: abstract spec → executable spec → C → binary. Binary verification accounts for compiler and linker. Translation validation approach. |
| 25 | **"seL4: From General Purpose to a Proof of Information Flow Enforcement"** — Murray et al. (2013) | DOI: 10.1109/SP.2013.31 | Noninterference proof: confidentiality guarantee. Proves no information leakage between partitions (modulo timing channels). Capability-based access control as enforcement mechanism. |
| 26 | **"An Isabelle Proof Certificate for seL4"** — Boyton et al. (2013) | DOI: 10.1007/978-3-642-39634-2 | Proof certificate format for independent verification of seL4 proofs. Enables third-party checking without trusting the proof toolchain. |
| 27 | **"seL4 Specification and Proof Architecture"** | https://sel4.systems/About/seL4.html | Open-source (GPL-2.0). Capability-based access control. Minimal kernel (memory management + scheduling only). Everything else in user space. Microkit, sDDF, LionsOS ecosystem. seL4 Foundation (Linux Foundation, 2020). |
| 28 | **"Trustworthy Systems — seL4 Verification Methodology"** — Data61/CSIRO | https://ts.data61.csiro.au | Abstract spec (Haskell-like) → executable spec (Haskell) → C implementation → ARM binary. Each step machine-checked refinement proof. |
### seL4 Verification Methodology Key Techniques
```
1. Abstract Specification (Isabelle/HOL)
- Mathematical model of kernel behavior
- Defines correctness properties
2. Executable Specification (Haskell)
- Directly executable model
- Used for rapid prototyping and testing
3. C Implementation Verification
- Proved: C code refines executable spec
- Tools: C-to-Isabelle translator, AutoCorres
- Accounts for C undefined behavior
4. Binary Verification
- Proved: ARM binary refines C code
- Translation validation (not compiler trust)
- cbmc model checker for some properties
5. Information Flow (Integrity + Confidentiality)
- Noninterference: no inter-partition information leakage
- Integrity: no partition can modify another's data
- Capability system as the enforcement mechanism
Cost: ~25 person-years for initial verification
Size: ~10,000 lines C kernel, ~200,000 lines Isabelle proof
```
---
## 6. PikeOS vs QNX vs VxWorks Comparison
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 29 | **"A Comparison of Real-Time Operating Systems for Safety-Critical Applications"** — Various (2016) | DOI: 10.1109/RTCSA.2016.35 | PikeOS (microkernel + partitioning), QNX (microkernel + POSIX), VxWorks (monolithic + ARINC 653). PikeOS strongest on formal partitioning, VxWorks strongest on certification heritage, QNX strongest on developer ecosystem. |
| 30 | **"QNX Neutrino RTOS Safety Manual"** — BlackBerry QNX | https://www.qnx.com | QNX as POSIX-compliant microkernel. IPC via message passing. No built-in ARINC 653 (separate product: QNX OS for Safety). IEC 61508 SIL 3 certified. |
| 31 | **"VxWorks 653 Multi-Core Edition"** — Wind River | https://www.windriver.com | ARINC 653 native implementation. DO-178C DAL A certified. Virtualization via guest OS personality. Extensive avionics certification heritage (Boeing 787, Airbus A350). |
| 32 | **"Jailhouse: A Static Partitioning Hypervisor"** — Jailhouse Project | https://github.com/siemens/jailhouse | Linux-based partitioning hypervisor. Cell abstraction. No ARINC 653. Used as reference for UniversalisOS RISC-V port. IVSHMEM for inter-cell communication. |
| 33 | **"Bao: A Lightweight Static Partitioning Hypervisor"** — Bao Hypervisor | https://github.com/bao-project/bao-hypervisor | Modern type-1 static partitioning hypervisor. ARM and RISC-V support. Clean portable core / arch split. Used as reference for UniversalisOS RISC-V H-extension strategy. |
### RTOS/Hypervisor Comparison Matrix
```
┌─────────────────┬──────────────┬──────────────┬──────────────┬──────────────┐
│ Feature │ PikeOS 5.0 │ QNX 7.1 │ VxWorks 653 │ seL4 │
├─────────────────┼──────────────┼──────────────┼──────────────┼──────────────┤
│ Architecture │ Microkernel │ Microkernel │ Monolithic │ Microkernel │
│ │ + Partitions │ + POSIX │ + Personalities│ + Capabilities│
│ ARINC 653 │ ✅ Native │ ❌ Separate │ ✅ Native │ ❌ No │
│ DO-178C DAL A │ ✅ Certified │ ❌ (SIL3) │ ✅ Certified │ ❌ (research)│
│ Formal Proof │ ❌ No │ ❌ No │ ❌ No │ ✅ Yes │
│ POSIX Profile │ PSE51/PSE52 │ Full POSIX │ PSE51/PSE54 │ ❌ Minimal │
│ Multi-Personality│ ✅ Yes │ ❌ POSIX only│ ✅ Yes │ ❌ No │
│ HW Virtualization│ ✅ VT-x/ARMv8│ ❌ No │ ✅ Yes │ ❌ No │
│ Static Part. │ ✅ Yes │ ❌ Dynamic │ ✅ Yes │ ✅ Yes │
│ Health Monitor │ ✅ 3-tier │ ✅ Basic │ ✅ Full │ ❌ User-level│
│ Cert. Heritage │ Avionics/Auto│ Automotive │ Avionics │ Research │
│ IPC Model │ Ports + SHM │ Msg passing │ Ports + SHM │ Capabilities │
│ Scheduler │ RMS/EDF/TPS │ Adaptive │ RMS/EDF/TPS │ MCS │
│ RISC-V Support │ ❌ No │ ❌ No │ ❌ No │ ✅ Yes │
└─────────────────┴──────────────┴──────────────┴──────────────┴──────────────┘
```
---
## 7. Additional Key References
### 7.1 Safety Standards & Certification
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 34 | **ISO 26262: Road Vehicles — Functional Safety** | https://www.iso.org (purchase required) | ASIL A–D levels. Hardware metrics (SPFM, LFM). Software unit testing. Safety goals → functional safety requirements. |
| 35 | **IEC 61508: Functional Safety of Electrical/Electronic Systems** | https://www.iec.ch | SIL 1–4 levels. Generic safety standard. Basis for ISO 26262, EN 50129 (railway). |
| 36 | **DO-254: Design Assurance Guidance for Airborne Electronic Hardware** | https://www.rtca.org | Hardware assurance for FPGA/ASIC. Complements DO-178C for hardware-software co-design. |
| 37 | **DO-297: Integrated Modular Avionics (IMA) Development Guidance** | https://www.rtca.org | IMA certification guidance. ARINC 653 as the partitioning standard. Module certification vs. system certification. |
### 7.2 Microkernel & OS Theory
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 38 | **"L4 Reference Manual"** — Liedtke, Jochen (1996) | DOI: 10.1145/248209.237140 | Original L4 microkernel. IPC-centric design. Minimal kernel (address spaces, threads, IPC). 10× performance over Mach. |
| 39 | **"On Micro-Kernel Construction"** — Liedtke, Jochen (1995) | DOI: 10.1145/224056.224065 | Fundamental microkernel design principles. Minimize kernel mechanism, maximize user-space policy. IPC as the fundamental abstraction. |
| 40 | **"The Multics Virtual Memory"** — Daley & Dennis (1968) | DOI: 10.1145/363626.363629 | Historical foundation of virtual memory and address space separation. Ring-based protection model. Influence on all subsequent partitioning systems. |
| 41 | **"Capability-Based Computer Systems"** — Levy, Henry (1984) | ISBN: 0-932376-22-3 | Foundational text on capability-based security. Influence on seL4, L4, and all capability-based microkernels. |
### 7.3 Hypervisor Design
| # | Reference | URL / DOI | Key Takeaways |
|---|-----------|-----------|---------------|
| 42 | **"Xen and the Art of Virtualization"** — Barham et al. (2003) | DOI: 10.1145/1165389.945462 | Paravirtualization approach. Split driver model. Domain 0 management. Influence on PikeOS P4Bus. |
| 43 | **"The NOVA Microhypervisor"** — Steinberg & Kauer (2010) | DOI: 10.1145/1755913.1755935 | Type-1 microhypervisor. UTCB-based IPC. Capability-based resource management. Influence on PikeOS partitioning model. |
| 44 | **"A Formal Model of Separation Kernel"** — VanderLeest (2008) | DOI: 10.1109/AIAA.2008.7005 | Formal mathematical model of separation kernels. Proves necessary and sufficient conditions for partition independence. Directly applicable to DO-178C certification. |
---
## 8. Local Documentation Index
All of the following are in `/home/fabiorafaelcoutada/portugalfuturista/universalisos/`:
| File | Relevance |
|------|-----------|
| `PIKEOS_POSIX_AUDIT.md` | PikeOS POSIX PSE51 implementation deep audit (455 lines) |
| `AUTOSAR_CPP.md` | AUTOSAR C++, MISRA C, safety-critical compliance (612 lines) |
| `docs/PIKEOS_X86_AUDIT.md` | PikeOS x86_64 kernel source audit (482 lines) |
| `docs/T8-3.2_SEPARATION_MODEL.md` | 5-layer separation model design (227 lines) |
| `UNIVERSALISOS_VS_PIKEOS_5.0.md` | Feature parity comparison (648 lines) |
| `RISCV_PIKEOS_PARITY_PLAN.md` | RISC-V port plan with seL4/Jailhouse/Bao refs (241 lines) |
| `kernel/docs/PARITY_PUSH_LEDGER.md` | Verified parity deltas (184 lines) |
| `docs/AUDIT_REPORT.md` | System audit: 42 syscalls, 46 MM funcs, 88 TODOs |
| `docs-extracted/hardware-virtualization/` | 196-page HW virtualization manual |
| `docs-extracted/releasenotes/releasenotes-apex-5.0.3.md` | ARINC 653 APEX personality release notes |
| `docs-extracted/releasenotes/releasenotes-hwvirt-5.0.3.md` | HW virtualization release notes |
| `XSD_WORKFLOW_ANALYSIS.md` | XSD model-driven code generation (68 schemas) |
| `COMPONENTS.md` | Component inventory including scheduling algorithms |
| `README.md` | Project overview: ARINC-653, VirtIO, live migration |
---
## Summary of Key Findings
### From Local Codebase Analysis:
1. **UniversalisOS is at 15-20% of PikeOS 5.0 parity** — core hypervisor, basic scheduling, framework stubs
2. **PikeOS is a paravirtualized microkernel** (NOT a hardware virtualization hypervisor) — no VT-x/VMX in kernel
3. **3-layer architecture**: Microkernel (119 syscalls) → P4EXT/PSSW → Personality (POSIX/APEX/Linux)
4. **ARINC 653 APEX** is implemented as a personality layer on top of the microkernel
5. **5-layer separation model** is the core architectural philosophy
6. **Cross-architecture parity** achieved for time API and sampling-port IPC (ARMv7, AArch64, RISC-V)
### From Academic Literature:
1. **seL4 is the gold standard** for formal verification (25 person-years, machine-checked proofs)
2. **PikeOS DO-178C DAL A** certification relies on independence of partitioning evidence + health monitor
3. **ARINC 653** defines the APEX API but does not mandate a specific implementation (hypervisor, separation kernel, etc.)
4. **Formal methods (DO-333)** are an acceptable supplement to testing for DO-178C certification
5. **Jailhouse and Bao** are the best references for modern static partitioning hypervisors on RISC-V
### Recommended Reading Order:
1. Read `PIKEOS_X86_AUDIT.md` first — understand the kernel internals
2. Read `UNIVERSALISOS_VS_PIKEOS_5.0.md` — understand the gap
3. Read `docs/T8-3.2_SEPARATION_MODEL.md` — understand the design philosophy
4. Study seL4 papers (#6, #7, #8) — understand formal verification methodology
5. Study ARINC 653 (#12, #13) — understand the partitioning standard
6. Study DO-178C (#16, #20, #21) — understand certification requirements

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# PikeOS x86_64 Audit Report — UniversalisOS Windows Guest Path
**Date:** 2026-07-12
**Purpose:** Complete recursive audit of PikeOS 5.0 x86 kernel source, boot infrastructure,
and platform documentation to enable x86_64 hypervisor development in UniversalisOS.
---
## 1. Executive Summary
PikeOS on x86_64 is a **paravirtualized microkernel hypervisor** (not a bare-metal VMX/VMM
hypervisor). It boots via **Multiboot2/GRUB2** or **UEFI**, runs at **Ring 0** (kernel mode),
and partitions run at **Ring 3** (user mode). There is **no VT-x/VMX usage** in the kernel
source — guest isolation is achieved through **page table partitioning** (separate CR3 per
partition), **I/O port bitmap filtering** (IOPL=0 + TSS I/O bitmap), and **syscall-based IPC**.
This means **Windows guest support requires a fundamentally different approach** than what
PikeOS provides natively — PikeOS is a partitioning hypervisor, not a hardware virtualization
hypervisor. UniversalisOS would need to add **VT-x/VMX support** on top of the PikeOS
partitioning model to run unmodified Windows guests.
---
## 2. File Inventory
### 2.1 Architecture Files (arch/x86/) — 11 files
| File | Size | Purpose |
|------|------|---------|
| `aexcpt.S` | 37KB | IDT vector table + assembly exception entry/exit (256 vectors) |
| `cexcpt.c` | 49KB | C exception dispatch — page faults, GPF, breakpoint, debug, NM, DF |
| `ccontext.c` | 38KB | Context switch: P4_regs_t save/restore, FPU lazy/eager switching |
| `mmu.c` | 34KB | 4-level page tables (PML4→P3→PD→PT), map/unmap/protect, TLB flush |
| `ccontext_ext.c` | 17KB | XSAVE/XRSTOR for AVX/AVX-512, MPX, PKRU extended state |
| `cmm.c` | 15KB | Memory management: phys alloc, DMA, IOMMU integration |
| `adspace.c` | 10KB | Address space CRUD: create/destroy/switch AS (CR3 manipulation) |
| `ccopy.c` | 12KB | Safe user↔kernel memory copy with fault recovery |
| `acopy.S` | 6KB | Assembly optimized memcpy/memset with SMAP/SMEP awareness |
| `acontext.S` | 4KB | Assembly context switch stub (swapgs, iretq) |
| `ioports.c` | 7KB | I/O port access: inb/outb/inw/outw/inl/outl + TSS I/O bitmap |
### 2.2 Key Headers (arch/x86/include/)
| Header | Purpose |
|--------|---------|
| `p4const.h` | Page size (4KB), user space (0→0x7ffffffff000), kernel (0xffff800000000000), 512 interrupts |
| `p4regs.h` | P4_regs_t: 15 GPRs + RIP/RFLAGS/CS/SS + FS/GS base + FPU/SSE/AVX state (64-byte aligned) |
| `p4feature.h` | CPU feature detection (SMEP, SMAP, UMIP, PCID, FSGSBASE, XSAVE) |
| `p4kinfoarch.h` | Architecture kernel info: CR0/CR4 values, EFER, TSC frequency |
| `x86cpu.h` | CPUID wrappers, MSR read/write, CR register manipulation |
| `x86mmu.h` | PML4/P3/PD/PT entry format, PTE flags (P=1, R/W, U/S, NX, PAT, XD) |
| `x86vectors.h` | IDT vector numbers (0-255), IST stack indices |
| `syscall.h` | SYSCALL/SYSRET instruction wrappers, STAR/LSTAR/FMASK MSR setup |
| `p4regoffset.h` | Offsets into P4_regs_t for assembly access |
| `arch_per_cpu.h` | Per-CPU data: current thread, kernel stack, TSC offset, CPUID |
### 2.3 Core Kernel (src/) — 97 files
**Syscall table** (`syscall_table.S`): Maps syscall numbers to C handlers via `sys_*` functions.
**Key subsystems:**
- **Scheduler** (`sched.c`, `sched_readyq.c`, `sched_deadline.c`, `sched_timeout.c`): RMS/EDF/priority scheduling
- **IPC** (`ipc.c`, `sys_ipc.c`, `comm.c`): Sampling + queuing ports, shared memory
- **Memory** (`mm.c`, `mm_balloc.c`, `mm_kmem.c`, `mm_list.c`, `map.c`): Physical allocator, kernel heap, VM map
- **Task/Thread** (`task.c`, `task_attr.c`, `thread.c`, `thread_create.c`, `thread_attr.c`): Task lifecycle
- **Health Monitor** (`hm.c`, `hm_dump.c`, `hm_lookup.c`): 3-tier HM with action injection
- **Interrupts** (`int.c`, `sys_int.c`): IRQ routing, interrupt attachment
- **KDEV** (30+ files): Device abstraction framework (gates, providers, descriptors, I/O)
- **Trace** (`trace.c`, `spider.c`): Instrumentation and tracing
- **Time** (`time.c`, `tps.c`): Time partitioning, timer management
### 2.4 User Library (lib/) — 80+ files
- **Syscall stubs** (`lib/stubs/p4_*.S`): Assembly wrappers for every syscall (SYSCALL instruction)
- **TLS** (`lib/p4_tls_*.c`): Thread-local storage via FS segment base
- **Mutex/Cond/Sem/Barrier** (`lib/p4_mutex_*.c`, etc.): POSIX-like synchronization primitives
- **FPU control** (`lib/p4_thread_fpu_on.c`, `p4_thread_fpu_off.c`): Enable/disable FPU per thread
### 2.5 Kernel Config (.cmp files) — 10 files
| File | Purpose |
|------|---------|
| `kernel.cmp` | Main kernel component (SMP) |
| `kernel-up.cmp` | Uniprocessor kernel variant |
| `kernel-smp.cmp` | SMP-specific config |
| `kernel-cert.cmp` | Certification build config |
| `barekernel.cmp` | Bare kernel (no fusion) |
| `kerneldriver.cmp` | Kernel-space driver support |
| `psp.cmp` | Platform Support Package config |
| `kernel_tags.cmp`, `psp_tags.cmp`, `tracing_tags.cmp` | Trace tag definitions |
---
## 3. Boot Protocol
### 3.1 Multiboot2 (Primary for QEMU/GRUB)
PikeOS boots via **Multiboot2** on x86. The flow:
1. **GRUB2** loads the PikeOS ELF at `PIKEOS_START_ADDRESS`
2. PikeOS preboot code (`multiboot1.bin` for MB1, or direct for MB2) sets up:
- GDT (flat 4GB segments, 64-bit long mode)
- Page tables (PML4 for long mode)
- Stack
3. Transitions to 64-bit long mode
4. Calls kernel `main()`
**Multiboot2 ELF format** (`bs.multiboot`):
```
OUTPUT_FORMAT("elf32-i386") ; Multiboot2 header is 32-bit
ENTRY (_start)
SECTIONS { .text $PIKEOS_START_ADDRESS : { _start = .; *(.text .data) } }
```
**QEMU x86 command** (`bs.qemu`):
```
qemu-system-x86_64 -boot d -cdrom <diskimage> -m <mem> -smp <cpus>
```
PikeOS boots x86 from a **CD-ROM/ISO image** via QEMU.
### 3.2 UEFI Boot
The UEFI boot path (`bs.uefi`) creates an EFI application:
1. PikeOS kernel binary is wrapped with a preboot object (`uefi-x86_amd64.o`)
2. Linked as a shared object with a UEFI-compatible linker script
3. `objcopy` converts to `efi-app-x86-64` PE/COFF format
4. Result is a standalone `.efi` binary for UEFI boot
**This is the path to Windows guest support** — UEFI firmware is required.
### 3.3 GRUB2 Configuration
PikeOS ships a full GRUB2 distribution (`share/grub2/`) with:
- `i386-pc` modules (BIOS boot)
- `x86_64-efi` modules (UEFI boot)
- Custom GRUB configuration for PikeOS Multiboot2
**GRUB2 menu entry:**
```
menuentry "PikeOS <version>" {
multiboot2 /<output_file>
set gfxpayload=text ; or auto for EFI
boot
}
```
### 3.4 Disk Image Boot
For x86 QEMU, PikeOS creates a disk image (ISO) using `prepare_diskimage`:
- The kernel is packaged into a bootable ISO with GRUB2
- QEMU boots from the ISO via `-boot d -cdrom`
---
## 4. Memory Layout (x86_64)
```
0x0000000000000000 - 0x00007ffffffff000 User space (128 TB)
0x00007ffffffff000 - 0xffff7fffffffffff Non-canonical (guard)
0xffff800000000000 - 0xffffffffffdfffff Kernel space (PikeOS kernel + PSP)
0xffffffffffe00000 - 0xffffffffffffffff Kernel info (KINFO_BASE, 2MB)
```
**Page table structure:** 4-level (PML4 → P3 → PD → PT), 4KB pages
- PML4: 512 entries × 512GB = 256 TB
- P3: 512 entries × 1GB = 512GB
- PD: 512 entries × 2MB = 1GB
- PT: 512 entries × 4KB = 2MB
**Large pages:** 2MB (PD level) and 1GB (P3 level) supported
**PTE flags:**
- Bit 0: Present (P)
- Bit 1: Read/Write (R/W)
- Bit 2: User/Supervisor (U/S)
- Bit 3: Page-level Write-Through (PWT)
- Bit 4: Page-level Cache Disable (PCD)
- Bit 7: Page Size (PS) — 2MB/1GB large page
- Bit 8: Global (G)
- Bit 63: Execute Disable (XD/NX)
---
## 5. Context Switch (P4_regs_t)
```c
typedef struct P4_regs_str {
// GPRs (pushed by assembly on syscall/exception entry)
P4_cpureg_t rdi, rsi, rdx, r10, r8, r9, rcx, r11;
P4_cpureg_t rax, rbx, rbp, r12, r13, r14, r15;
// Exception frame (pushed by CPU + assembly)
P4_cpureg_t vector; // Exception vector number
P4_cpureg_t error; // Error code
P4_cpureg_t rip; // Instruction pointer
P4_cpureg_t cs; // Code segment
P4_cpureg_t rflags; // CPU flags
P4_cpureg_t rsp; // Stack pointer
P4_cpureg_t ss; // Stack segment
// Segment bases (for TLS)
P4_cpureg_t fs_base;
P4_cpureg_t gs_base;
// PikeOS internal
P4_cpureg_t reserved[6];
P4_cpureg_t ex_code; // Exception status/reply
P4_cpureg_t usedfpu; // FPU enable flag
// FPU/SSE/AVX state (64-byte aligned)
struct {
struct { /* FXSAVE area: x87 + SSE */ } fxsave;
struct { /* XSAVE header */ } xsave_header;
struct { /* AVX YMM registers */ } avx;
} fpu;
} P4_regs_t __attribute__((aligned(64)));
```
**Syscall entry** (via SYSCALL instruction):
- RCX → RIP (saved return address)
- R11 → RFLAGS
- RAX → syscall number
- RDI, RSI, RDX, R10, R8, R9 → arguments 1-6
---
## 6. Interrupt/Exception Handling
**IDT:** 256 vectors, 64-bit IDT entries (16 bytes each)
**Exception flow:**
1. CPU pushes SS, RSP, RFLAGS, CS, RIP (+ error code for some)
2. Assembly (`aexcpt.S`) saves all GPRs → builds P4_regs_t on stack
3. Loads kernel CR3 (page table switch for Meltdown mitigation)
4. Calls C handler (`cexcpt.c`) with vector number + P4_regs_t
5. C handler dispatches: page fault → mmu.c, GPF → panic, syscall → sys_*
**Key exceptions handled:**
- #PF (14): Page fault → memory management, demand paging
- #GP (13): General protection → I/O port violation, segment violation
- #UD (6): Undefined instruction → FPU/SSE trap (lazy FPU switching)
- #NM (7): Device not available → FPU/SSE/AVX context save/restore
- #DB (1): Debug → breakpoint handling
- #DF (8): Double fault → critical error
**Meltdown mitigation:** Kernel/user page table switching via trampoline code
(`p4x86_int_vectors_meltdown`, `p4x86_set_both_cr3_meltdown`)
---
## 7. x86-Specific Features Used
| Feature | Usage | Status |
|---------|-------|--------|
| **CR3** | Per-partition page tables | ✅ Core isolation mechanism |
| **TSS I/O Bitmap** | I/O port filtering per partition | ✅ Used for device passthrough |
| **SYSCALL/SYSRET** | Fast system call interface | ✅ Primary syscall mechanism |
| **FXSAVE/XSAVE** | FPU/SSE/AVX state save/restore | ✅ Full support |
| **PCID** | Process-context IDs for TLB | ✅ Performance optimization |
| **SMEP/SMAP** | Supervisor mode execution/access prevention | ✅ Security hardening |
| **UMIP** | User-mode instruction prevention | ✅ Security hardening |
| **FSGSBASE** | Fast FS/GS base access | ✅ TLS optimization |
| **TSC** | Time stamp counter for timing | ✅ Primary time source |
| **IOPL** | I/O privilege level (set to 0 for user) | ✅ I/O isolation |
| **VT-x/VMX** | Hardware virtualization | ❌ NOT USED |
---
## 8. Boot Infrastructure (share/boot/)
### Boot Strategies Available
| Strategy | File | Target |
|----------|------|--------|
| `bs.qemu` | QEMU boot (all arches) | x86: cdrom image; arm/aarch64: kernel |
| `bs.grub` | GRUB2 Multiboot2 | x86 (requires GRUB2) |
| `bs.multiboot` | Multiboot1/2 ELF | x86 (generic) |
| `bs.uefi` | UEFI EFI application | x86_64 (requires UEFI firmware) |
| `bs.elf` | Raw ELF boot | All arches |
| `bs.raw` | Raw binary boot | All arches |
| `bs.uboot` | U-Boot boot | ARM/PPC |
| `bs.diskimage` | Disk image (ISO) | x86 (for QEMU cdrom) |
| `bs.fastboot` | Android fastboot | ARM |
| `bs.fastmodel` | ARM Fast Model | ARM |
### QEMU x86 Specifics
```bash
# Minimal QEMU x86 command
qemu-system-x86_64 -boot d -cdrom <image.iso> -m 512
# With SMP
qemu-system-x86_64 -boot d -cdrom <image.iso> -m 512 -smp 4
# With networking (virtio)
qemu-system-x86_64 -boot d -cdrom <image.iso> -m 512 \
-device virtio-net-pci,vlan=0 -net tap,ifname=tap0
# With AHCI storage
qemu-system-x86_64 -boot d -cdrom <image.iso> -m 512 \
-device ich9-ahci,id=ahci0 \
-device ide-drive,bus=ahci0.0,drive=ahcidrive0 \
-drive file=disk.img,if=none,id=ahcidrive0,format=raw
# With USB
qemu-system-x86_64 -boot d -cdrom <image.iso> -m 512 \
-drive if=none,id=usbstick,file=usb.img \
-usb -device nec-usb-xhci,id=xhci \
-device usb-storage,bus=xhci.0,drive=usbstick,port=2
# No graphics (serial console)
qemu-system-x86_64 -nographic -fw_cfg etc/sercon-port,string=0 \
-boot d -cdrom <image.iso>
```
---
## 9. Target/x86 BSP Structure
```
target/x86/amd64/
├── apex/ APEX ARINC-653 personality configs
├── board/ Board-specific .cmp files
├── boot-images/ Boot image configs
├── cenv/ C environment configs
├── cppenv/ C++ environment configs
├── ddk-kerneldriver/ Kernel driver DDK
├── ddk-user-level/ User-level driver DDK
├── driver/ Device driver .cmp files
├── fusion-kernel/ Fusion kernel configs
├── fusion-pssw/ Fusion PSSW configs
├── fusion-volume-provider/ Volume provider configs
├── health-monitoring/ HM configs
├── include/ BSP-specific headers
├── integration/ Integration project configs
├── integration-partition/ Integration partition configs
├── integration-preconf/ Pre-configured integration
├── kernel/ Kernel build configs
├── kerneldriver/ Kernel driver configs
├── ldscript/ Linker scripts
├── lib/ BSP libraries
├── linux/ Linux personality configs
├── makeinc/ Make include files
├── network/ Network configs
├── object/ Object file configs
├── objects/ Object configs
├── partition/ Partition configs
├── pikeos/ PikeOS native personality
├── pikeos-native/ PikeOS native configs
├── posix/ POSIX personality configs
├── preboot/ Preboot objects (multiboot1.bin, uefi-x86_amd64.o)
├── psp/ Platform Support Package
├── pssw/ PSSW configs
├── scov/ Source code coverage configs
├── scov-output/ Coverage output configs
├── scripts/ Build scripts
├── share/ Shared configs
├── systemextension/ System extension configs
└── volume-provider/ Volume provider configs
```
**Total BSP files:** 2,566 files
---
## 10. What's Needed for Windows Guest Support
### 10.1 Current PikeOS Architecture (NOT sufficient for Windows)
PikeOS is a **partitioning hypervisor**, not a hardware virtualization hypervisor:
- Isolation via **page tables** (separate CR3 per partition) + **I/O port bitmap** + **syscall IPC**
- No VT-x/VMX usage — cannot run unmodified OS guests
- Guests must be **PikeOS-aware** (use PikeOS syscalls, not hardware interrupts)
- Cannot trap hardware exceptions into a guest — they go to the kernel
### 10.2 Required Additions for Windows Guest
To run Windows as a guest, UniversalisOS needs **VT-x/VMX hardware virtualization**:
| Component | Effort | Description |
|-----------|--------|-------------|
| **VMX init** | Large | Enable VT-x, set up VMCS, configure VM-exit controls |
| **VMCS management** | Large | VM-entry/exit fields, host/guest state save/restore |
| **EPT (Extended Page Tables)** | Large | Stage-2 translation: guest physical → host physical |
| **VM-exit handler** | Large | Handle CPUID, MSR, I/O, HLT, CR access, EPT violations |
| **APIC virtualization** | Large | Virtual APIC, posted interrupts, TPR virtualization |
| **I/O emulation** | Very Large | Emulate PIT, PIC, PS/2 keyboard/mouse, VGA, serial |
| **UEFI firmware** | Very Large | Embed OVMF/EDK2 as guest firmware for Windows boot |
| **PCI passthrough** | Large | VT-d/IOMMU for device assignment |
| **virtio devices** | Large | virtio-blk, virtio-net, virtio-gpu for paravirtualized I/O |
| **ACPI tables** | Medium | Generate DSDT/SSDT/FADT/MADT for Windows |
| **SMBIOS** | Small | System management BIOS tables |
### 10.3 Recommended Implementation Path
**Phase 1: x86_64 kernel boot** (2-3 months)
- Port PikeOS x86 kernel structure to UniversalisOS
- Multiboot2 boot via GRUB2
- GDT/IDT/TSS setup
- Paging (PML4→PT)
- SYSCALL/SYSRET
- Serial console (UART 16550)
**Phase 2: Partitioning base** (2-3 months)
- Per-partition page tables (CR3 switching)
- Context switch (P4_regs_t equivalent)
- I/O port bitmap (TSS I/O bitmap)
- Basic scheduler
**Phase 3: VT-x/VMX hypervisor** (4-6 months)
- VMX initialization and VMCS setup
- EPT (Extended Page Tables)
- VM-exit handling (CPUID, MSR, I/O, HLT, CR)
- APIC virtualization
- Guest boot (start in real mode, transition through protected to long mode)
**Phase 4: Device emulation** (4-6 months)
- Serial UART (16550)
- PS/2 keyboard/mouse
- VGA/Bochs VGA
- PIT/RTC timer
- PCI/PCIe configuration space
- AHCI/NVMe storage
- virtio-blk, virtio-net, virtio-gpu
**Phase 5: UEFI firmware** (6-12 months)
- Embed OVMF (open-source UEFI firmware) as guest firmware
- Or implement minimal UEFI services for Windows boot
- ACPI table generation
- SMBIOS tables
**Phase 6: Windows boot** (3-6 months)
- Windows installer boot (WinPE)
- Driver integration (virtio-win drivers for paravirtualized I/O)
- GPU passthrough or virtio-gpu
- Network (virtio-net or e1000 emulation)
**Total estimated time to Windows guest: 21-36 months**
---
## 11. Key Differences: PikeOS vs UniversalisOS x86
| Aspect | PikeOS | UniversalisOS (needed) |
|--------|--------|----------------------|
| Boot protocol | Multiboot2/UEFI | Same (replicate) |
| Isolation | Page tables + I/O bitmap | Same + VT-x/EPT |
| Guest awareness | PikeOS syscalls | Unmodified OS (VT-x traps) |
| Interrupts | Kernel handles all | VM-exit → hypervisor → inject to guest |
| Memory | Flat 4GB sections | EPT for nested translation |
| I/O | Direct port access (filtered) | Trapped and emulated |
| Timer | TSC + PIT | Virtual APIC timer + TSC offset |
| SMP | IPI via APIC | Virtual IPI via virtual APIC |
---
## 12. Documentation References
- **PSP Development Guide**: BSP creation workflow, .cmp/.bsp.dom model, linker scripts
- **x86 Platform Manual**: Memory layout, boot protocol, interrupt routing, PCI configuration
- **GCC Compiler Annex**: x86_64 cross-compilation flags, ABI conventions
- **Visual Studio Annex**: Windows host compilation (future: Windows development tooling)
- **TASKING VxToolset Annex**: Alternative compiler support
- **GHS Multi Annex**: Green Hills compiler support
---
## 13. Next Actions
1. **Write x86_64 architecture backend** (`kernel/src/arch/x86_64/`) replicating PikeOS structure
2. **Implement Multiboot2 boot** with GRUB2
3. **Set up GDT/IDT/TSS** for 64-bit long mode
4. **Implement 4-level paging** (PML4→PT)
5. **Add SYSCALL/SYSRET** support
6. **Implement context switch** (P4_regs_t equivalent)
7. **Add VT-x/VMX** initialization (for hardware virtualization)
8. **Implement VMCS** management and VM-exit handling
9. **Add EPT** (Extended Page Tables)
10. **Implement device emulation** (serial, keyboard, VGA, storage)
11. **Embed OVMF** or implement UEFI services
12. **Boot Windows** as guest

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# Deep Audit: ChibiOS, RT-Thread, Contiki, RODOS
## Source locations
- ChibiOS: `/home/fabiorafaelcoutada/portugalfuturista/rtos_ref/ChibiOS/`
- RT-Thread: `/home/fabiorafaelcoutada/portugalfuturista/rtos_ref/rt-thread/`
- Contiki: `/home/fabiorafaelcoutada/portugalfuturista/rtos_ref/contiki/`
- RODOS: `/home/fabiorafaelcoutada/portugalfuturista/rtos_ref/rodos/`
---
# 1. ChibiOS/RT v8.0.0
## 1.1 Architecture Support
**Port layers** in `os/common/ports/`:
- ARM, ARM-common, ARMv6-M, ARMv7-M, ARMv7-M-ALT, ARMv7-R, ARMv8-M-ML, ARMv8-M-ML-ALT, ARMv8-M-ML-TZ, ARMvx-M-SB
- AVR, e200 (PowerPC NXP), SIMIA32, SIMX86_64
**HAL ports** in `os/hal/ports/`:
- ADUCM (Analog Devices), AVR, LPC (NXP), MAX32, RP (Raspberry Pi RP2040), SPC5 (ST PowerPC), STM32 (C0/F0/F1/F3/F4/F7/G0/G4/H5/H7/L0/L1/L4/L5/MP1/U0/U3/U5/WB/WL), simulator
**Demo BSPs** in `demos/`:
- ADUCM, AVR (Arduino UNO/MEGA/MINI/NANO/Leonardo, DigiSpark ATTiny, MT-DB-X4), LPC21xx, MAX32, RP, SPC5, STM32, various
**Key takeaway**: Broad ARM Cortex-M coverage (M0/M0+/M3/M4/M7/M23/M33/M55/M85 with TrustZone), AVR, PPC e200, simulator (x86/x86_64).
## 1.2 Memory Model
**No MMU required.** Flat memory model with static allocation as primary pattern.
File: `os/rt/include/chmem.h`
- **Static working areas**: `THD_WORKING_AREA(s, n)` allocates thread stack + `thread_t` struct in BSS
- **NUMA memory classes**: `CH_MEM_GLOBAL_BSS`, `CH_MEM_LOCAL_BSS(c)`, `CH_MEM_PRIVATE_BSS(c)`, plus coherent variants for SMP cache management
- **No heap allocator in kernel**: ChibiOS relies on statically allocated pools. Dynamic allocation is optional via `oslib/` (heap, mempool, mailbox abstractions)
- Stack guard via MPU (`PORT_ENABLE_GUARD_PAGES` on ARMv7-M)
**Design pattern**: Pre-allocated working areas, no `malloc()` in kernel. Thread stacks are compile-time sized arrays.
## 1.3 Kernel Primitives
### Threads (`os/rt/include/chthreads.h`, `os/rt/src/chthreads.c`)
```c
typedef void (*tfunc_t)(void *p);
// Static creation
thread_t *chThdCreateStatic(void *wsp, size_t size, tprio_t prio, tfunc_t tp, void *arg);
thread_t *chThdCreateI(...); // from ISR context
// Dynamic creation (requires CH_CFG_USE_DYNAMIC)
thread_t *chThdCreate(...);
// Control
void chThdExit(msg_t msg);
void chThdTerminate(thread_t *tp);
msg_t chThdWait(thread_t *tp); // join
void chThdSleep(sysinterval_t ticks);
void chThdSleepUntil(systime_t time);
void chThdYield(void);
void chThdSuspendS(thread_t *tpp);
void chThdResumeI(thread_t *tp, msg_t msg);
```
**Thread states** (16 states, `chschd.h`):
```
READY, CURRENT, WTSTART, SUSPENDED, QUEUED, WTSEM, WTMTX,
WTCOND, SLEEPING, WTEXIT, WTOREVT, WTANDEVT, SNDMSGQ, SNDMSG, WTMSG, FINAL
```
### Scheduler (`os/rt/include/chschd.h`, `os/rt/src/chschd.c`)
```c
void chSchReadyI(thread_t *tp); // insert in ready list
void chSchGoSleepS(tstate_t newstate); // sleep
msg_t chSchGoSleepTimeoutS(tstate_t, sysinterval_t);
void chSchWakeupS(thread_t *ntp, msg_t msg);
void chSchRescheduleS(void);
void chSchDoPreemption(void);
void chSchDoYieldS(void);
thread_t *chSchSelectFirst(void);
```
**Priority-based preemptive** ready list. Priorities 1-255 (IDLE=1, LOW=2, NORMAL=128, HIGH=255). `ch_sch_prio_insert()` walks sorted doubly-linked list. Supports `CH_CFG_TIME_QUANTUM` for round-robin among equal-priority threads.
### IPC Primitives
**Semaphores** (`chsem.h`):
```c
void chSemObjectInit(semaphore_t *sp, cnt_t n);
msg_t chSemWait(semaphore_t *sp);
msg_t chSemWaitTimeout(semaphore_t *sp, sysinterval_t timeout);
void chSemSignal(semaphore_t *sp);
void chSemSignalI(semaphore_t *sp); // ISR-safe
msg_t chSemSignalWait(semaphore_t *sps, semaphore_t *spw); // atomic signal+wait
```
**Mutexes** (`chmtx.h`) with **priority inheritance**:
```c
void chMtxLock(mutex_t *mp);
bool chMtxTryLock(mutex_t *mp);
void chMtxUnlock(mutex_t *mp);
void chMtxUnlockAll(void); // unlock all mutexes held by current thread
```
Mutex structure has `owner`, `next` (linked list on thread), optional `cnt` for recursive.
**Condition Variables** (`chcond.h`):
```c
void chCondSignal(condition_variable_t *cp);
void chCondBroadcast(condition_variable_t *cp);
msg_t chCondWait(condition_variable_t *cp);
```
**Events** (`chevents.h`) - event flags model:
```c
void chEvtRegisterMaskWithFlags(event_source_t *esp, event_listener_t *elp, eventmask_t events, eventflags_t wflags);
void chEvtSignal(thread_t *tp, eventmask_t events);
eventmask_t chEvtWaitAny(eventmask_t events);
eventmask_t chEvtWaitAll(eventmask_t events);
void chEvtDispatch(const evhandler_t *handlers, eventmask_t events);
```
Event listeners link to event sources. Uses bitmask model (eventmask_t + eventflags_t).
**Synchronous Messages** (`chmsg.h`) - rendezvous-style:
```c
msg_t chMsgSend(thread_t *tp, msg_t msg); // blocking send, returns reply
thread_t *chMsgWait(void); // blocking receive
void chMsgRelease(thread_t *tp, msg_t msg); // reply
```
### ChibiOS/NIL (ultra-lightweight variant, `os/nil/`)
- Only 4 source files: `ch.c`, `chevt.c`, `chmsg.c`, `chsem.c`
- Cooperative only, no preemption
- Fixed number of threads (compile-time)
- Minimal states: WTSTART, READY, SLEEPING, SUSPENDED, WTEXIT, WTQUEUE, WTOREVT, WTANDEVT, SNDMSGQ, SNDMSG, WTMSG
- ~1KB footprint, ideal for 8-bit MCUs
## 1.4 API Surface
Single include: `#include "ch.h"` → pulls all kernel headers:
```
chearly.h → chrfcu.h → chdebug.h → chtime.h → chalign.h → chtrace.h →
chport.h → chsafety.h → chlists.h → chtmm → chstats.h → chobjects.h →
chmem.h → chsys.h → chinstances.h → chvt.h → chschd.h → chthreads.h →
chregistry.h → chsem.h → chmtx.h → chcond.h → chevents.h → chmsg.h →
chlib.h (OSLIB) → chdynamic.h
```
**Locking model**: Three-class API with `S` suffix (caller must hold system lock), `I` suffix (caller must be in ISR), no suffix (API-level, acquires lock internally):
```c
chSysLock(); // enter critical section
chSysUnlock(); // exit critical
```
## 1.5 Hardware Abstraction
Port layer contract (`os/rt/include/chport.h`) requires every port to define:
```c
PORT_COMPILER_NAME, PORT_IDLE_THREAD_STACK_SIZE, PORT_INT_REQUIRED_STACK,
PORT_SUPPORTS_RT, PORT_NATURAL_ALIGN, PORT_STACK_ALIGN, PORT_WORKING_AREA_ALIGN,
PORT_ARCHITECTURE_NAME, PORT_CORE_VARIANT_NAME, PORT_INFO,
PORT_IRQ_IS_VALID_PRIORITY, PORT_IRQ_IS_VALID_KERNEL_PRIORITY,
PORT_SETUP_CONTEXT, PORT_WA_SIZE, PORT_IRQ_PROLOGUE, PORT_IRQ_EPILOGUE,
PORT_IRQ_HANDLER, PORT_FAST_IRQ_HANDLER
```
HAL layer (`os/hal/`): Full driver abstraction for ADC, CAN, DAC, EXT, GPT, I2C, ICU, MAC, PAL (GPIO), PWM, RTC, SDC, SERIAL, SIO, SPI, UART, USB, WDG. Each has a `hal_xxx_lld.h` low-level driver per port.
## 1.6 Tick/Timer Infrastructure
File: `os/rt/include/chvt.h`, `os/rt/src/chvt.c`
**Two modes**:
1. **Tick mode** (`CH_CFG_ST_TIMEDELTA == 0`): Regular SysTick interrupt increments `currcore->vtlist.systime`. Virtual timers stored in delta list.
2. **Tickless mode** (`CH_CFG_ST_TIMEDELTA > 0`): Hardware timer programmed for exact next wakeup. `port_timer_get_time()` returns current time.
```c
void chVTDoSetI(virtual_timer_t *vtp, sysinterval_t delay, vtfunc_t vtfunc, void *par);
void chVTDoSetContinuousI(virtual_timer_t *vtp, sysinterval_t delay, vtfunc_t vtfunc, void *par);
void chVTDoResetI(virtual_timer_t *vtp);
void chVTDoTickI(void); // called from tick ISR or timer ISR
systime_t chVTGetSystemTimeX(void);
```
Virtual timer is a delta-list node with callback. Supports one-shot and continuous (auto-reload).
## 1.7 Cooperative vs Preemptive
**ChibiOS/RT**: Fully **preemptive** by default. Priority-based preemption. Optional time quantum for round-robin at same priority (`CH_CFG_TIME_QUANTUM > 0`). No cooperative-only mode.
**ChibiOS/NIL**: **Cooperative only**. Threads yield explicitly. No preemption. Ultra-minimal for deeply constrained targets.
---
# 2. RT-Thread v5.3.0
## 2.1 Architecture Support
**libcpu/** supports 21 architecture families:
- aarch64, arc, arm (23 sub-ports: am335x, arm926, armv6, AT91SAM7S/X, cortex-a/m0/m23/m3/m33/m4/m7/m85/r4/r52, dm36x, lpc214x/lpc24xx, s3c24x0/s3c44b0, sep4020, zynqmp-r5)
- avr32, blackfin, c-sky, ia32, m16c, mips, nios, ppc, risc-v, rx, sim, sparc-v8, ti-dsp, unicore32, v850, xilinx
**BSP/**: 107 board support packages including STM32 (full range), GD32, Infineon, Renesas, NXP, Allwinner, Raspberry Pi, QEMU (aarch64, riscv, virt64), RISC-V (hifive1, rv32m1_vega), x86, simulator, and many Chinese MCU vendors.
## 2.2 Memory Model
**No MMU required.** Three memory allocation strategies (compile-time selectable):
1. **Small Memory** (`src/mem.c`, `RT_USING_SMALL_MEM`): First-fit allocator from contiguous heap. `rt_smem_init()` takes a begin address + size. Items linked via `next`/`prev` offsets. Coalescing on free. O(n) worst-case.
2. **SLAB allocator** (`src/slab.c`, `RT_USING_SLAB`): Derived from DragonFly BSD. 72 zones, chunk sizes 8B to 16KB. Page-based backing. O(1) alloc/free for common sizes.
3. **Memory heap** (`src/memheap.c`, `RT_USING_MEMHEAP`): Multiple disjoint memory regions managed as a single logical heap. Good for systems with non-contiguous RAM (e.g., SRAM + external SDRAM).
4. **Memory pool** (`src/mempool.c`): Fixed-size block pool, O(1) alloc/free.
**Key API**:
```c
void *rt_malloc(rt_size_t nbytes);
void rt_free(void *ptr);
void *rt_realloc(void *ptr, rt_size_t nbytes);
void *rt_calloc(rt_size_t count, rt_size_t size);
rt_smem_t rt_smem_init(const char *name, void *begin_addr, rt_size_t size);
```
## 2.3 Kernel Primitives
### Threads (`src/thread.c`, `include/rtdef.h`)
```c
// Static creation
rt_err_t rt_thread_init(struct rt_thread *thread, const char *name,
void (*entry)(void *parameter), void *parameter,
void *stack_start, rt_uint32_t stack_size, rt_uint8_t priority, rt_uint32_t tick);
// Dynamic creation
rt_thread_t rt_thread_create(const char *name, void (*entry)(void *parameter),
void *parameter, rt_uint32_t stack_size, rt_uint8_t priority, rt_uint32_t tick);
rt_err_t rt_thread_startup(rt_thread_t thread);
rt_err_t rt_thread_delay(rt_tick_t tick);
rt_err_t rt_thread_yield(void);
rt_err_t rt_thread_suspend(rt_thread_t thread);
rt_err_t rt_thread_resume(rt_thread_t thread);
rt_err_t rt_thread_control(rt_thread_t thread, int cmd, void *arg);
rt_thread_t rt_thread_self(void);
```
**Thread control block** (`rtdef.h:852`):
```c
struct rt_thread {
struct rt_object parent; // inherit from kernel object
void *sp, *entry, *parameter, *stack_addr;
rt_uint32_t stack_size;
rt_err_t error;
RT_SCHED_THREAD_CTX; // scheduler-specific context
struct rt_timer thread_timer; // built-in thread timer
rt_thread_cleanup_t cleanup;
rt_list_t taken_object_list; // mutex tracking for priority inheritance
rt_object_t pending_object;
rt_uint32_t event_set;
rt_uint8_t event_info;
// ... signals, pthreads, LWP fields
};
```
### Scheduler (`src/scheduler_comm.c`, `src/scheduler_up.c`, `src/scheduler_mp.c`)
**Two scheduler variants**:
1. **UP (uniprocessor)**: Bit-map priority scheduler. `priority_group` + `ready_table[32]` for O(1) highest-priority lookup. Up to 256 priority levels.
2. **MP (multiprocessor/SMP)**: Per-CPU ready queues, IPI-based preemption, CPU affinity binding.
```c
void rt_sched_thread_init_ctx(struct rt_thread *thread, rt_uint32_t tick, rt_uint8_t priority);
rt_err_t rt_sched_thread_ready(struct rt_thread *thread);
```
### IPC (`src/ipc.c`)
**Semaphores**:
```c
rt_err_t rt_sem_init(rt_sem_t sem, const char *name, rt_uint32_t value, rt_uint8_t flag);
rt_err_t rt_sem_take(rt_sem_t sem, rt_int32_t timeout);
rt_err_t rt_sem_release(rt_sem_t sem);
```
**Mutexes** with priority inheritance + priority ceiling:
```c
rt_err_t rt_mutex_init(rt_mutex_t mutex, const char *name, rt_uint8_t flag);
rt_err_t rt_mutex_take(rt_mutex_t mutex, rt_int32_t timeout);
rt_err_t rt_mutex_release(rt_mutex_t mutex);
```
**Events** (32-bit bitmask):
```c
rt_err_t rt_event_init(rt_event_t event, const char *name, rt_uint8_t flag);
rt_err_t rt_event_recv(rt_event_t event, rt_uint32_t set, rt_uint8_t option, rt_int32_t timeout, rt_uint32_t *recved);
rt_err_t rt_event_send(rt_event_t event, rt_uint32_t set);
```
**Mailbox** (fixed-size message slots):
```c
rt_err_t rt_mb_init(rt_mailbox_t mb, const char *name, void *msgpool, rt_size_t size, rt_uint8_t flag);
rt_err_t rt_mb_send(rt_mailbox_t mb, rt_ubase_t value);
rt_err_t rt_mb_recv(rt_mailbox_t mb, rt_ubase_t *value, rt_int32_t timeout);
```
**Message Queue** (variable-size messages):
```c
rt_err_t rt_mq_init(rt_mq_t mq, const char *name, void *msgpool, rt_size_t msg_size, rt_size_t pool_size, rt_uint8_t flag);
rt_err_t rt_mq_send(rt_mq_t mq, const void *buffer, rt_size_t size);
rt_err_t rt_mq_recv(rt_mq_t mq, void *buffer, rt_size_t size, rt_int32_t timeout);
```
IPC flags: `RT_IPC_FLAG_PRIO` (priority-ordered waiters) or `RT_IPC_FLAG_FIFO`.
## 2.4 API Surface
Single include: `#include <rtthread.h>` → `rtdef.h`, `rtservice.h`, `rtm.h`, `rtatomic.h`, `rtklibc.h`
**Object system**: All kernel objects inherit from `struct rt_object` with name, type, flag, list node. Enables runtime object discovery via `rt_object_find()`.
**Initialization export macros** for component init ordering:
```c
INIT_BOARD_EXPORT(fn) // level "1"
INIT_DEVICE_EXPORT(fn) // level "3"
INIT_COMPONENT_EXPORT(fn)// level "4"
INIT_APP_EXPORT(fn) // level "6"
```
**Hook system**: Per-operation hooks (`rt_thread_suspend_sethook`, `rt_timer_enter_sethook`, etc.) plus hook lists for multiple subscribers.
## 2.5 Hardware Abstraction
**libcpu/** per-arch provides:
```c
rt_uint8_t *rt_hw_stack_init(void *entry, void *parameter, rt_uint8_t *stack_addr, void *exit);
void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to);
void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to, rt_thread_t from_thread, rt_thread_t to_thread);
rt_base_t rt_hw_interrupt_disable(void);
void rt_hw_interrupt_enable(rt_base_t level);
void rt_hw_cpu_reset(void);
void rt_hw_cpu_shutdown(void);
```
**BSP/** per-board provides system clock, peripheral init, linker script, console.
**Device framework** (`include/rtdef.h`): `struct rt_device` with `rt_device_ops` (init, open, close, read, write, control).
## 2.6 Tick/Timer Infrastructure
File: `src/clock.c`, `src/timer.c`
```c
rt_tick_t rt_tick_get(void);
void rt_tick_increase(void); // called from SysTick ISR
void rt_tick_increase_tick(rt_tick_t tick); // multi-tick advance
void rt_timer_init(rt_timer_t timer, const char *name,
void (*timeout)(void *parameter), void *parameter,
rt_tick_t time, rt_uint8_t flag);
rt_err_t rt_timer_start(rt_timer_t timer);
rt_err_t rt_timer_stop(rt_timer_t timer);
rt_err_t rt_timer_control(rt_timer_t timer, int cmd, void *arg);
```
Timer flags: `RT_TIMER_FLAG_ONE_SHOT` / `RT_TIMER_FLAG_PERIODIC`, `RT_TIMER_FLAG_HARD_TIMER` (callback in ISR) / `RT_TIMER_FLAG_SOFT_TIMER` (callback in timer thread). Uses **skip list** for O(log n) timer insertion (`RT_TIMER_SKIP_LIST_LEVEL`).
## 2.7 Cooperative vs Preemptive
**Fully preemptive** by default. Priority-based preemption with optional time-slice round-robin (`tick` parameter per thread). SMP variant adds per-CPU scheduling with IPI-triggered rescheduling.
No explicit cooperative mode, but a thread can yield voluntarily with `rt_thread_yield()`.
---
# 3. Contiki OS (v3.x)
## 3.1 Architecture Support
**Platform directory** (`platform/`) with 33 platforms:
- AVR: atmega128rfa1, raven, ravenlcd, ravenusb, rcb, rss2, zigbit
- ARM: cc2538dk, nrf52dk, openmote-cc2538, srf06-cc26xx, stm32nucleo-spirit1, stm32test, zoul
- MSP430: exp5438, sky, wismote, z1
- x86: native (Linux host), win32, galileo, minimal-net
- Simulators: cooja, cooja-ip64
- Other: cc2530dk, econotag, ev-aducrf101mkxz, jn516x, mbxxx, micaz, seedeye
**No libcpu separation** — each platform provides its own clock, rtimer, and radio drivers directly.
## 3.2 Memory Model
**No MMU. No dynamic memory allocation in the kernel.**
Contiki uses **no heap at all** by default. Everything is statically allocated:
- Process structures are compile-time macros
- Event queue is a fixed-size array: `static struct event_data events[PROCESS_CONF_NUMEVENTS]` (default 32)
- Protothread state is a single `char` in the process struct (local continuation)
- No thread stacks — protothreads share the main stack
**This is the most memory-efficient model of all four RTOSes.** A protothread is literally a single byte of state.
## 3.3 Kernel Primitives
### Protothreads (`core/sys/pt.h`)
Protothreads are **stackless threads** implemented as C macros using Duff's device (local continuations):
```c
struct pt { lc_t lc; }; // lc_t is typically a char
PT_THREAD(my_thread(struct pt *pt, process_event_t ev, process_data_t data));
#define PT_BEGIN(pt) // start
#define PT_END(pt) // end
#define PT_WAIT_UNTIL(pt, condition) // block until condition
#define PT_WAIT_WHILE(pt, condition) // block while condition
#define PT_YIELD(pt) // yield to scheduler
#define PT_SPAWN(pt, child, thread) // spawn child protothread
```
**No per-thread stack.** Each protothread is a function that returns `PT_WAITING`, `PT_YIELDED`, `PT_EXITED`, or `PT_ENDED`. The continuation point is stored in `lc_t` (typically 1 byte using GCC computed goto labels, or 2 bytes using switch-based Duff's device).
### Processes (`core/sys/process.h`, `core/sys/process.c`)
```c
PROCESS_THREAD(name, ev, data); // declare process
PROCESS_NAME(name); // get process name
void process_start(struct process *p, process_data_t data);
void process_exit(struct process *p);
int process_post(struct process *p, process_event_t ev, process_data_t data);
void process_poll(struct process *p);
process_event_t process_alloc_event(void);
```
Each process wraps a protothread:
```c
struct process {
struct process *next;
const char *name;
PT_THREAD((*thread)(struct pt *, process_event_t, process_data_t));
struct pt pt;
unsigned char state, needspoll;
};
```
### Event System
**Synchronous event dispatch** via `process_run()`:
```c
// In main loop:
while(1) {
do {} while(process_run() > 0); // dispatch events
// low-power sleep if no events
}
```
Events are posted to a **fixed-size circular queue** (`events[PROCESS_CONF_NUMEVENTS]`). Pre-defined events: `PROCESS_EVENT_INIT`, `PROCESS_EVENT_POLL`, `PROCESS_EVENT_EXIT`, `PROCESS_EVENT_TIMER`, `PROCESS_EVENT_CONTINUE`, etc.
### No mutexes, semaphores, or message queues
Contiki has **none of these**. Synchronization is entirely event-driven + protothread blocking conditions. `core/sys/pt-sem.h` provides a minimal counting semaphore for protothreads.
## 3.4 API Surface
Main includes: `contiki.h`, `contiki-net.h`, `contiki-lib.h`
```c
// Process macros
PROCESS_THREAD(), PROCESS_BEGIN(), PROCESS_END(), PROCESS_YIELD()
PROCESS_WAIT_EVENT(), PROCESS_WAIT_EVENT_UNTIL()
PROCESS_POLL_AND_EXIT()
// Timer APIs
timer_set(), timer_reset(), timer_expired()
etimer_set(), etimer_reset(), etimer_expired()
ctimer_set(), ctimer_reset(), ctimer_expired()
stimer_set(), stimer_expired()
rtimer_set()
// Event APIs
process_post(), process_poll()
```
## 3.5 Hardware Abstraction
Each platform provides:
- `clock.c` / `clock.h`: System tick
- `rtimer-arch.c`: Real-time timer
- `*contiki-conf.h`: Platform configuration
- Radio driver (for networking)
No unified HAL layer — each platform is self-contained.
## 3.6 Tick/Timer Infrastructure
**Four timer layers** (coexisting):
1. **timer** (`core/sys/timer.h`): Simple interval timer, checked by polling `timer_expired()`. Uses `clock_time_t` (typically 16-bit).
2. **etimer** (`core/sys/etimer.h`): Event timer — posts `PROCESS_EVENT_TIMER` to the owning process when expired. Linked list managed by `etimer_request_poll()`.
3. **ctimer** (`core/sys/ctimer.h`): Callback timer — calls a function pointer on expiry.
4. **rtimer** (`core/sys/rtimer.h`): Real-time timer with **microsecond precision**, runs from ISR context. Used for time-critical radio operations.
```c
// Clock layer
void clock_init(void);
clock_time_t clock_time(void); // typically 32 ticks/sec
unsigned long clock_seconds(void);
#define CLOCK_SECOND (clock_time_t)32
// rtimer
void rtimer_set(struct rtimer *rt, rtimer_clock_t time, rtimer_clock_t duration,
rtimer_callback_t func, void *ptr);
```
## 3.7 Cooperative vs Preemptive
**Purely cooperative.** Protothreads yield explicitly via `PT_YIELD()`, `PT_WAIT_UNTIL()`, etc. No preemption. The main loop runs `process_run()` which dispatches one event at a time.
The only "preemption" is ISR-level rtimer callbacks, which run in interrupt context and must not block.
---
# 4. RODOS (Realtime Onboard Dependable Operating System) v2.x
## 4.1 Architecture Support
**Bare-metal ports** (`src/bare-metal/`):
- **Cortex-M** (`src/bare-metal-cortex-m/`): Generic Cortex-M port with PendSV-based context switch
- **STM32F4**: STM32F4xx (F407, F411 discovery boards)
- **STM32H7**: STM32H7xx (H723, H735, H745, H753 — Nucleo, Discovery, custom boards)
- **STM32L4**: STM32L431, L432, L475, L496 (Nucleo L432KC, L496ZG, Discovery L475)
- **STM32WB**: STM32WB55 Nucleo (BLE-capable)
- **EFR32FG1P**: Silicon Labs EFR32 Flex Gecko (Thunderboard)
- **VA41620**: Vorago VA41620 (radiation-hardened Cortex-M4)
- **SF2**: Microsemi SmartFusion2 (Cortex-M3 + FPGA)
- **Raspberry Pi 3**: Bare-metal AArch64
- **Linux x86**: Linux-hosted with makecontext/setcontext
- **Template**: Porting template
**POSIX simulation** (`src/on-posix/`, `src/on-posix-mac/`): Run as Linux/macOS process using POSIX threads.
## 4.2 Memory Model
**No MMU required.** Fully static memory model in C++.
- **Threads** use either static stacks (via template) or dynamic `new` (deprecated):
```cpp
template <size_t STACK_SIZE>
Thread(char (&stack)[STACK_SIZE], const char* name, const int32_t priority);
// deprecated: Thread(const char* name, int32_t priority, size_t stackSize);
```
- **StaticThread<STACK_SIZE>** is the recommended pattern (compile-time sized stack array).
- No heap allocator in kernel. All kernel objects (`Thread`, `Semaphore`, `TimeEvent`, `Topic`, `Subscriber`) are statically constructed C++ objects created before `main()`.
- Stack grows downward. Sentinel value `0xdeaddead` placed at stack base for overflow detection.
## 4.3 Kernel Primitives
### Threads (`api/thread.h`, `src/independent/thread.cpp`)
C++ class with virtual `run()` method:
```cpp
class Thread : public ListElement {
public:
Thread(const char* name, int32_t priority, size_t stackSize);
template <size_t STACK_SIZE>
Thread(char (&stack)[STACK_SIZE], const char* name, int32_t priority);
virtual void run() = 0; // user implements
virtual void init() {} // called before run()
static bool suspendCallerUntil(int64_t reactivationTime = END_OF_TIME, void* signaler = 0);
void suspendUntilNextBeat();
void setPeriodicBeat(int64_t begin, int64_t period);
void resume();
void resumeAndYield();
static void yield();
static Thread* getCurrentThread();
static Thread* findNextToRun(int64_t& selectedEarliestSuspendedUntil);
static Thread* findNextWaitingFor(void* signaler);
};
```
Thread state tracked via:
```cpp
Atomic<long*> context{nullptr}; // saved stack pointer
Atomic<int32_t> priority{};
Atomic<int64_t> suspendedUntil{0}; // wake time
Atomic<void*> waitingFor{nullptr}; // synchronization target
Atomic<uint64_t> lastActivation{0};
```
### Scheduler
**Priority-based preemptive** scheduler using PendSV on Cortex-M:
- `Thread::findNextToRun()` iterates all threads, selects highest-priority ready thread
- Context switch via PendSV interrupt: save R4-R11 + EXC_RETURN to PSP, call `schedulerWrapper()`, restore next thread's context
- SVC handler for first thread start (idle thread)
- Time-driven: scheduler triggered by `TimeEvent::propagate()` in SysTick
```cpp
// Context switch chain (Cortex-M):
__asmSaveContextAndCallScheduler() → SCB->ICSR |= PENDSVSET →
PendSV_Handler: save regs → schedulerWrapper() → restore next thread regs
```
### Semaphore (`api/rodos-semaphore.h`)
**Mutex semaphore** with priority ceiling:
```cpp
class Semaphore {
Atomic<Thread*> owner;
Atomic<int32_t> ownerEnterCnt; // reentrant lock count
Atomic<int32_t> ownerPriority;
public:
void enter(); // blocking lock
void leave(); // unlock + resume highest-priority waiter
};
// RAII guard
class ScopeProtector { ... };
#define PROTECT_IN_SCOPE(_sema)
```
### Barrier (`api/barrier.h`)
```cpp
class Barrier {
Thread* volatile owner;
public:
bool waitForSignal(bool condition = true, int64_t timeOutAt = END_OF_TIME);
bool unblock();
};
```
### Event (`api/event.h`)
```cpp
class Event {
bool state_;
Thread *waiter_; // only ONE waiter!
public:
bool set(void); // trigger + optionally resume waiter
bool suspendUntilTriggered(int64_t timeout = END_OF_TIME);
void reset(void);
};
```
### Topic/Subscriber (Publish-Subscribe middleware, `api/topic.h`)
```cpp
template <class Type>
class Topic : public TopicInterface {
public:
Topic(int64_t id, const char* name, bool onlyLocal = false);
uint32_t publish(Type &msg, bool shallSendToNetwork = true);
};
class Subscriber : public SubscriberInterface {
public:
Subscriber(TopicInterface &topic, const char* name = "Subscriber");
virtual void put(uint32_t topicId, size_t len, void *msg, ...) = 0;
};
```
### Gateway (inter-node communication, `api/gateway/`)
```cpp
class Gateway : public ListElement {
virtual bool sendNetworkMessage(NetworkMessage &msg);
virtual void onIncomingMessage(NetworkMessage &msg);
};
```
Link interfaces: CAN, UART, UDP, Shared Memory.
### CommBuffer (`api/commbuffer.h`)
```cpp
template <class Type>
class CommBuffer { ... }; // lock-free single-producer/single-consumer buffer
```
## 4.4 API Surface
Language: **C++ (C++11 minimum)**. Single master header: `#include <rodos.h>` → `api/rodos.h`
Key headers:
```
thread.h, rodos-semaphore.h, barrier.h, event.h, topic.h, subscriber.h,
timeevent.h, timemodel.h, hal.h, gateway.h, commbuffer.h, application.h,
fifo.h, putter.h
```
**Application model**:
```cpp
class Application : public ListElement {
virtual long init() { return 0; }
virtual void run() { }
};
```
All `Application` and `Thread` instances are global objects. `main()` calls `initSystem()` → `initAllThreads()` → `startIdleThread()`.
## 4.5 Hardware Abstraction
File: `api/hal.h`, `api/hal/hal_*.h`
```cpp
class HW_HAL { /* base for all HW peripherals */ };
class GPIO : public HW_HAL { ... };
class UART : public HW_HAL { ... };
class SPI : public HW_HAL { ... };
class I2C : public HW_HAL { ... };
class ADC : public HW_HAL { ... };
class PWM : public HW_HAL { ... };
class CAN : public HW_HAL { ... };
class Ethernet : public HW_HAL { ... };
class SharedMemory : public HW_HAL { ... };
```
Each port implements the HAL classes. Platform-specific code in `src/bare-metal/<platform>/hal/`.
## 4.6 Tick/Timer Infrastructure
File: `api/timeevent.h`, `src/independent/timeevent.cpp`, `src/independent/timemodel.cpp`
```cpp
class TimeEvent : public ListElement {
static List timeEventList;
Atomic<int64_t> eventAt;
Atomic<int64_t> eventPeriod;
public:
virtual void handle(void) {} // override for custom handling
void activateAt(int64_t time);
void activatePeriodic(int64_t startAt, int64_t period);
static int32_t propagate(int64_t timeNow); // called from tick ISR
static int64_t getNextTriggerTime();
};
```
**Time model**: Uses nanosecond-precision `int64_t` time (`Nanoseconds`, `Microseconds`, `Milliseconds`, `Seconds` are all int64_t aliases). `NOW()` returns current time. `TimeModel::computeNextBeat()` handles period computation.
Tick ISR calls `TimeEvent::propagate(NOW())` which:
1. Iterates all TimeEvents
2. Fires handlers where `eventAt < now`
3. Updates `eventAt` for periodic events
4. Triggers scheduler if a thread became ready
## 4.7 Cooperative vs Preemptive
**Fully preemptive** via PendSV on Cortex-M:
- `TimeEvent::propagate()` runs in SysTick ISR
- When a higher-priority thread becomes ready, `__asmSaveContextAndCallScheduler()` triggers PendSV
- PendSV performs full context switch (R4-R11 + EXC_RETURN, optionally S16-S31 for FPU)
- `Thread::yield()` calls `resume()` + triggers reschedule
On POSIX platforms: preemption via POSIX signals (`SIGALRM` or timer threads).
---
# Comparative Summary for UniversalisOS
| Feature | ChibiOS/RT | RT-Thread | Contiki | RODOS |
|---------|-----------|-----------|---------|-------|
| **Language** | C | C | C | C++ |
| **Arch support** | ARM, AVR, PPC, x86 | 21 families, 107 BSPs | 33 platforms (sensor nodes) | ARM Cortex-M, RPi3, POSIX |
| **MMU needed** | No | No (optional RT-Smart uses it) | No | No |
| **Memory model** | Static working areas | Heap (small/slab/mempool) | Zero-allocation | Static C++ objects |
| **Thread model** | Preemptive, priority | Preemptive, priority | Stackless protothreads | Preemptive, priority |
| **Context switch** | SVC/PendSV (ARM) | arch-specific | None (continuation) | PendSV (ARM) |
| **IPC** | Sem, Mutex, CondVar, Events, Msg | Sem, Mutex, Event, MB, MQ | Event queue only | Sem, Barrier, Event, Topic/Subscriber |
| **Priority inherit.** | Yes (mutex) | Yes (mutex + ceiling) | N/A | Yes (semaphore) |
| **SMP** | Yes (CH_CFG_SMP_MODE) | Yes (RT_USING_SMP) | No | No (single-core) |
| **Timer** | Virtual timer delta list | Skip-list timer | 4-layer (timer/etimer/ctimer/rtimer) | TimeEvent list |
| **Tickless** | Yes (CH_CFG_ST_TIMEDELTA) | No (tick-based) | rtimer is real-time | Yes (nanosecond time) |
| **Min footprint** | ~1KB (NIL), ~5KB (RT) | ~3KB (nano mode) | ~1KB (protothreads) | ~2KB (Cortex-M) |
| **Scheduling** | Preemptive + round-robin | Preemptive + round-robin | Cooperative only | Preemptive |
## Key Design Patterns for UniversalisOS
1. **ChibiOS port contract** (`chcore.h`): Excellent model for hypervisor port layer. Defines exact macros every port must export (stack init, IRQ prologue/epilogue, context setup, priority validation).
2. **RT-Thread object system**: Uniform kernel object model with name, type, list node. Enables `rt_object_find()` for runtime discovery. Good pattern for hypervisor resource management.
3. **Contiki protothreads**: Zero-overhead "threads" for monitoring/management tasks that never need to block on hardware. Could be used for hypervisor event handlers.
4. **RODOS Topic/Subscriber**: Built-in publish-subscribe middleware for inter-partition communication in a hypervisor. The Gateway/LinkInterface pattern maps directly to inter-VM communication.
5. **ChibiOS SMP memory classes**: `CH_MEM_GLOBAL_COHERENT_BSS`, `CH_MEM_PRIVATE_BSS(c)` — directly applicable to hypervisor memory partitioning for cache-coherent shared regions.
6. **RT-Thread skip-list timers**: O(log n) timer insertion vs O(n) delta lists. Better for large numbers of virtual timers.
7. **RODOS nanosecond time**: `int64_t` nanoseconds avoids 32-bit wrap issues. Better for hypervisor wall-clock management than tick-based models.

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# RTOS Reference Deep Audit: seL4, ThreadX, NuttX, RTEMS
**Purpose:** Extract architecture abstraction patterns, no-MMU handling, kernel primitives, context switch, and isolation mechanisms to inform UniversalisOS microkernel design.
---
## 1. seL4
### 1.1 Architecture Support
**Architectures:** ARM (32/64), RISC-V (32/64), x86 (32/64)
| seL4 arch | Directory | Sub-variants |
|-----------|-----------|-------------|
| ARM 32 | `src/arch/arm/32/` | armv7-a, armv8-a/32 |
| ARM 64 | `src/arch/arm/64/` | armv8-a/64 (AArch64) |
| RISC-V | `src/arch/riscv/` | riscv32, riscv64 |
| x86 32 | `src/arch/x86/32/` | ia32 |
| x86 64 | `src/arch/x86/64/` | x86_64 |
**Platforms:** allwinnerA20, am335x, apq8064, ariane, bcm2711, bcm2712, bcm2837, cheshire, eswin, exynos4/5, fvp, hifive, hikey, imx6/7/8m/93, maaxboard, odroidc2/c4, omap3, pc99, qemu-arm-virt, qemu-riscv-virt, rk3399, spike, tk1, tx1, tx2, zynqmp, xilinx-versal, zcu102
**Key files:**
- `src/arch/arm/32/traps.S` — ARM32 vector table + trap handlers
- `src/arch/arm/64/traps.S` — AArch64 vector table (EL1/EL2)
- `src/arch/riscv/traps.S` — RISC-V trap entry
- `src/arch/x86/32/traps.S` / `src/arch/x86/64/traps.S` — x86 IDT-based traps
- `libsel4/sel4_arch_include/` — per-arch API headers: aarch32, aarch64, ia32, riscv32, riscv64, x86_64
**Critical observation:** seL4 does NOT support ARMv-M (Cortex-M). It requires an MMU. No MPU-only support.
### 1.2 Memory Model
**MMU-only.** seL4 is a capability-based microkernel that REQUIRES an MMU for its fundamental isolation model.
- `include/kernel/vspace.h` — architecture-abstracted virtual space management
- `src/arch/arm/32/kernel/vspace.c` — ARM32 page table manipulation (L1/L2)
- `src/arch/arm/64/kernel/vspace.c` — AArch64 translation tables
- Capabilities: `cap_page_table_cap`, `cap_page_directory_cap`, `cap_frame_cap` — all MMU-dependent
**How isolation works:** Capability-based access control. Each object (TCB, Endpoint, Page Table, etc.) is accessed only through capabilities held in CNodes. No process can access kernel memory or another process's memory without the appropriate capability. The MMU enforces address space separation between threads in different PDs.
**No-MMU strategy:** None. seL4 fundamentally requires MMU. There is no MPU path.
### 1.3 Kernel Primitives
**Kernel Objects** (`src/object/`):
| Object | File | Purpose |
|--------|------|---------|
| TCB | `tcb.c` | Thread Control Block — the schedulable entity |
| Endpoint | `endpoint.c` | Synchronous IPC rendezvous point |
| Notification | `notification.c` | Async signal / event flag |
| CNode | `cnode.c` | Capability table node |
| Untyped | `untyped.c` | Raw memory for retype into kernel objects |
| Reply | `reply.c` | MCS scheduling reply object |
| SchedContext | `schedcontext.c` | MCS budget/timeslice |
| SchedControl | `schedcontrol.c` | CPU scheduling control |
| Domain | `domain.c` | Scheduling domain (ARINC-like) |
**Scheduling** (`include/kernel/thread.h`):
- Bitmap priority scheduler with L1/L2 bitmaps: `getHighestPrio()` uses `clzl`
- Up to `CONFIG_NUM_PRIORITIES` priority levels
- Domain support: multiple scheduling domains with time-slicing
- MCS kernel: CBS (Constant Bandwidth Server) / sporadic server scheduling
- Key functions: `schedule()`, `chooseThread()`, `switchToThread()`, `switchToIdleThread()`
**IPC** (`src/object/endpoint.c`):
- Synchronous rendezvous: `sendIPC()` / `recvIPC()`
- Message passing via IPC buffer in user space (registers: `msgInfoRegister`, `capRegister`)
- Badge-based capability transfer over endpoints
- Syscall dispatch: `SysSend`, `SysNBSend`, `SysCall`, `SysRecv`, `SysReply`, `SysReplyRecv`, `SysWait`, `SysNBWait`
- Fastpath for `Call`/`ReplyRecv` in `src/fastpath/fastpath.c`
**Synchronization:**
- Notifications: binary event-like primitive (`sendSignal()`, `wait()`, `tryWait()`)
- No mutexes/semaphores — IPC IS the synchronization mechanism
**Memory management:**
- All memory created from Untyped objects via `seL4_Untyped_Retype()`
- Capabilities control access to all objects including page tables and frames
- Kernel does not allocate memory after boot — all created from initial untypeds
### 1.4 API Surface
**Public API** defined in `libsel4/`:
- `include/interfaces/sel4.xml` — formal IDL defining all system calls
- `include/interfaces/object-api.xml` — object method API
**System calls** (from `src/api/syscall.c`):
```c
exception_t handleSyscall(syscall_t syscall);
// SysCall, SysSend, SysNBSend, SysRecv, SysReply, SysReplyRecv, SysWait, SysNBWait
```
**API functions** (from `libsel4/sel4_arch_include/*/sel4/sel4_arch/`):
- `seL4_Untyped_Retype()` — create new kernel objects
- `seL4_TCB_*` — thread control (Configure, SetPriority, SetIPCBuffer, WriteRegisters, ReadRegisters, Suspend, Resume)
- `seL4_Endpoint_Send/Recv/Call()` — synchronous IPC
- `seL4_Signal/Wait()` on Notification objects
- `seL4_CNode_*` — capability space manipulation
- `seL4_VSpace_*` — virtual address space management
- `seL4_IRQControl/Handler_*` — interrupt management
- `seL4_SchedControl_*` — MCS scheduling control
### 1.5 Hardware Abstraction
**Three-layer architecture:**
1. **`arch/`** — architecture-specific code: ARM, RISC-V, x86
2. **`machine/`** — machine-level (common within arch): `registerset.h`, `fpu.c`, `hardware.h`
3. **`plat/`** — platform-specific: per-SoC timer, IRQ controller, serial
**Key HAL interfaces** (`include/arch/machine.h`):
```c
void init_cpu(void);
void init_drivers(void); // platform-level
void ackInterrupt(irq_t irq);
irq_t getActiveIRQ(void);
bool_t isIRQPending(void);
void setNextPC(tcb_t *tcb, word_t v);
word_t getRestartPC(tcb_t *tcb);
void switchToThread(tcb_t *tcb); // architecture-level
void Arch_switchToThread(tcb_t *tcb); // arch-specific (setVMRoot + clearExMonitor)
```
**Register abstraction** (`include/machine/registerset.h` → per-arch):
```c
enum _register { R0, ..., R14, SP=13, LR=14, NextIP=15, CPSR=16, FaultIP=17, TPIDRURW=18, TPIDRURO=19, n_contextRegisters=20 };
```
**Pattern:** `Arch_*()` prefix for architecture-specific functions; `arch_*` directories per arch; `mode/` subdirectories for 32/64-bit variants.
### 1.6 Partition/Isolation Mechanisms
- **Capability-based:** All access mediated by capabilities in CNodes. No global names.
- **Address space isolation:** Each thread can be in a different VSpace (page directory). `setVMRoot()` switches page tables.
- **Scheduling domains:** `CONFIG_NUM_DOMAINS > 1` enables ARINC-653-like temporal partitioning
- **MCS scheduling:** Budget-based isolation prevents starvation/budget-exhaustion attacks
- **No no-MMU path:** seL4 REQUIRES MMU. The capability system IS the isolation mechanism.
### 1.7 Context Switch
**ARM32 context** (`src/arch/arm/32/traps.S`):
```asm
arm_swi_syscall:
srsia #PMODE_SUPERVISOR @ Save CPSR + LR to SVC stack
sub lr, lr, #4 @ FaultIP = NextIP - 4
str lr, [sp, #(PT_FaultIP - PT_NextIP)]
stmdb sp, {r0-lr}^ @ Save all user regs (r0-r14)
mrc p15, 0, sp, c13, c0, 4 @ Load kernel stack from TPIDRPRW
```
**Saved state:** 20 words per thread — R0-R14, NextIP, CPSR, FaultIP, TPIDRURW, TPIDRURO
- FPU state saved lazily (optional `CONFIG_HAVE_FPU`)
- `Arch_switchToThread()`: `setVMRoot(tcb)` + `clearExMonitor()`
- No explicit register save/restore in switch — the trap handler saves everything on entry, the scheduler just swaps the kernel stack pointer
**AArch64 context** (`src/arch/arm/64/traps.S`):
```asm
@ Vector table with 128-byte aligned entries per ARM D1-7
@ Uses TPIDR_EL1/EL2 for kernel stack pointer
@ Saves: X0-X30, SPSR, ELR, TPIDR to kernel stack
```
**Fastpath** (`src/fastpath/fastpath.c`):
```c
void NORETURN fastpath_call(word_t cptr, word_t msgInfo);
void NORETURN fastpath_reply_recv(word_t cptr, word_t msgInfo);
```
Optimized path that avoids full save/restore when only message registers change. Directly switches TCB and address space.
---
## 2. ThreadX (Eclipse ThreadX)
### 2.1 Architecture Support
**Broadest port coverage of any RTOS in the audit.**
**ARM Cortex-A:** cortex_a5, a7, a8, a9, a12, a15, a17, a34, a35, a53, a55, a57, a65, a72, a73, a75, a76, a77, a5x, a65ae, a76ae
**ARM Cortex-R:** cortex_r4, r5, r7
**ARM Cortex-M:** cortex_m0, m23, m3, m4, m7, m33, m55, m85
**ARM legacy:** arm9, arm11
**RISC-V:** risc-v32, risc-v64, risc-v_common
**ARC:** arc_em, arc_hs
**Renesas RX:** rxv1, rxv2, rxv3
**TI DSP:** c667x
**Xtensa:** xtensa
**Linux user-space:** linux (gnu)
**Windows:** win32, win64
**Architecture-grouped ports** (`ports_arch/`):
- ARMv7-A, ARMv7-M, ARMv8-A, ARMv8-M
**Key files per port:**
- `ports/cortex_m0/gnu/src/tx_thread_context_save.S`
- `ports/cortex_m0/gnu/src/tx_thread_context_restore.S`
- `ports/cortex_m0/gnu/src/tx_thread_schedule.S`
- `ports/cortex_m0/gnu/src/tx_thread_system_return.S`
- `ports/cortex_m0/gnu/src/tx_thread_stack_build.S`
- `ports/cortex_m0/gnu/inc/tx_port.h` — port-specific type definitions + inline optimizations
### 2.2 Memory Model
**No MMU/MPU required.** ThreadX runs on flat memory model by default.
- **No-MMU (Cortex-M0/M3/M4):** Single address space, no protection between threads
- **With MPU (Cortex-M33/M85):** Optional MPU support via ThreadX Modules (separate product)
- **With MMU (Cortex-A):** Flat model or optional virtual memory
**Isolation without MMU:** ThreadX provides NONE by default. All threads share the same address space. The `tx_thread_system_state` variable tracks ISR nesting but doesn't protect memory.
**Memory management:**
- `tx_byte_pool` — variable-size memory allocator (malloc-like)
- `tx_block_pool` — fixed-size block allocator (pool-based)
- Both are user-space objects, not kernel-managed pages
### 2.3 Kernel Primitives
**Threads** (`common/src/tx_thread_*.c`):
- `tx_thread_create()`, `tx_thread_delete()`, `tx_thread_suspend()`, `tx_thread_resume()`
- Priority-based preemptive scheduling (0 = highest, up to `TX_MAX_PRIORITIES` = 32-1024)
- Round-robin time-slicing within same priority
- Preemption-threshold: disable preemption for priorities below threshold
**Synchronization:**
- `tx_mutex_create/get/put/delete` — mutex with priority inheritance
- `tx_semaphore_create/get/put/delete` — counting semaphore
- `tx_event_flags_create/get/set/delete` — event flags (AND/OR)
**Communication:**
- `tx_queue_create/send/receive/delete` — fixed-size message queues
- No IPC/message passing between address spaces (single address space)
**Timers:**
- `tx_timer_create/activate/deactivate/delete` — software timers
- Tick-based: `tx_timer_interrupt` increments system tick
**Memory:**
- `tx_byte_pool_create/allocate/release/delete` — dynamic memory pools
- `tx_block_pool_create/allocate/release/delete` — fixed-block pools
### 2.4 API Surface
**Header:** `common/inc/tx_api.h` — single monolithic API header
**Function naming:** All public functions prefixed `tx_`:
```c
UINT tx_thread_create(TX_THREAD *thread_ptr, CHAR *name_ptr, VOID (*entry)(ULONG), ULONG entry_input,
VOID *stack_start, ULONG stack_size, UINT priority, UINT preempt_threshold,
ULONG time_slice, UINT auto_start);
UINT tx_thread_delete(TX_THREAD *thread_ptr);
UINT tx_thread_suspend(TX_THREAD *thread_ptr);
UINT tx_thread_resume(TX_THREAD *thread_ptr);
UINT tx_thread_relinquish(void);
UINT tx_thread_sleep(ULONG timer_ticks);
UINT tx_mutex_create(TX_MUTEX *mutex_ptr, CHAR *name_ptr, UINT inherit);
UINT tx_mutex_get(TX_MUTEX *mutex_ptr, ULONG wait_option);
UINT tx_mutex_put(TX_MUTEX *mutex_ptr);
UINT tx_semaphore_create(TX_SEMAPHORE *sem_ptr, CHAR *name_ptr, ULONG initial_count);
UINT tx_semaphore_get(TX_SEMAPHORE *sem_ptr, ULONG wait_option);
UINT tx_semaphore_put(TX_SEMAPHORE *sem_ptr);
UINT tx_queue_create(TX_QUEUE *queue_ptr, CHAR *name_ptr, UINT message_size, VOID *queue_start, ULONG queue_size);
UINT tx_queue_send(TX_QUEUE *queue_ptr, VOID *source_ptr, ULONG wait_option);
UINT tx_queue_receive(TX_QUEUE *queue_ptr, VOID *destination_ptr, ULONG wait_option);
```
**Error-checked variants:** `_txe_*` prefix (with parameter validation)
**MISRA variants:** `_txr_*` prefix
### 2.5 Hardware Abstraction
**Port-based abstraction:** Each target gets a complete port directory:
```
ports/<cpu>/<compiler>/
inc/tx_port.h — type definitions, macros, inline optimizations
src/
tx_thread_context_save.S
tx_thread_context_restore.S
tx_thread_schedule.S
tx_thread_system_return.S
tx_thread_stack_build.S
tx_thread_interrupt_control.S
tx_thread_interrupt_disable.S
tx_thread_interrupt_restore.S
tx_timer_interrupt.S
```
**`tx_port.h` pattern** (Cortex-M0 example):
```c
#define TX_INT_DISABLE 1
#define TX_INT_ENABLE 0
#define TX_MINIMUM_STACK 200
// Inline interrupt control:
static inline unsigned int __disable_interrupts(void) { ... MRS PRIMASK; CPSID i ... }
static inline void __restore_interrupts(unsigned int primask_value) { ... MSR PRIMASK ... }
// Inline system return (PendSV-based):
static inline void _tx_thread_system_return_inline(void) {
*((volatile ULONG *) 0xE000ED04) = ((ULONG) 0x10000000); // Set PendSV
// DSB + ISB
}
#define TX_DISABLE interrupt_save = __disable_interrupts();
#define TX_RESTORE __restore_interrupts(interrupt_save);
```
**Key pattern:** The C kernel code (`common/src/`) is 100% portable. All arch-specific behavior is in the port `.S` files and `tx_port.h`. The common code calls `_tx_thread_context_save()`, `_tx_thread_schedule()`, `_tx_thread_system_return()` which are entirely implemented in the port assembly.
### 2.6 Partition/Isolation Mechanisms
**None in base ThreadX.** Single flat address space, no protection.
**ThreadX Modules** (`ports_module/`): Optional module that provides memory-isolated modules using MPU/MMU when available. This is a separate add-on, not part of core ThreadX.
### 2.7 Context Switch
**Cortex-M0** (`ports/cortex_m0/gnu/src/tx_thread_schedule.S`):
```asm
_tx_thread_schedule:
MOVS r0, #0
LDR r2, =_tx_thread_preempt_disable
STR r0, [r2, #0] @ Clear preempt disable
CPSIE i @ Enable interrupts
LDR r0, =#0x10000000 @ PENDSVSET bit
LDR r1, =#0xE000ED04 @ NVIC ICSR
STR r0, [r1] @ Trigger PendSV
...PendSV handler does the actual switch...
```
**Cortex-M PendSV context switch** (in `tx_thread_context_restore.S`):
```asm
_tx_thread_context_restore:
@ PendSV handler - hardware saves R0-R3, R12, LR, PC, xPSR automatically
@ Save remaining: R4-R11, optionally S16-S31 (FPU)
@ Load new thread's R4-R11 from its stack
@ Hardware restores R0-R3, R12, LR, PC, xPSR on exception return
```
**Cortex-A** (`ports/cortex_a9/gnu/src/tx_thread_context_save.S`):
```asm
@ Saves R0-R12, LR, CPSR, SPSR to thread's stack
@ IRQ/FIQ nesting support: tx_thread_irq_nesting_start/end
```
**Cortex-A scheduler** (`tx_thread_schedule.S`):
```asm
@ Load _tx_thread_execute_ptr, compare with current
@ If different: save full context (R0-R12, SP, LR, CPSR) to old TCB stack
@ restore from new TCB stack
@ Handle FPU context (VFP D0-D31, FPEXC, FPSCR)
```
**Stack building** (`tx_thread_stack_build.S`):
```asm
@ Builds initial stack frame for new thread:
@ Pushes: CPSR, PC (entry), LR (thread shell), R12, R3-R0 (entry_input)
@ Sets SP to top of stack
```
---
## 3. NuttX
### 3.1 Architecture Support
**Most architectures of any RTOS in the audit.** NuttX is a POSIX-like RTOS.
**Architectures** (`arch/`):
| Arch | Directory | Sub-variants |
|------|-----------|-------------|
| ARM | `arch/arm/` | arm, armv6-m, armv7-a, armv7-m, armv7-r, armv8-m, armv8-r |
| ARM64 | `arch/arm64/` | AArch64 |
| AVR | `arch/avr/` | ATmega |
| CEVA | `arch/ceva/` | DSP |
| HC | `arch/hc/` | HCS12 |
| MIPS | `arch/mips/` | PIC32, MIPS32 |
| MISC | `arch/misoc/` | MiSoC |
| OpenRISC | `arch/or1k/` | or1k |
| Renesas | `arch/renesas/` | SH-1, M16C, RX |
| RISC-V | `arch/risc-v/` | RV32, RV64 |
| Simulator | `arch/sim/` | Linux/macOS user-space |
| SPARC | `arch/sparc/` | LEON |
| TriCore | `arch/tricore/` | Infineon |
| x86 | `arch/x86/` | i486, QEMU |
| x86_64 | `arch/x86_64/` | Intel |
| Xtensa | `arch/xtensa/` | ESP32 |
| Z16 | `arch/z16/` | Zilog |
| Z80 | `arch/z80/` | Z80, eZ80, Z180 |
**ARM sub-architectures in `arch/arm/src/`:**
- armv6-m (Cortex-M0/M0+)
- armv7-a (Cortex-A5/A7/A8/A9/A53 with MMU)
- armv7-m (Cortex-M3/M4/M7 — no MMU, optional MPU)
- armv7-r (Cortex-R4/R5/R7 — MPU)
- armv8-m (Cortex-M23/M33/M55/M85 — TrustZone-M + MPU)
- armv8-r (Cortex-R52/R82)
**Board support:** Hundreds of BSPs under `boards/` — STM32, NRF52, RP2040, ESP32, SAM, i.MX, Kinetis, etc.
### 3.2 Memory Model
**Adaptive — supports no-MMU, MPU, and MMU.**
**No-MMU (Cortex-M, most MCUs):**
- Flat address space, all tasks in single memory map
- `CONFIG_ARCH_NO_INTERRUPT_STACK` — uses thread stack for ISR
- Protection: stack canary checking (`CONFIG_STACK_CANARIES`)
- No memory isolation between tasks
**MPU (Cortex-M with MPU, Cortex-R):**
- `CONFIG_ARCH_USE_MPU` — enables MPU support
- `CONFIG_BUILD_PROTECTED` — kernel/user separation using MPU
- Kernel runs privileged, user runs unprivileged
- `syscall/` directory: system call table (`syscall.csv`) with auto-generated proxies/stubs
- `arch/arm/src/armv7-m/arm_dispatch_syscall.S` — SVC-based syscall entry
- `CONFIG_MM_KERNEL_HEAP` — separate kernel heap
**MMU (Cortex-A, x86, etc.):**
- `CONFIG_BUILD_KERNEL` — full virtual memory isolation
- `arch/arm/src/armv7-a/` — full MMU page table management
- `sched/addrenv/` — address environment management
- `mm/kmap/` — kernel memory mapping
**Memory management (`mm/`):**
- `mm_heap/` — general heap allocator
- `mm/tlsf/` — TLSF (Two-Level Segregated Fit) allocator
- `mm/mempool/` — fixed-size memory pool
- `mm/mm_gran/` — granule allocator (for DMA, etc.)
- `mm/umm_heap/` — user memory heap
- `mm/kmm_heap/` — kernel memory heap
- `mm/shm/` — shared memory
### 3.3 Kernel Primitives
**Tasks** (`sched/task/`):
- `task_create()`, `task_spawn()`, `task_delete()`, `task_exit()`
- POSIX-like: `nxtask_create()` internal, `task_create()` public
- Priority-based preemptive scheduling (FIFO, Round-Robin, Sporadic)
**Pthreads** (`sched/pthread/`):
- Full POSIX threads: `pthread_create()`, `pthread_join()`, `pthread_detach()`
- `pthread_mutex_*`, `pthread_cond_*`, `pthread_rwlock_*`
- `pthread_attr_*` — full attribute support
**Semaphores** (`sched/semaphore/`):
- `nxsem_wait()`, `nxsem_post()`, `nxsem_trywait()`
- Binary and counting semaphores
**Message queues** (`sched/mqueue/`):
- POSIX mqueue: `mq_open()`, `mq_send()`, `mq_receive()`
**Signals** (`sched/signal/`):
- Full POSIX signals: `kill()`, `sigaction()`, `sigwait()`, `pthread_sigmask()`
**Events** (`sched/event/`):
- NuttX-specific event flags
**Scheduling** (`sched/sched/`):
- `sched_addreadytorun()` — core scheduling logic
- `nxsched_process_timer()` — tick processing
- SMP support: per-CPU ready queues
- `CONFIG_SCHED_INSTRUMENTATION` — trace hooks
### 3.4 API Surface
**POSIX-compliant API.** The public API IS POSIX:
```c
// Task management
int task_create(const char *name, int priority, int stack_size, main_t entry, char *const argv[]);
int task_delete(pid_t pid);
int task_setpriority(pid_t pid, int sched_priority);
// POSIX threads
int pthread_create(pthread_t *thread, const pthread_attr_t *attr, pthread_startroutine_t start_routine, void *arg);
int pthread_join(pthread_t thread, void **value_ptr);
int pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *attr);
int pthread_mutex_lock(pthread_mutex_t *mutex);
// Semaphores
int sem_init(sem_t *sem, int pshared, unsigned int value);
int sem_wait(sem_t *sem);
int sem_post(sem_t *sem);
// POSIX I/O
int open(const char *path, int oflags, ...);
ssize_t read(int fd, void *buf, size_t nbytes);
ssize_t write(int fd, const void *buf, size_t nbytes);
// Sockets
int socket(int domain, int type, int protocol);
int bind(int sockfd, const struct sockaddr *addr, socklen_t addrlen);
```
**System call table** (`syscall/syscall.csv`):
```
"task_create","nuttx/task.h","","int","FAR const char *","int","int","main_t","FAR char * const *"
"task_delete","unistd.h","","int","pid_t"
"pthread_create","pthread.h","","int","FAR pthread_t *","FAR const pthread_attr_t *","FAR pthread_startroutine_t","FAR void *"
```
**Auto-generated syscall mechanism:** The CSV file drives code generation for:
- User-space proxies (in `syscall/proxies/`)
- Kernel-space stubs (in `syscall/stubs/`)
- SVC/SWI dispatch (in `arch/*/arm_dispatch_syscall.S`)
### 3.5 Hardware Abstraction
**Three-layer architecture:**
1. **`arch/<arch>/`** — architecture-level
- `src/common/` — shared across sub-architectures (e.g., `arm_dataabort.c`, `arm_vectors.S`)
- `src/<subarch>/` — sub-architecture (e.g., `armv7-m/`, `armv7-a/`)
- `src/<chip>/` — chip-specific (e.g., `stm32/`, `nrf52/`)
- `include/` — headers per chip/subarch
2. **`boards/<arch>/<chip>/<board>/`** — board-level configuration and drivers
3. **`drivers/`** — portable device drivers (serial, SPI, I2C, GPIO, etc.)
**Key HAL functions** (`include/nuttx/arch.h`):
```c
void up_initialize(void); // Architecture init
int up_saveusercontext(void *saveregs); // Save CPU context
void up_initial_state(struct tcb_s *tcb); // Initialize new task context
void up_switch_context(struct tcb_s *tcb, struct tcb_s *rtcb); // Context switch
void up_irqinitialize(void); // IRQ controller init
int up_enable_irq(int irq); // Enable interrupt
int up_disable_irq(int irq); // Disable interrupt
```
**IRQ abstraction** (`include/nuttx/irq.h`):
```c
int irq_attach(int irq, xcpt_t isr, xcpt_t isrthread, FAR void *arg, FAR const char *name);
// Supports: ISR handlers, threaded IRQ handlers, work-queue-based IRQ handlers
```
**Architecture-specific context** (ARM, `arch/arm/include/armv7-m/irq.h`):
```c
struct xcptcontext {
uint32_t regs[XCPTCONTEXT_REGS]; // R0-R15, xPSR, BASEPRI, EXC_RETURN
// FPU: S0-S31, FPSCR
// Signal context overlay
};
```
### 3.6 Partition/Isolation Mechanisms
**`CONFIG_BUILD_PROTECTED`** — NuttX's primary no-MMU isolation mechanism:
- Kernel runs in privileged mode (Handler mode or privileged Thread mode)
- User tasks run unprivileged (Thread mode, PSP stack)
- System calls via SVC instruction
- MPU regions protect kernel memory from user access
- Separate kernel/user heaps
**`CONFIG_BUILD_KERNEL`** — Full MMU isolation:
- Per-process address spaces
- `sched/addrenv/` — address environment switching on context switch
- `mm/kmap/` — kernel virtual memory management
**Key files:**
- `arch/arm/src/armv7-m/arm_dispatch_syscall.S` — SVC handler for protected mode
- `syscall/` — auto-generated syscall proxy/stub pairs
- `mm/umm_heap/` vs `mm/kmm_heap/` — separate user/kernel heaps
### 3.7 Context Switch
**ARMv7-M context save** (`arch/arm/src/armv7-m/arm_saveusercontext.S`):
```asm
up_saveusercontext:
str r0, [r0, #(4*REG_R0)] @ Save R0-R3, R12, R14, R15
str r1, [r0, #(4*REG_R1)]
...
mrs r1, XPSR
str r1, [r0, #(4*REG_XPSR)]
@ FPU: vstmia r1!, {s0-s15}; vmrs fpscr
mov r2, sp
mrs r3, basepri
stmia r0!, {r2-r11} @ SP, BASEPRI, R4-R11
mov r1, #-1
stmia r0!, {r1} @ EXC_RETURN = 0xffffffff
@ FPU: vstmia r0!, {s16-s31}
```
**ARMv7-M exception entry** (`arch/arm/src/armv7-m/arm_exception.S`):
```asm
exception_common:
mrs r0, ipsr @ IRQ number
mrs r12, control
tst r14, #EXC_RETURN_PROCESS_STACK @ PSP or MSP?
beq 1f
mrs r1, psp @ Context on PSP
b 2f
1: mrs r1, msp @ Context on MSP
sub r2, r1, #SW_XCPT_SIZE
msr msp, r2
2: @ Complete save: R2-R12, R14, BASEPRI, SP
@ FPU: vstmdbeq r1!, {s16-s31}
stmdb r1!, {r2-r12,r14}
@ Call arm_doirq(irq_number, saved_context)
```
**Context switch:** On Cortex-M, NuttX uses the hardware PendSV mechanism:
- `up_switch_context()` triggers PendSV
- PendSV handler saves R4-R11 (hardware saves R0-R3, R12, LR, PC, xPSR)
- Loads new thread's registers
- Hardware restores on exception return
---
## 4. RTEMS
### 4.1 Architecture Support
**14 CPU architectures** (`cpukit/score/cpu/`):
| Architecture | Directory | BSP Variants |
|-------------|-----------|-------------|
| AArch64 | `score/cpu/aarch64/` | a53, a72, raspberrypi5, rk3399, xilinx-zynqmp, xen, frdm-imx93, xilinx-versal |
| ARM | `score/cpu/arm/` | beagle, stm32f4/h7/u5, atsam, lpc, imx, imxrt, raspberrypi, tms570, xen, fvp, efm32, lpc176x |
| i386 | `score/cpu/i386/` | pc386, pc486 |
| x86_64 | `score/cpu/x86_64/` | amd64 |
| M68k | `score/cpu/m68k/` | mcf5206, mcf52235, mcf5225x, mcf5329, mrm332 |
| MicroBlaze | `score/cpu/microblaze/` | Xilinx |
| MIPS | `score/cpu/mips/` | Malta, JMR3904, RBtx4938 |
| Moxie | `score/cpu/moxie/` | moxiesim |
| Nios II | `score/cpu/nios2/` | Altera |
| OpenRISC 1000 | `score/cpu/or1k/` | or1ksim |
| PowerPC | `score/cpu/powerpc/` | MPC5xx, MPC8xx, MPC8260, MPC83xx, MPC85xx, QorIQ, mvme3100, beatnik |
| RISC-V | `score/cpu/riscv/` | rv32/rv64, generic, spike, frdm-k28f |
| SPARC | `score/cpu/sparc/` | ERC32, LEON2, LEON3, LEON4 |
| no_cpu | `score/cpu/no_cpu/` | Template/porting guide |
### 4.2 Memory Model
**Adaptive — supports no-MMU, MPU, and MMU.**
**No-MMU (ARM Cortex-M, SPARC ERC32):**
- Flat address space
- Stack-based protection (stack bounds checking via guard patterns)
**MPU (ARMv7-M/R):**
- `score/cpu/arm/include/rtems/score/armv7-pmsa.h` — full PMSAv7 MPU support
- Region-based protection with `_ARMV7_PMSA_Write_region()`, `_ARMV7_PMSA_Add_regions()`
- Supports up to 16 MPU regions (or more with sub-region disable)
- Access control: read-only/read-write, cached/uncached, shared/non-shared
**MMU (AArch64, PowerPC, x86_64):**
- Full virtual memory support via BSP-specific MMU drivers
- `score/cpu/aarch64/` — EL1 page table management
**Memory management:**
- Workspace allocator (kernel heap) — configured at link time
- `cpukit/libcsupport/src/` — POSIX malloc/free
- `cpukit/libblock/` — block device cache
### 4.3 Kernel Primitives
**Classic RTEMS API** (`cpukit/include/rtems/rtems/`):
| Manager | Header | Functions |
|---------|--------|-----------|
| Tasks | `tasks.h` | `rtems_task_create/delete/start/restart/suspend/resume/wake_when/set_priority` |
| Semaphores | `sem.h` | `rtems_semaphore_create/delete/obtain/release/release_count` |
| Message Queues | `message.h` | `rtems_message_queue_create/delete/send/receive/broadcast/urgent` |
| Events | `event.h` | `rtems_event_send/receive` |
| Barriers | `barrier.h` | `rtems_barrier_create/delete/wait/release` |
| Partitions | `part.h` | `rtems_partition_create/delete/get/release` |
| Regions | `region.h` | `rtems_region_create/delete/get/return_segment` |
| Timers | `timer.h` | `rtems_timer_create/delete/server_fire_when/fire_after/reset/cancel` |
| Rate Monotonic | `ratemon.h` | `rtems_rate_monotonic/create/delete/period/cancel/get_status` |
| Dual-Port Memory | `dpmem.h` | `rtems_port_create/delete/external2internal/internal2external` |
| Signals | `signal.h` | `rtems_signal_send/catch` |
| Clock | `clock.h` | `rtems_clock_set/get/get_tod/get_seconds_since_epoch/tick` |
**POSIX API** (via `cpukit/posix/`):
- Full POSIX threads, mutexes, condition variables, semaphores, mqueues, timers
**Super Core (score)** (`cpukit/score/src/`):
- `corebarrier.c`, `coremsg.c`, `coremutexseize.c`, `coresem.c` — internal implementations
- `thread*.c` — thread management
- `scheduler*.c` — pluggable scheduler framework
- `smp.c` — SMP management
### 4.4 API Surface
**Classic RTEMS API:**
```c
rtems_task_create(name, initial_priority, stack_size, modes, attributes, &id);
rtems_task_start(id, entry_point, argument);
rtems_task_suspend(id);
rtems_task_resume(id);
rtems_semaphore_create(name, count, attributes, priority, &id);
rtems_semaphore_obtain(id, options, timeout);
rtems_semaphore_release(id);
rtems_message_queue_create(name, count, max_size, attributes, &id);
rtems_message_queue_send(id, buffer, size);
rtems_message_queue_receive(id, buffer, &size, options, timeout);
rtems_event_send(task_id, event_in);
rtems_event_receive(event_in, options, ticks, &event_out);
```
**POSIX API:**
```c
int pthread_create(pthread_t *thread, const pthread_attr_t *attr, void *(*start_routine)(void *), void *arg);
int sem_init(sem_t *sem, int pshared, unsigned int value);
int mq_send(mqd_t mqdes, const char *msg_ptr, size_t msg_len, unsigned msg_prio);
```
### 4.5 Hardware Abstraction
**Score CPU layer** (`cpukit/score/cpu/<arch>/`):
```
include/rtems/score/cpu.h — CPU-level type definitions, macros, inline functions
include/rtems/score/cpuimpl.h — implementation details
include/rtems/score/cpu_asm.h — assembly prototypes
```
**Key CPU interface** (from `cpu.h`):
```c
#define CPU_STACK_MINIMUM_SIZE (1024 * 4)
#define CPU_SIZEOF_POINTER 4
#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED(32)
void _CPU_Context_switch(Context_Control *run, Context_Control *heir);
void _CPU_Context_restore(Context_Control *new_context);
void _CPU_Context_Initialize(Context_Control *context, void *stack_area_begin,
size_t stack_area_size, uint32_t new_level,
void (*entry_point)(void), bool is_fp, void *tls_area);
```
**BSP layer** (`bsps/<arch>/<bsp>/`):
```
include/bsp.h — BSP configuration
start/ — startup code
console/ — UART driver
clock/ — timer driver
irq/ — interrupt controller
```
**Pattern:** CPU layer provides `_CPU_*()` functions. BSP provides `_BSP_*()` functions. The score (super core) is arch-independent and calls only `_CPU_*()` and `_BSP_*()`.
### 4.6 Partition/Isolation Mechanisms
**MPU-based protection:**
- `score/cpu/arm/include/rtems/score/armv7-pmsa.h` — comprehensive MPU management
- `_ARMV7_PMSA_Write_region()` — write MPU region (base, size, attributes, sub-region disable)
- `_ARMV7_PMSA_Add_regions()` — add memory region to MPU (handles power-of-2 alignment)
- `_ARMV7_PMSA_Find_region()` — search for region containing address
- `_ARMV7_PMSA_Find_available_region()` — find free MPU slot
- Supports data and instruction regions separately (DRBAR/IRBAR)
- Region attributes: cached/uncached, read-only/read-write, shareable, device
**ARINC 653 partitioning:**
- RTEMS has an ARINC 653 API layer for safety-critical partitioning
- Rate Monotonic scheduling provides temporal isolation
### 4.7 Context Switch
**ARMv7-M context switch** (`score/cpu/arm/armv7m-context-switch.c`):
```c
void __attribute__((naked)) _CPU_Context_switch(
Context_Control *executing,
Context_Control *heir
) {
__asm__ volatile (
"movw r2, #:lower16:_Per_CPU_Information\n"
"movt r2, #:upper16:_Per_CPU_Information\n"
"ldr r3, [r2, %[isrpcpuoff]]\n"
"stm r0, {r4-r11, lr}\n" // Save callee-saved regs
#ifdef ARM_MULTILIB_VFP
"add r4, r0, %[d8off]\n"
"vstm r4, {d8-d15}\n" // Save FPU D8-D15
#endif
"str sp, [r0, %[spctxoff]]\n" // Save SP
"str r3, [r0, %[isrctxoff]]\n" // Save ISR nest level
"ldr r3, [r1, %[isrctxoff]]\n" // Load new ISR nest level
"ldr sp, [r1, %[spctxoff]]\n" // Load new SP
#ifdef ARM_MULTILIB_VFP
"add r4, r1, %[d8off]\n"
"vldm r4, {d8-d15}\n" // Restore FPU D8-D15
#endif
"ldm r1, {r4-r11, lr}\n" // Restore callee-saved regs
"str r3, [r2, %[isrpcpuoff]]\n"// Store ISR nest level
"bx lr\n"
);
}
```
**`Context_Control` structure** (ARM, from `cpu.h`):
```c
typedef struct {
uint32_t register_r4;
uint32_t register_r5;
uint32_t register_r6;
uint32_t register_r7;
uint32_t register_r8;
uint32_t register_r9;
uint32_t register_r10;
uint32_t register_r11;
uint32_t register_lr;
uint32_t register_sp;
uint32_t isr_nest_level;
uint32_t thread_id; // TLS
#ifdef ARM_MULTILIB_VFP
uint64_t register_d8;
...
uint64_t register_d15;
#endif
} Context_Control;
```
**Key pattern:** RTEMS uses `naked` functions with inline assembly, directly manipulating the SP. Unlike ThreadX (which uses PendSV on Cortex-M), RTEMS performs the context switch in the calling function itself. The `isr_nest_level` is stored per-context to handle nested interrupts correctly.
---
## 5. Cross-RTOS Comparison Matrix
| Feature | seL4 | ThreadX | NuttX | RTEMS |
|---------|------|---------|-------|-------|
| **Arch count** | 3 (ARM, RISC-V, x86) | 10+ (ARM-M/A/R, RISC-V, ARC, RX, Xtensa, Win, Linux) | 18 (ARM, AVR, MIPS, RISC-V, x86, SPARC, Z80...) | 14 (ARM, AArch64, x86, PPC, MIPS, SPARC, M68k, RISC-V...) |
| **Cortex-M support** | NO | YES (M0 to M85) | YES (M0 to M85) | YES (M3/M4/M7/M33) |
| **No-MMU support** | NO | YES (flat) | YES (flat + MPU + protected) | YES (flat + MPU) |
| **MPU support** | NO | Modules (optional) | CONFIG_BUILD_PROTECTED | armv7-pmsa.h |
| **MMU support** | REQUIRED | Optional | CONFIG_BUILD_KERNEL | Per-arch |
| **API style** | Capability IPC | tx_*() proprietary | POSIX | Classic RTEMS + POSIX |
| **Scheduling** | Priority bitmap + MCS | Priority + preemption-threshold | Priority FIFO/RR/Sporadic | Pluggable scheduler |
| **IPC** | Synchronous endpoints | Message queues | POSIX mqueue/signals | Message queues/events |
| **Context switch** | Trap handler saves all | PendSV (Cortex-M) / IRQ | PendSV (Cortex-M) / IRQ | Direct (naked function) |
| **Isolation model** | Capabilities | None (flat) | MPU protected / MMU | MPU regions |
| **Naming convention** | `seL4_*` | `tx_*` / `_tx_*` | POSIX (`task_create`, etc.) | `rtems_*` |
## 6. Design Patterns for UniversalisOS
### 6.1 Architecture Abstraction Pattern
**Best model: NuttX's 3-layer + RTEMS's CPU interface**
```
include/uos_arch.h — arch-independent interface (like RTEMS score/cpu.h)
arch/<arch>/include/ — arch-specific type definitions
arch/<arch>/src/<subarch>/ — sub-arch implementation (like NuttX)
arch/<arch>/src/<chip>/ — chip-specific (like NuttX)
```
**Key functions to abstract:**
```c
void uos_context_switch(uos_context_t *from, uos_context_t *to); // RTEMS pattern
void uos_context_save(uos_context_t *ctx); // ThreadX pattern
void uos_context_restore(uos_context_t *ctx); // ThreadX pattern
void uos_context_init(uos_context_t *ctx, void *sp, void *entry); // RTEMS pattern
void uos_irq_disable(void); // ThreadX inline pattern
void uos_irq_enable(void);
```
### 6.2 No-MMU Strategy
**Layer 1 (always):** Flat memory, stack canaries, cooperative/idle-hooks (ThreadX baseline)
**Layer 2 (MPU available):** Kernel/user separation via MPU (NuttX CONFIG_BUILD_PROTECTED pattern)
**Layer 3 (MMU available):** Full process isolation (seL4 capability pattern)
**MPU abstraction** should follow RTEMS `armv7-pmsa.h` pattern:
```c
void uos_mpu_write_region(uint32_t index, uintptr_t base, size_t size, uint32_t attrs);
void uos_mpu_enable(void);
void uos_mpu_disable(void);
uint32_t uos_mpu_find_region(uintptr_t addr, uint32_t start);
```
### 6.3 Context Switch Pattern
**For Cortex-M (no MMU, PendSV):** Use ThreadX/NuttX PendSV pattern — hardware saves half the context automatically.
**For Cortex-A/R (MMU/MPU, IRQ):** Use seL4/NuttX trap handler pattern — save all registers on kernel stack, switch stack pointer + page tables.
**For RISC-V (all modes):** Follow seL4's `src/arch/riscv/traps.S` pattern — save all CSRs + registers.
**Minimal context (Cortex-M):** ~68 bytes (17 words) — R4-R11, SP, LR, PC, xPSR, BASEPRI, EXC_RETURN + optional FPU (132 bytes for S0-S31+FPSCR)
**Full context (Cortex-A):** ~72 bytes (18 words) + FPU (256 bytes for D0-D31) + VFP regs
### 6.4 Kernel Primitive Naming Convention
Based on the audit, the `uos_*` naming should follow this pattern:
```c
// Tasks/Threads
uos_task_create(), uos_task_delete(), uos_task_suspend(), uos_task_resume()
uos_thread_create() (for pthread-like)
// Scheduling
uos_sched_yield(), uos_sched_set_priority()
// Synchronization
uos_sem_create(), uos_sem_wait(), uos_sem_post()
uos_mutex_create(), uos_mutex_lock(), uos_mutex_unlock()
uos_event_create(), uos_event_wait(), uos_event_set()
// IPC
uos_mq_create(), uos_mq_send(), uos_mq_receive()
uos_endpoint_send(), uos_endpoint_recv() // seL4-style synchronous
// Memory
uos_mem_alloc(), uos_mem_free()
uos_mpu_set_region(), uos_mpu_enable()
// Context
uos_context_switch(), uos_context_init()
```
### 6.5 Guest RTOS Personality Layer
To host FreeRTOS, ThreadX, Zephyr, Mbed as guests, create thin wrappers:
```c
// FreeRTOS personality: wraps uos_task_create -> xTaskCreate
// ThreadX personality: wraps uos_task_create -> tx_thread_create
// Each personality provides the exact API the guest expects
// All call uos_* primitives underneath
```
---
*Generated from deep audit of `/home/fabiorafaelcoutada/portugalfuturista/rtos_ref/{seL4,threadx,nuttx,rtems}/`*