# UniversalisOS Microkernel — Complete Architecture Target List

**Date:** 2026-07-14
**Status:** ACTIVE — Expanded target matrix

---

## The Complete Vision

UniversalisOS runs on **everything that computes**. From an 8051 with 256 bytes of RAM to a Xeon with 512GB. Every chip, every era, every vendor.

```
┌─────────────────────────────────────────────────────────────────────────┐
│                     UniversalisOS Microkernel                           │
│                  "If it has a clock, we run on it"                      │
├─────────────────────────────────────────────────────────────────────────┤
│  8-bit           16-bit          32-bit           64-bit                │
│  AVR/8051/PIC    RL78/TriCore    Cortex-M/A/R     AArch64/x86_64       │
│  Z80/HC11        MSP430/RX       RISC-V32         RISC-V64             │
│                  Renesas V850    Xtensa            Pentium+ (32→64)     │
├─────────────────────────────────────────────────────────────────────────┤
│  Tier 0: No MPU/MMU (cooperative)                                       │
│  Tier 1: MPU-based (preemptive isolation)                               │
│  Tier 2: MMU-based (full type-1 hypervisor)                             │
│  Tier 3: Hardware virtualization (VT-x/VE/H-ext)                        │
└─────────────────────────────────────────────────────────────────────────┘
```

---

## COMPLETE ARCHITECTURE TARGETS

### ARM Cortex-M (ARMv6-M / ARMv7-M / ARMv8-M)

| Core | Arch | Tier | MPU | TrustZone | Chips | Port Priority |
|------|------|------|-----|-----------|-------|--------------|
| **Cortex-M0** | ARMv6-M | 0 | No | No | STM32F0, nRF51, SAMD21, LPC11xx | P0 |
| **Cortex-M0+** | ARMv6-M | 0 | Optional | No | STM32G0, SAMD21, KL27, LPC8xx | P0 |
| **Cortex-M1** | ARMv6-M | 0 | No | No | Xilinx FPGA soft-core (Cyclone, Artix) | P2 |
| **Cortex-M3** | ARMv7-M | 1 | Yes (8 regions) | No | STM32F1, LPC1768, EFM32, MAX32660 | P0 |
| **Cortex-M4** | ARMv7E-M | 1 | Yes (8 regions) | No | STM32F4, nRF52, K66, SAM4S, TM4C | P0 |
| **Cortex-M7** | ARMv7E-M | 1 | Yes (16 regions) | No | STM32F7, STM32H7, i.MX RT1060, SAMV71 | P1 |
| **Cortex-M23** | ARMv8-M | 1 | Yes (8 regions) | Optional | SAMD21, STM32L5, MAX32655 | P1 |
| **Cortex-M33** | ARMv8-M | 1 | Yes (8 regions) | Yes | STM32L5, STM32U5, nRF5340, LPC55S69, RA4M1 | P0 |
| **Cortex-M35P** | ARMv8-M | 1 | Yes (8 regions) | Yes + tamper | STM32L5 (secure) | P2 |
| **Cortex-M55** | ARMv8.1-M | 1 | Yes (16 regions) | Yes + MVE | STM32U5, Alif E7 | P1 |
| **Cortex-M85** | ARMv8.1-M | 1 | Yes (16 regions) | Yes + MVE + PAC | RA8M1, RA8D1 | P2 |

**Key ARMv8-M features we must support:**
- **TrustZone-M**: Secure/Non-secure partition at hardware level. SAU (Security Attribution Unit) + IDAU (Implementation Defined Attribution Unit). Each task runs in Secure or Non-secure world.
- **MPU enhancements**: 8/16 regions with per-region size, type (Normal/Device/Code), and shareability
- **MVE (M-Profile Vector Extension)**: Helium SIMD for Cortex-M55/M85
- **PAC (Pointer Authentication)**: Return address signing on M85
- **Stack limit registers**: Hardware stack overflow detection (ARMv8-M)

### ARM Cortex-A (ARMv7-A / ARMv8-A)

| Core | Arch | Tier | VE | Chips | Port Priority |
|------|------|------|----|----|------|
| **Cortex-A5** | ARMv7-A | 2 | No | SAM9X60, VF610 | P2 |
| **Cortex-A7** | ARMv7-A | 2 | No | Allwinner A20, i.MX6ULL, STM32MP1 | P1 |
| **Cortex-A8** | ARMv7-A | 2 | No | AM335x (BeagleBone), OMAP3530 | P2 |
| **Cortex-A9** | ARMv7-A | 2 | No | i.MX6Q, Zynq-7000, OMAP4 | P2 |
| **Cortex-A15** | ARMv7-A | 2 | Yes | Exynos 5250, OMAP5, Keystone 2 | P1 |
| **Cortex-A35** | ARMv8-A | 2/3 | Yes | i.MX8ULP | P2 |
| **Cortex-A53** | ARMv8-A | 2/3 | Yes | RPi 3, i.MX8M, Allwinner A64, STM32MP2 | P0 |
| **Cortex-A55** | ARMv8.2-A | 2/3 | Yes | DynamIQ little core | P1 |
| **Cortex-A72** | ARMv8-A | 3 | Yes | RPi 4, RK3399, Layerscape | P1 |
| **Cortex-A76** | ARMv8.2-A | 3 | Yes | RPi 5 (BCM2712), RK3588 | P1 |
| **Cortex-A78** | ARMv8.2-A | 3 | Yes | Snapdragon 888 | P2 |

### ARM Cortex-R (ARMv7-R / ARMv8-R)

| Core | Arch | Tier | Chips | Port Priority |
|------|------|------|-------|------|
| **Cortex-R4** | ARMv7-R | 1 | TMS570, RM48 | P2 |
| **Cortex-R5** | ARMv7-R | 1 | Zynq UltraScale+, Sitara AM65x | P2 |
| **Cortex-R7** | ARMv7-R | 1 | TMS570LC, Jacinto 7 | P2 |
| **Cortex-R8** | ARMv7-R | 1 | Automotive | P2 |
| **Cortex-R52** | ARMv8-R | 1/2 | Automotive, MPU + optional MMU | P2 |
| **Cortex-R82** | ARMv8.4-R | 2 | Real-time with MMU | P3 |

### ARM Legacy

| Core | Tier | Chips | Notes |
|------|------|-------|-------|
| **ARM7TDMI** | 0 | LPC2106, AT91SAM7, STR711 | ARMv4T, no Thumb-2 |
| **ARM926EJ-S** | 2 | i.MX27, AT91SAM9, OMAP-L138 | ARMv5, MMU |
| **ARM1176JZF-S** | 2 | RPi 1, i.MX31 | ARMv6, MMU |
| **ARM11 MPCore** | 2 | OMAP3, i.MX35 | ARMv6, SMP |

### RISC-V

| Extension | Tier | Chips | Port Priority |
|-----------|------|-------|------|
| **RV32I** | 0 | Minimal cores (no extensions) | P2 |
| **RV32IMC** | 0/1 | ESP32-C3, GD32VF103, CH32V003 | P0 |
| **RV32IMAFC** | 1 | SiFive FE310, GD32VF103 | P1 |
| **RV32IMAFDC** | 1 | SiFive U74 (HiFive Unmatched) | P1 |
| **RV64IMAC** | 1/2 | ESP32-C6, BL808 | P1 |
| **RV64GC** | 2 | SiFive U74, StarFive JH7110 | P1 |
| **RV64GC + H-ext** | 3 | QEMU, PolarFire (HSS) | P0 (existing) |
| **RV32E** | 0 | Embedded RISC-V (16 regs only) | P2 |

### Xtensa (Espressif)

| Core | Tier | Chips | Port Priority |
|------|------|-------|------|
| **Xtensa LX6** | 1 | ESP32, ESP32-S2 | P0 |
| **Xtensa LX7** | 1 | ESP32-S3 | P0 |
| **Xtensa Diamond** | 1 | ESP32-P4 (RISC-V + Xtensa) | P1 |

**Xtensa-specific challenges:**
- Windowed registers (register window shift on CALL/RET)
- Level-1/level-2/level-N interrupts with different vector tables
- Flexible-length instructions (not fixed-width)
- TIE (Tensilica Instruction Extension) per-chip customization

### AVR (Microchip/Atmel)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **ATmega** | 0 | ATmega328P (Arduino Uno), ATmega2560, ATmega4809 | 2-8KB | P0 |
| **ATtiny** | 0 | ATtiny85, ATtiny1614, ATtiny3217 | 0.5-2KB | P1 |
| **AVR-DA/DB** | 0 | AVR128DA48, AVR128DB48 | 16KB | P1 |
| **AVR-DD** | 0 | AVR64DD32 | 64KB | P2 |
| **AVR-EA** | 0 | AVR64EA48 | 64KB | P2 |

**AVR-specific challenges:**
- 8-bit data bus, 16-bit pointers
- Harvard architecture (separate code/data address spaces)
- 32 registers (R0-R31), no hardware stack pointer in some variants
- Interrupt vectors are fixed addresses (not configurable)
- `reti` (return from interrupt) only instruction for context restore
- EEPROM for persistent storage (wear leveling)

### 8051 (Intel MCS-51 derivatives)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **Classic 8051** | 0 | AT89S52, P89V51RD2, STC89C52 | 256B-1KB | P1 |
| **Enhanced 8051** | 0 | STC12/STC15/STC8, SiLabs C8051F, Nuvoton N76E | 256B-8KB | P1 |
| **Dallas/Maxim 8051** | 0 | DS80C320, DS89C430 | 1KB | P2 |
| **Silicon Labs 8051** | 0 | EFM8BB (Busy Bee), EFM8UB (Universal Bee) | 256B-4KB | P2 |

**8051-specific challenges:**
- 8-bit accumulator architecture (only `A` register for arithmetic)
- 128/256 bytes internal RAM (direct/indirect addressing)
- Bit-addressable memory (256 bits)
- 4 register banks (R0-R7 × 4)
- 16-bit program counter, 64KB code space
- Dual DPTR (data pointers) in enhanced variants
- MOVX for external memory access
- Context switch must save: ACC, B, PSW, DPTR, R0-R7 (current bank)

### PIC (Microchip)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **PIC16** | 0 | PIC16F18857, PIC16F15376 | 1-4KB | P2 |
| **PIC18** | 0 | PIC18F47K40, PIC18F26Q10 | 4KB | P2 |
| **PIC24/dsPIC** | 0/1 | PIC24FJ256, dsPIC33C | 8-64KB | P2 |
| **PIC32MX** | 1 | PIC32MX795 (MIPS32) | 128KB | P2 |
| **PIC32MZ** | 1/2 | PIC32MZ2048 (MIPS32, MMU) | 512KB | P2 |

### MSP430 (Texas Instruments)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **MSP430** | 0 | MSP430G2553, MSP430F5529 | 0.5-8KB | P2 |
| **MSP432** | 1 | MSP432P401R (Cortex-M4) | 256KB | P2 |

### Renesas

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **RL78** | 0 | R5F104LE, R7F0C004 | 2-32KB | P2 |
| **RX** | 0/1 | RX65N, RX72N (custom 32-bit ISA) | 64-512KB | P2 |
| **RA** | 1 | RA4M1 (Cortex-M33), RA6M5 (Cortex-M33) | 32-512KB | P1 |
| **RH850** | 1 | R7F701581 (automotive) | 4MB | P2 |
| **V850** | 0/1 | V850E2 (legacy automotive) | 256KB | P3 |

### Infineon TriCore

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **TriCore (TC1.x)** | 1 | TC1797, TC1796 (automotive) | 1-2MB | P2 |
| **AURIX TC2xx** | 1 | TC275, TC277 (automotive) | 4-6MB | P2 |
| **AURIX TC3xx** | 1 | TC375, TC397 (automotive) | 6-12MB | P2 |
| **AURIX TC4xx** | 1 | TC499 (next-gen automotive) | 12MB | P3 |

**TriCore-specific challenges:**
- VLIW (Very Long Instruction Word) — 2 instructions per cycle
- Circular addressing mode for DSP operations
- Context save area (CSA) — hardware-managed linked list of contexts
- No privilege levels (all supervisor mode)
- Safety features: ECC on all memories, lockstep cores, LBIST/MBIST

### SuperH (Renesas)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **SH-2** | 0/1 | SH7047, SH7085 (legacy automotive) | 8-32KB | P3 |
| **SH-2A** | 1 | SH7216, SH7286 | 64-256KB | P3 |

### PowerPC/e200 (NXP/Freescale)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **e200z4** | 2 | MPC5674F (automotive) | 256KB | P2 |
| **e200z7** | 2 | MPC5777M (automotive) | 512KB | P3 |
| **e500** | 2 | P2020, P4080 (networking) | 1-2MB | P2 (existing PPC port) |
| **e6500** | 2/3 | T2080, T4240 (networking) | 4MB+ | P3 |

### x86 / x86_64 (Intel, AMD)

| Era | Tier | Chips | RAM | Port Priority |
|-----|------|-------|-----|------|
| **8086/8088** | 0 | Original PC (1981) | 64KB-1MB | P3 |
| **286** | 0/1 | Protected mode, 16-bit | 1-16MB | P3 |
| **386** | 1/2 | 32-bit protected, paging | 4-64MB | P2 |
| **486** | 2 | Integrated FPU, cache | 4-128MB | P2 |
| **Pentium** | 2 | Superscalar, APIC | 16-512MB | P1 |
| **Pentium II/III** | 2 | Slot 1/Socket 370 | 32MB-1GB | P1 |
| **Pentium 4** | 2/3 | HyperThreading, SSE2 | 256MB-4GB | P0 |
| **Core 2** | 2/3 | 64-bit, VT-x | 512MB-8GB | P0 |
| **Atom** | 2/3 | Low-power, VT-x | 1-4GB | P1 |
| **Core i3/i5/i7** | 3 | VT-x, VT-d, AES-NI | 4-64GB | P0 (existing) |

**DDR/DDR2 era focus (2000-2010):**
- Pentium 4 (Willamette → Prescott, 2000-2008): DDR-266/333/400, DDR2-533/667/800
- Pentium D (Smithfield/Presler, 2005-2008): First desktop dual-core
- Core 2 Duo (Conroe/Merom/Penryn, 2006-2009): DDR2-667/800
- Core 2 Quad (Kentsfield/Yorkfield, 2007-2009): DDR2-800
- Athlon 64 (Clawhammer → Brisbane, 2003-2007): DDR-400, DDR2-667/800
- Phenom (Agena/Toliman, 2007-2009): DDR2-1066

**BIOS chip targets:**
- Winbond W39V040AP (4Mbit, LPC flash)
- SST SST49LF004A (4Mbit, FWH flash)
- PMC Pm49FL004 (4Mbit, LPC flash)
- These are 3.3V/5V flash chips on LPC/FWH bus
- x86 real-mode boot at 0xFFFFFFF0 (4GB - 16)
- UniversalisOS can be a BIOS payload (like coreboot/SeaBIOS)

### MIPS

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **MIPS32 M4K** | 1 | PIC32MX, PIC32MZ | 32-512KB | P2 |
| **MIPS32 microAptiv** | 1 | PIC32MK, WFI32E01 | 256KB | P2 |
| **MIPS32 24K** | 2 | Atheros AR71xx (routers) | 32-128MB | P2 |
| **MIPS32 74K** | 2 | Broadcom BCM7xxx (set-top boxes) | 128-512MB | P1 |
| **MIPS64** | 2 | Loongson 2F, Baikal-T1 | 1-4GB | P3 |

### ARC (Synopsys)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **ARC EM** | 0/1 | IoT sensors (DesignWare) | 4-64KB | P3 |
| **ARC HS** | 1 | High-performance embedded | 64-256KB | P3 |

### NIOS II (Intel/Altera FPGA)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **NIOS II/e** | 0 | Cyclone, Stratix FPGA | External | P2 |
| **NIOS II/f** | 1 | Cyclone V, Arria 10 FPGA | External | P2 |
| **NIOS II/s** | 0/1 | Cyclone, Stratix FPGA | External | P2 |

### 8-bit Legacy (for the absolute madlads)

| Family | Tier | Chips | RAM | Port Priority |
|--------|------|-------|-----|------|
| **Z80** | 0 | Z84C00, eZ80, Z180 | 64-512KB | P3 |
| **HC11** | 0 | MC68HC11, MC9S12 | 1-12KB | P3 |
| **HC12** | 0 | MC9S12X | 8-64KB | P3 |
| **6502** | 0 | WDC 65C02, 65C816 | 64KB-16MB | P3 |
| **68000** | 1 | MC68000, MC68020, MC68030 | 1-16MB | P3 |

---

## Port Priority Summary

| Priority | Targets | Count |
|----------|---------|-------|
| **P0** | Cortex-M0/M0+, M3, M4, M33, RISC-V32IMC, Xtensa LX6/LX7, ATmega, Pentium 4, Core 2, x86_64 (existing) | 12 |
| **P1** | Cortex-M7, M23, M55, Cortex-A7/A53, ESP32-C3/C6, RISC-V64, RX65, TriCore AURIX, Pentium II/III | 10 |
| **P2** | Cortex-R4/R5, PIC32, MIPS, 8051, NIOS II, 386/486, HC11, ATtiny | 12 |
| **P3** | Z80, 6502, 68000, SH-2, AVR-DD/EA, ARC, V850, 8086/286 | 8 |

**Total: 42 architecture targets across 12 ISA families.**

---

## Implementation Strategy: How to Cover Everything

### The Port Template

Every architecture gets exactly the same 4-file template:

```
kernel/ports/<arch>/<tier>/
    uos_port.h             ← Critical section macros, arch defines
    uos_port_init.c        ← HW init (NVIC/PMP/MMU/timer)
    uos_port_context.S     ← Context save/restore (interrupt handler)
    uos_port_dispatch.S    ← First task launch
```

### Shared Code vs Port Code

```
kernel/src/core/     ← 100% shared (uos_task, uos_sched, uos_sem, etc.)
kernel/src/port/     ← 0% shared (arch-specific)
kernel/include/      ← 100% shared (uos_api.h, uos_types.h)
```

The core code NEVER uses `#ifdef ARCH_*`. Instead, the port layer exports a uniform interface via `uos_port.h`. The core calls `uos_port_critical_enter()`, `uos_port_yield()`, `uos_port_dispatch_first()` — the port layer handles the hardware.

### Tier-Scaled Compilation

```c
// kernel/src/core/uos_task.c — same file for ALL tiers
uos_task_t* uos_task_create(const char* name, uos_prio_t prio,
                            void (*entry)(void*), void* arg,
                            void* stack, uos_size_t stack_size) {
#if UOS_TIER == 0
    // Static allocation from task pool
    uos_task_t* task = uos_task_pool_alloc();
    if (!task) return NULL;
#else
    // Dynamic allocation from heap
    uos_task_t* task = uos_mem_alloc(sizeof(uos_task_t));
    if (!task) return NULL;
#endif

    task->priority = prio;
    task->entry = entry;
    task->arg = arg;
    task->stack_ptr = stack;
    task->stack_size = stack_size;

#if UOS_TIER >= 1
    // MPU/PMP: set memory protection for this task's stack
    uos_port_mpu_set_region(0, (uint32_t)stack, stack_size,
                            UOS_MPU_ATTR_RW | UOS_MPU_ATTR_USER);
#endif

    uos_task_ready_enqueue(task);
    return task;
}
```

---

## The UniversalisOS Promise

> "Install UniversalisOS on any chip, run any RTOS personality on top."
>
> - STM32F0 (Cortex-M0, 4KB RAM): UniversalisOS microkernel + FreeRTOS personality
> - ESP32 (Xtensa, 520KB RAM): UniversalisOS microkernel + Zephyr personality
> - Pentium 4 (DDR2, 2GB RAM): UniversalisOS hypervisor + Linux guest + Windows guest
> - nRF52840 (Cortex-M4, 256KB RAM): UniversalisOS microkernel + ThreadX personality
> - 8051 (256 bytes RAM): UniversalisOS nano-kernel (cooperative task switcher)
> - Core 2 Duo (DDR2, 4GB RAM): UniversalisOS hypervisor + multiple RTOS partitions
> - ATmega328P (Arduino, 2KB RAM): UniversalisOS nano-kernel + cooperative tasks
> - RISC-V ESP32-C3: UniversalisOS microkernel + FreeRTOS personality
>
> **Every chip. Every era. Every vendor. uos_ prefix everywhere.**