Fábio Coutada
98ed638f3c
All uncommitted work from ESP32 GDB stub development session. Includes: - GDB stub (uos_gdbstub.c/.h/_entry.S) - Startup vector table rewrite - ESP32 HAL integration files - Boot chain design docs - AGENTS.md absolute rules (commit before refactor, no unauthorized changes) - All prior deepseek session work This commit prevents further data loss. No claims of correctness.
39 lines
1.5 KiB
Text
39 lines
1.5 KiB
Text
menu "ESP-Driver:Camera Controller Configurations"
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depends on SOC_MIPI_CSI_SUPPORTED || SOC_ISP_DVP_SUPPORTED || SOC_LCDCAM_CAM_SUPPORTED
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config CAM_CTLR_MIPI_CSI_ISR_CACHE_SAFE
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bool "CSI ISR Cache-Safe"
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depends on SOC_MIPI_CSI_SUPPORTED
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default n
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select DW_GDMA_ISR_IRAM_SAFE
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select DW_GDMA_CTRL_FUNC_IN_IRAM
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select DW_GDMA_SETTER_FUNC_IN_IRAM
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select DW_GDMA_GETTER_FUNC_IN_IRAM
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help
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Ensure the CSI driver ISR is Cache-Safe. When enabled, the ISR handler
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will be available when the cache is disabled.
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config CAM_CTLR_ISP_DVP_ISR_CACHE_SAFE # IDF-10093
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bool "ISP_DVP ISR Cache-Safe"
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depends on SOC_ISP_DVP_SUPPORTED
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default n
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select DW_GDMA_ISR_IRAM_SAFE
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select DW_GDMA_CTRL_FUNC_IN_IRAM
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select DW_GDMA_SETTER_FUNC_IN_IRAM
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select DW_GDMA_GETTER_FUNC_IN_IRAM
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help
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Ensure the ISP_DVP driver ISR is Cache-Safe. When enabled, the ISR handler
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will be available when the cache is disabled.
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config CAM_CTLR_DVP_CAM_ISR_CACHE_SAFE
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bool "DVP ISR Cache-Safe"
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depends on SOC_LCDCAM_CAM_SUPPORTED
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default n
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select GDMA_ISR_HANDLER_IN_IRAM if SOC_GDMA_SUPPORTED
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select GDMA_CTRL_FUNC_IN_IRAM if SOC_GDMA_SUPPORTED
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help
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Ensure the DVP driver ISR is Cache-Safe. When enabled, the ISR handler
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will be available when the cache is disabled.
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endmenu # ESP Camera Controller Configurations
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