Fábio Coutada
62e8454f91
- make-uefi-iso.sh: UEFI ISO image builder - test_boot.S, test_boot.ld: test boot assembly and linker script - eim_config.toml: EIM (External Interface Module) configuration - edk2-ovmf RPM for UEFI firmware - GAP_ANALYSIS_PIKEOS_PARITY.md: PikeOS parity gap analysis
129 lines
4.9 KiB
C
129 lines
4.9 KiB
C
/*
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* UniversalisOS Microkernel — Hard Real-Time Monitoring
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*
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* HRT-2.1: Execution budget enforcement (WCET overrun detection)
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* HRT-2.2: ISR latency measurement
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*
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* Design:
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* - exec_consumed is incremented every tick for the running task.
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* - If exec_consumed > exec_budget, the protection hook fires.
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* - ISR entry/exit timestamps are captured via DWT cycle counter
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* (Cortex-M3+) or SysTick counter (Cortex-M0).
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*
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* Bounds:
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* - uos_hrt_tick_check: O(1) — single comparison
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* - uos_hrt_isr_enter/exit: O(1) — 2 register reads + compare
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*/
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#ifndef UOS_HRT_H
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#define UOS_HRT_H
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#include "uos_types.h"
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#include "uos_api.h"
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/* ====================================================================== */
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/* Protection Hook (called on WCET overrun, stack overflow, etc.) */
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/* ====================================================================== */
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typedef enum {
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UOS_HRT_VIOLATION_NONE = 0,
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UOS_HRT_VIOLATION_EXEC_BUDGET = 1, /* Task exceeded its WCET budget */
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UOS_HRT_VIOLATION_INTERARRIVAL = 2, /* Task activated too soon */
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UOS_HRT_VIOLATION_STACK_OVERFLOW= 3, /* Stack canary corrupted */
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UOS_HRT_VIOLATION_ISR_LATENCY = 4, /* ISR latency exceeded bound */
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} uos_hrt_violation_t;
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typedef enum {
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UOS_HRT_ACTION_IGNORE = 0,
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UOS_HRT_ACTION_SUSPEND_TASK = 1,
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UOS_HRT_ACTION_TERMINATE_TASK = 2,
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UOS_HRT_ACTION_SHUTDOWN = 3,
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} uos_hrt_action_t;
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typedef uos_hrt_action_t (*uos_hrt_hook_t)(uos_hrt_violation_t violation,
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uos_task_t* task,
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uos_tick_t value);
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/* Register the global protection hook */
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void uos_hrt_set_hook(uos_hrt_hook_t hook);
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/* ====================================================================== */
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/* Execution Budget API */
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/* ====================================================================== */
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/* Set execution budget for a task (max ticks per activation) */
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void uos_hrt_set_exec_budget(uos_task_t* task, uos_tick_t budget_ticks);
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/* Set minimum inter-arrival time (for periodic tasks) */
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void uos_hrt_set_interarrival(uos_task_t* task, uos_tick_t min_ticks);
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/* Called from tick handler: check running task's budget */
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void uos_hrt_tick_check(void);
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/* Called when a task is activated: reset budget, check inter-arrival */
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void uos_hrt_on_activate(uos_task_t* task);
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/* ====================================================================== */
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/* ISR Latency Measurement */
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/* ====================================================================== */
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typedef struct {
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uint32_t min_cycles; /* Minimum ISR latency in CPU cycles */
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uint32_t max_cycles; /* Maximum ISR latency in CPU cycles */
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uint32_t count; /* Number of ISR invocations measured */
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uint32_t threshold; /* Alert threshold (0 = unchecked) */
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uint32_t overrun_count; /* Times threshold was exceeded */
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} uos_hrt_isr_stat_t;
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/* Register an ISR for latency measurement */
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void uos_hrt_isr_register(uint32_t irq_num, uint32_t threshold_cycles);
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/* Called at ISR entry — captures cycle counter */
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void uos_hrt_isr_enter(uint32_t irq_num);
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/* Called at ISR exit — computes latency, updates stats */
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void uos_hrt_isr_exit(uint32_t irq_num);
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/* Get ISR latency statistics */
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const uos_hrt_isr_stat_t* uos_hrt_isr_get_stats(uint32_t irq_num);
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/* Reset all ISR statistics */
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void uos_hrt_isr_reset_stats(void);
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/* ====================================================================== */
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/* Cycle Counter (port-provided) */
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/* ====================================================================== */
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/* Read the CPU cycle counter.
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* Cortex-M3+: DWT->CYCCNT
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* Cortex-M0: approximate via SysTick->VAL */
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UOS_INLINE uint32_t uos_hrt_cycle_count(void) {
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || \
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defined(__ARM_ARCH_8M__) || defined(__ARM_ARCH_8M_MAIN__)
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/* DWT cycle counter (Cortex-M3+) */
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volatile uint32_t* dwt_cyccnt = (volatile uint32_t*)0xE0001004;
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return *dwt_cyccnt;
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#else
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/* Cortex-M0: no DWT, approximate with a raw counter.
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* The port layer can override this. */
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static volatile uint32_t mock_cycles;
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return ++mock_cycles;
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#endif
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}
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/* Initialize the cycle counter (enable DWT on M3+) */
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void uos_hrt_cycle_counter_init(void);
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/* ====================================================================== */
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/* Statistics */
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/* ====================================================================== */
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/* Get worst-case observed execution time for a task (in ticks) */
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uos_tick_t uos_hrt_get_worst_case(uos_task_t* task);
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/* Global context-switch count */
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extern volatile uint32_t uos_hrt_switch_count;
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/* Global tick count with ISR entry overhead */
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extern volatile uint32_t uos_hrt_tick_isr_cycles;
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#endif /* UOS_HRT_H */
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