Fábio Coutada
62e8454f91
- make-uefi-iso.sh: UEFI ISO image builder - test_boot.S, test_boot.ld: test boot assembly and linker script - eim_config.toml: EIM (External Interface Module) configuration - edk2-ovmf RPM for UEFI firmware - GAP_ANALYSIS_PIKEOS_PARITY.md: PikeOS parity gap analysis
98 lines
3.6 KiB
C
98 lines
3.6 KiB
C
/*
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* UniversalisOS Microkernel — MPU Region Abstraction
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*
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* ARMv6-M (Cortex-M0/M0+): No MPU.
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* ARMv7-M (Cortex-M3/M4/M7): Up to 16 MPU regions.
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* ARMv8-M (Cortex-M23/M33): Up to 16 MPU regions + optional TrustZone.
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*
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* Region assignment (hard RT):
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* Region 0: Kernel code (FLASH) — priv RX, unpriv none
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* Region 1: Kernel data (RAM) — priv RW, unpriv none
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* Region 2: Per-task stack — reconfigured on every context switch
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* Region 3: Peripherals (0x40000000+) — priv RW, device, XN
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*/
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#ifndef UOS_MPU_H
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#define UOS_MPU_H
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#include "uos_types.h"
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#include "uos_config.h"
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/* ====================================================================== */
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/* Constants (always available — no MPU required) */
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/* ====================================================================== */
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/* Region access permissions (RASR.AP field, bits 4:2) */
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#define UOS_MPU_AP_NONE 0x00 /* No access */
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#define UOS_MPU_AP_RW_PRIV 0x03 /* RW privileged only */
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#define UOS_MPU_AP_RO_PRIV 0x05 /* RO privileged only */
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/* Region enable/disable */
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#define UOS_MPU_REGION_ENABLE 1
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#define UOS_MPU_REGION_DISABLE 0
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/* MPU region assignments */
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#define UOS_MPU_REGION_KERNEL_CODE 0
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#define UOS_MPU_REGION_KERNEL_DATA 1
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#define UOS_MPU_REGION_TASK_STACK 2
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#define UOS_MPU_REGION_PERIPHERALS 3
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/* Region sizes (log2) */
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#define UOS_MPU_SIZE_32B 4
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#define UOS_MPU_SIZE_64B 5
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#define UOS_MPU_SIZE_128B 6
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#define UOS_MPU_SIZE_256B 7
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#define UOS_MPU_SIZE_512B 8
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#define UOS_MPU_SIZE_1KB 9
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#define UOS_MPU_SIZE_2KB 10
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#define UOS_MPU_SIZE_4KB 11
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#define UOS_MPU_SIZE_8KB 12
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#define UOS_MPU_SIZE_16KB 13
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#define UOS_MPU_SIZE_32KB 14
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#define UOS_MPU_SIZE_64KB 15
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#define UOS_MPU_SIZE_128KB 16
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#define UOS_MPU_SIZE_256KB 17
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#define UOS_MPU_SIZE_512KB 18
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#define UOS_MPU_SIZE_1MB 19
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#define UOS_MPU_SIZE_2MB 20
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#define UOS_MPU_SIZE_4MB 21
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/* ====================================================================== */
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/* MPU Register Access (Cortex-M3/M4/M7) */
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/* ====================================================================== */
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#if UOS_HAS_MPU
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#define UOS_MPU_TYPE (*(volatile uint32_t*)0xE000ED90)
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#define UOS_MPU_CTRL (*(volatile uint32_t*)0xE000ED94)
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#define UOS_MPU_RNR (*(volatile uint32_t*)0xE000ED98)
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#define UOS_MPU_RBAR (*(volatile uint32_t*)0xE000ED9C)
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#define UOS_MPU_RLAR (*(volatile uint32_t*)0xE000EDA0)
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void uos_mpu_init(void);
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void uos_mpu_set_region(uint32_t region_num, uint32_t base,
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uint32_t size_log2, uint32_t attr);
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void uos_mpu_set_region_rasar(uint32_t region_num, uint32_t rbar,
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uint32_t rasr);
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void uos_mpu_region_enable(uint32_t region_num);
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void uos_mpu_region_disable(uint32_t region_num);
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void uos_mpu_enable(void);
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void uos_mpu_disable(void);
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/* Configure MPU region 2 for a task's stack (called on context switch).
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* O(1) — 3 register writes + DSB. */
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void uos_mpu_apply_task(const void* task);
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#else /* No MPU — no-ops */
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UOS_INLINE void uos_mpu_init(void) {}
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UOS_INLINE void uos_mpu_set_region(uint32_t r, uint32_t b, uint32_t s, uint32_t a) { (void)r; (void)b; (void)s; (void)a; }
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UOS_INLINE void uos_mpu_set_region_rasar(uint32_t r, uint32_t b, uint32_t rasr) { (void)r; (void)b; (void)rasr; }
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UOS_INLINE void uos_mpu_region_enable(uint32_t r) { (void)r; }
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UOS_INLINE void uos_mpu_region_disable(uint32_t r) { (void)r; }
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UOS_INLINE void uos_mpu_enable(void) {}
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UOS_INLINE void uos_mpu_disable(void) {}
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UOS_INLINE void uos_mpu_apply_task(const void* t) { (void)t; }
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#endif /* UOS_HAS_MPU */
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#endif /* UOS_MPU_H */
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