Fábio Coutada
9540b0528c
Phase B (Core Device Support) — all drivers verified in QEMU: - Network: virtio-net cleanup, RTL8139, E1000, clause-22 MDIO PHY management, CAN bus, industrial protocols (Modbus/Profibus/EtherCAT), controller probe+dispatch - Block storage: RAM disk backend (write->read->verify PASSED), virtio-blk transport, backend dispatch, real MBR+GPT partition parsers, SD/eMMC command framework - GPIO: PL061 (verified), I2C: DesignWare (verified), SPI: PL022 (verified) Phase C (Advanced Features): - PCI: FULL PikeOS ARMv7 replica — transport-agnostic uos_pci_ops, config-address encoding, BAR sizing, capability walk, enumeration+bridge recursion, MSI/MSI-X - USB: PikeOS-style layered stack — usb.h contract, usb_core.cpp (enumeration state machine), usb_ehci.cpp (EHCI transport) - Display: FULL 1:1 PikeOS fbcon replica + copied font_8x16 Build foundation fixes: - Freestanding aeabi_runtime.cpp (__aeabi_uidiv/__aeabi_uldivmod) - PikeOS-style flat 4GB MMU section map + proper enable (unblocked device MMIO) - guest.h MAX_GUEST_IMAGE_SIZE 256MB->16MB (BSS was 259MB) - C/C++ linkage fixes, duplicate-virtio_net_init, MMIO access-size handling Phase D (PikeOS ARMv7 Microkernel Port): - D-1: Per-VM address spaces — cloned pgdirs, ASID-tagged TLB, 4K page walker, isolation PASSED (two guests, same VA->different PAs), guest fault recovery - D-2: IRQ dispatch backbone — 1024-slot dispatch table, real GICv2 hardware (GICD_CTLR/GICC_CTLR/GICC_PMR/GICC_IAR/GICC_EOIR), arm_irq_handler wired - D-3: Time subsystem — CNTVCT ns-since-boot, CNTP periodic ticker via D-2 - D-4: KDEV framework — linker-section driver registration, uos_kdev_init_all, name lookup - D-5: VFP/NEON — lazy enable (undef trap->CPACR+FPEXC.EN), FPEXC=0x40000000 - D-6: SMP — per-CPU state, MPIDR, IPI/SGI framework (reschedule+TLB flush) All uos_ naming (PikeOS p4_ convention adapted). Compiles -Werror freestanding C++17. Co-Authored-By: Claude <noreply@anthropic.com>
89 lines
3.4 KiB
C
89 lines
3.4 KiB
C
/*
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* Universalisos per-VM address-space management (uos_adspace.h)
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*
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* 1:1 adaptation of PikeOS arch/arm/src/adspace.c. Each guest/VM gets an
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* independent TTBR0 user page directory (half-size: UOS_PD_ENTRIES/2 entries,
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* covering [0, UOS_MEM_USR_END)). uos_arch_adspace_set_active() performs the
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* TTBR0 + ASID + BTAC switch on guest entry — the core of per-VM isolation.
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*
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* CP15 primitives (set_asid/set_ttbr0/inval_btac/tlb_inval_asid) and the global
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* per-VM pgdir pool are supplied by uos_cmm.cpp.
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*
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* Author: PortugalFuturista Hypervisor Development Team (adapted from SYSGO PikeOS)
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*/
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#ifndef UOS_ADSPACE_H
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#define UOS_ADSPACE_H
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#include <stdint.h>
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#include "uos_armmmu_v6.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Per-VM isolation model (D-1 pragmatic approach):
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* TTBCR=0 (no TTBR0/TTBR1 split); TTBR0 covers all 4 GB. Each guest gets a
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* FULL-SIZE 16 KB pgdir cloned from the kernel flat map — kernel/device
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* sections carry AP=privileged-only (UOS_PD_AP0) so user-mode guests fault on
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* them, while supervisor-mode kernel code can access everything. Guest-specific
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* user pages are added with AP=user-RW. Isolation is via AP bits + per-guest
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* ASID-tagged TLB, not VA-range split. This avoids the risky 0x80000000 kernel
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* relocation; a future hardening can switch to the full PikeOS split (TTBCR=1). */
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#define UOS_MEM_USR_BASE 0x00000000u
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#define UOS_MEM_USR_END 0x40000000u /* guest user space: 1 GB below kernel */
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#define UOS_MEM_KERN_BASE 0x40000000u /* kernel + devices live here (identity-mapped) */
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/* With TTBCR=0 (identity), KERN_TO_PHYS/PHYS_TO_KERN are no-ops. */
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#define UOS_KERN_TO_PHYS(x) ((uint32_t)(x))
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#define UOS_PHYS_TO_KERN(x) ((uint32_t)(x))
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/* Per-task MMU context (PikeOS P4k_task_mmuctxt_t). */
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typedef struct {
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uint32_t *pgdir; /* points into uos_user_pgdirs[]; NULL == kernel/idle task */
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} uos_task_mmuctxt_t;
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/* Minimal taskinfo carrying the adspace + a task number used as the ASID. */
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typedef struct {
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uos_task_mmuctxt_t adspace;
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uint32_t taskno;
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} uos_taskinfo_t;
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/* --- CP15 primitives (implemented in uos_cmm.cpp) --- */
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void uos_arm_dsb(void);
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void uos_arm_set_asid(uint32_t asid);
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void uos_arm_set_ttbr0(uint32_t ttbr0);
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void uos_arm_inval_btac(void);
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void uos_arm_tlb_inval_all(void);
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void uos_arm_tlb_inval_asid(uint32_t asid);
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void uos_arm_tlb_inval_page(uint32_t mva);
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/* --- Global per-VM user page-directory pool (allocated in uos_arm_init_mmu) --- */
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extern uint32_t *uos_user_pgdirs;
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/* Free an L2 page table behind a user VA (implemented in uos_mmu_walk.cpp). */
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void uos_arm_free_pt(uos_taskinfo_t *td, uint32_t vaddr);
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/* --- Address-space lifecycle (PikeOS adspace.c) --- */
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/** Switch TTBR0/ASID to the task's address space. */
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void uos_arch_adspace_set_active(uos_taskinfo_t *td, uos_taskinfo_t *prev);
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/** Set up the idle/kernel task (runs purely on TTBR1). */
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void uos_arch_adspace_register_kernel(uos_taskinfo_t *td);
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/** Initialise a new address space (pgdir deferred). Returns 0 on success. */
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int uos_arch_adspace_init(uos_taskinfo_t *td);
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/** Assign the task its half-size user pgdir out of the global pool. */
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void uos_arch_adspace_register_user(uos_taskinfo_t *td);
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/** Unused callback (PikeOS leaves empty). */
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void uos_arch_adspace_free(uos_taskinfo_t *td);
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/** Unmap + free the task's entire user address space; flush its ASID TLB. */
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void uos_arch_adspace_unmap_user(uos_taskinfo_t *td);
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#ifdef __cplusplus
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}
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#endif
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#endif /* UOS_ADSPACE_H */
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