Fábio Coutada
b8af1e6ec2
## Agent System - **Plan Maintainer Agent**: Manages session context and verifies todo lists - **Aurelio Agent**: Imports Claude Code sessions and syncs to backend ## Universalisos Kernel Run Skill - **Build & Launch**: Automated kernel build and QEMU execution - **Driver Script**: Test automation with output validation - **Fixed Issues**: Section directive errors, exception handlers, stack symbols ## Context Monitoring System - **Measurement**: Real-time token counting and usage tracking - **Continuous Monitoring**: Background compaction to prevent data loss - **Automatic Compaction**: Preserves important context to memory - **Alert System**: Desktop notifications for threshold events - **Historical Tracking**: Usage trends and optimization recommendations ## Kernel Enhancements - **Fixed boot.S**: Corrected section directives and stack symbol naming - **Exception Handlers**: Added C stubs for ARM exception handling - **RISC-V Support**: Added boot and exception handling for RISC-V - **Core Components**: IPC, scheduler, heap manager, safety framework ## Integration - **Aurelio Backend**: PortugalFuturista MCP synchronization - **Memory System**: Context preservation before compaction - **Automated Testing**: Driver scripts for all components Co-Authored-By: Claude <noreply@anthropic.com>
177 lines
No EOL
3.8 KiB
ArmAsm
177 lines
No EOL
3.8 KiB
ArmAsm
/*
|
|
* Universalisos RISC-V Boot Code
|
|
* PikeOS 5.0 Feature Parity - RISC-V 64-bit Architecture Support
|
|
*
|
|
* This code handles:
|
|
* - RISC-V boot sequence for 64-bit mode
|
|
* - Exception vector table setup
|
|
* - Trap handling for RISC-V
|
|
* - Context saving and restoration
|
|
* - Platform initialization (QEMU virt machine)
|
|
*/
|
|
|
|
.section .text.boot
|
|
.global _start
|
|
|
|
_start:
|
|
/*
|
|
* RISC-V boot entry point
|
|
* QEMU loads the kernel at 0x80200000 and jumps here
|
|
*/
|
|
|
|
/* Disable interrupts until kernel is ready */
|
|
csrw mie, zero
|
|
|
|
/* Set up stack pointer */
|
|
lui sp, %hi(_stack_top)
|
|
addi sp, sp, %lo(_stack_top)
|
|
|
|
/* Check hart ID - we only run on hart 0 */
|
|
csrr a0, mhartid
|
|
bnez a0, halt_other_harts
|
|
|
|
halt_other_harts:
|
|
/* Other harts wait here */
|
|
wfi
|
|
j halt_other_harts
|
|
|
|
/* Clear BSS section */
|
|
main_hart:
|
|
lui a0, %hi(_bss_start)
|
|
addi a0, a0, %lo(_bss_start)
|
|
lui a1, %hi(_bss_end)
|
|
addi a1, a1, %lo(_bss_end)
|
|
|
|
bss_loop:
|
|
bge a0, a1, bss_done
|
|
sw zero, 0(a0)
|
|
addi a0, a0, 4
|
|
j bss_loop
|
|
|
|
bss_done:
|
|
/* Set up trap vector (exception handler table) */
|
|
la t0, trap_vector
|
|
csrw mtvec, t0
|
|
|
|
/* Configure trap vector to use direct mode */
|
|
/* mtvec[1:0] = 0 for direct mode */
|
|
|
|
/* Enable machine-mode external interrupts */
|
|
csrr t0, mie
|
|
ori t0, t0, 0x800 /* Enable MEIE (machine external interrupt enable) */
|
|
csrw mie, t0
|
|
|
|
/* Set up machine stack pointer (MSP) */
|
|
lui sp, %hi(_stack_top)
|
|
addi sp, sp, %lo(_stack_top)
|
|
|
|
/* Jump to C kernel */
|
|
call kernel_main
|
|
|
|
/* Halt if kernel_main returns */
|
|
halt:
|
|
wfi
|
|
j halt
|
|
|
|
/*
|
|
* RISC-V Trap Vector Table
|
|
* All exceptions and interrupts go through mtvec
|
|
* In direct mode, all traps jump to this address
|
|
*/
|
|
.align 4
|
|
.global trap_vector
|
|
trap_vector:
|
|
/*
|
|
* Save caller-saved registers
|
|
* RISC-V ABI: t0-t6, a0-a7 are caller-saved
|
|
*/
|
|
addi sp, sp, -128
|
|
|
|
/* Save general purpose registers */
|
|
sd x1, 0(sp) /* ra (return address) */
|
|
sd x5, 8(sp) /* t0 */
|
|
sd x6, 16(sp) /* t1 */
|
|
sd x7, 24(sp) /* t2 */
|
|
sd x10, 32(sp) /* a0 */
|
|
sd x11, 40(sp) /* a1 */
|
|
sd x12, 48(sp) /* a2 */
|
|
sd x13, 56(sp) /* a3 */
|
|
sd x14, 64(sp) /* a4 */
|
|
sd x15, 72(sp) /* a5 */
|
|
sd x16, 80(sp) /* a6 */
|
|
sd x17, 88(sp) /* a7 */
|
|
sd x28, 96(sp) /* t3 */
|
|
sd x29, 104(sp) /* t4 */
|
|
sd x30, 112(sp) /* t5 */
|
|
sd x31, 120(sp) /* t6 */
|
|
|
|
/* Read mcause to determine exception type */
|
|
csrr a0, mcause
|
|
csrr a1, mtval /* Trap value (fault address or instruction) */
|
|
|
|
/* Read mepc (exception program counter) */
|
|
csrr a2, mepc
|
|
|
|
/* Read mstatus (machine status register) */
|
|
csrr a3, mstatus
|
|
|
|
/* Call C trap handler */
|
|
call riscv_trap_handler
|
|
|
|
/* Restore general purpose registers */
|
|
ld x1, 0(sp)
|
|
ld x5, 8(sp)
|
|
ld x6, 16(sp)
|
|
ld x7, 24(sp)
|
|
ld x10, 32(sp)
|
|
ld x11, 40(sp)
|
|
ld x12, 48(sp)
|
|
ld x13, 56(sp)
|
|
ld x14, 64(sp)
|
|
ld x15, 72(sp)
|
|
ld x16, 80(sp)
|
|
ld x17, 88(sp)
|
|
ld x28, 96(sp)
|
|
ld x29, 104(sp)
|
|
ld x30, 112(sp)
|
|
ld x31, 120(sp)
|
|
|
|
addi sp, sp, 128
|
|
|
|
/* Return from trap */
|
|
mret
|
|
|
|
/*
|
|
* Define stack regions
|
|
*/
|
|
.section .bss
|
|
.align 16
|
|
|
|
/* Main kernel stack */
|
|
.global kernel_stack
|
|
kernel_stack:
|
|
.skip 16384 /* 16KB kernel stack */
|
|
.global _stack_top
|
|
_stack_top:
|
|
|
|
/* Exception stack */
|
|
.global exception_stack
|
|
exception_stack:
|
|
.skip 8192 /* 8KB exception stack */
|
|
.global exception_stack_top
|
|
exception_stack_top:
|
|
|
|
/* User stack for kernel operations */
|
|
.global user_stack
|
|
user_stack:
|
|
.skip 8192 /* 8KB user stack */
|
|
.global user_stack_top
|
|
user_stack_top:
|
|
|
|
/*
|
|
* External symbols for BSS clearing
|
|
*/
|
|
.global _bss_start
|
|
_bss_start:
|
|
.global _bss_end
|
|
_bss_end: |