universalisos/kernel/drivers/gpio.cpp

/*
 * Universalisos GPIO Driver Implementation (ARM PrimeCell PL061)
 * Phase B Priority 6: Platform I/O
 *
 * PL061 is an 8-bit GPIO port controller. Its defining quirk is masked data
 * access: the GPIODATA register is replicated across address bits [9:2], so a
 * write to offset 0x3FC drives all pins, while a write to (1<<(pin+2)) drives
 * only that pin. We model each port once and translate masks here.
 *
 * MISRA C++ compliant, freestanding.
 *
 * Author: PortugalFuturista Hypervisor Development Team
 */

#include "gpio.h"
#include "../arch/arm/uart.h"
#include "../device.h"

/*
 * PL061 register offsets
 */
#define PL061_GPIODATA   0x000
#define PL061_GPIODIR    0x400
#define PL061_GPIOIS     0x404
#define PL061_GPIOIBE    0x408
#define PL061_GPIOIEV    0x40C
#define PL061_GPIOIM     0x410
#define PL061_GPIORIS    0x414
#define PL061_GPIOMIS    0x418
#define PL061_GPIOICR    0x41C
#define PL061_GPIOAFSEL  0x420
#define PL061_GPIOPCELLID0 0xFE0   /* PrimeCell ID: 0x11/0x61/0x00/0x00 ... */

#define PL061_PCELLID0 0x0BU
#define PL061_PCELLID1 0xF1U
#define PL061_PCELLID2 0x10U
#define PL061_PCELLID3 0x0EU

#define GPIO_MMIO_READ(base, off)    (*((volatile uint32_t*)((base) + (off))))
#define GPIO_MMIO_WRITE(base, off, v) ((*((volatile uint32_t*)((base) + (off)))) = (v))

typedef struct {
    uint32_t base;
    bool     initialized;
    uint8_t  allowed_mask;   /* for virtual ports: pins the owner may touch */
    bool     is_virtual;
    uint32_t owning_vm_id;
} gpio_port_t;

static gpio_port_t gpio_ports[MAX_GPIO_PORTS];

static gpio_port_t* find_port(uint8_t port_id) {
    if (port_id >= MAX_GPIO_PORTS) {
        return nullptr;
    }
    if (!gpio_ports[port_id].initialized) {
        return nullptr;
    }
    return &gpio_ports[port_id];
}

/**
 * Validate a PL061 by reading the PrimeCell peripheral ID.
 */
static bool gpio_validate_pl061(uint32_t base) {
    uint8_t id0 = (uint8_t)GPIO_MMIO_READ(base, PL061_GPIOPCELLID0);
    uint8_t id1 = (uint8_t)GPIO_MMIO_READ(base, PL061_GPIOPCELLID0 + 4);
    uint8_t id2 = (uint8_t)GPIO_MMIO_READ(base, PL061_GPIOPCELLID0 + 8);
    uint8_t id3 = (uint8_t)GPIO_MMIO_READ(base, PL061_GPIOPCELLID0 + 12);
    /* When no controller is present the bus reads back 0xFF; treat as absent */
    if (id0 == 0xFFU && id1 == 0xFFU) {
        return false;
    }
    return (id0 == PL061_PCELLID0 && id1 == PL061_PCELLID1 &&
            id2 == PL061_PCELLID2 && id3 == PL061_PCELLID3);
}

int gpio_init(uint8_t port_id, uint32_t base_address) {
    if (port_id >= MAX_GPIO_PORTS) {
        return -1;
    }

    gpio_port_t* port = &gpio_ports[port_id];
    port->base = base_address;
    port->allowed_mask = 0xFFU;
    port->is_virtual = false;
    port->owning_vm_id = 0;

    /* If a real PL061 is present, put it in a known state: all inputs,
     * software-controlled function, interrupts masked and cleared. */
    if (base_address != 0U) {
        if (gpio_validate_pl061(base_address)) {
            GPIO_MMIO_WRITE(base_address, PL061_GPIODIR, 0);
            GPIO_MMIO_WRITE(base_address, PL061_GPIOAFSEL, 0);
            GPIO_MMIO_WRITE(base_address, PL061_GPIOIM, 0);
            GPIO_MMIO_WRITE(base_address, PL061_GPIOICR, 0xFF);
            uart_puts("GPIO: PL061 port ");
            uart_print_dec(port_id);
            uart_puts(" initialized at 0x");
            uart_print_hex(base_address);
            uart_puts("\n");
        } else {
            uart_puts("GPIO: port ");
            uart_print_dec(port_id);
            uart_puts(" armed (no controller probed)\n");
        }
    }

    port->initialized = true;
    return 0;
}

int gpio_set_direction(uint8_t port_id, uint8_t pin_mask, gpio_direction_t direction) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr) {
        return -1;
    }
    if (port->is_virtual && (pin_mask & ~port->allowed_mask) != 0U) {
        return -2; /* VM tried to touch a disallowed pin */
    }
    if (port->base == 0U) {
        return 0; /* no hardware bound */
    }

    uint32_t dir = GPIO_MMIO_READ(port->base, PL061_GPIODIR);
    if (direction == GPIO_DIR_OUTPUT) {
        dir |= pin_mask;
    } else {
        dir &= ~(uint32_t)pin_mask;
    }
    GPIO_MMIO_WRITE(port->base, PL061_GPIODIR, dir);
    return 0;
}

int gpio_write(uint8_t port_id, uint8_t pin_mask, uint8_t value) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr) {
        return -1;
    }
    if (port->is_virtual && (pin_mask & ~port->allowed_mask) != 0U) {
        return -2;
    }
    if (port->base == 0U) {
        return 0;
    }

    /* Masked write: the effective offset encodes which bits to drive. For the
     * common case where pin_mask == 0xFF we use the all-bits offset 0x3FC. */
    uint32_t data = (uint32_t)(value & pin_mask);
    if (pin_mask == 0xFFU) {
        GPIO_MMIO_WRITE(port->base, GPIO_DATA_ALL, data);
    } else {
        uint32_t offset = 0U;
        for (uint8_t b = 0; b < 8U; b++) {
            if ((pin_mask & (1U << b)) != 0U) {
                offset |= (1U << (b + 2U));
            }
        }
        GPIO_MMIO_WRITE(port->base, offset, data);
    }
    return 0;
}

int gpio_read(uint8_t port_id, uint8_t* value) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr || value == nullptr) {
        return -1;
    }
    if (port->base == 0U) {
        *value = 0;
        return 0;
    }
    *value = (uint8_t)GPIO_MMIO_READ(port->base, GPIO_DATA_ALL);
    return 0;
}

int gpio_config_interrupt(uint8_t port_id, uint8_t pin, gpio_int_mode_t mode) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr || pin >= GPIO_PINS_PER_PORT) {
        return -1;
    }
    if (port->base == 0U) {
        return 0;
    }

    uint8_t bit = (uint8_t)(1U << pin);

    /* Mask the interrupt while we reconfigure to avoid glitches */
    uint32_t im = GPIO_MMIO_READ(port->base, PL061_GPIOIM);
    GPIO_MMIO_WRITE(port->base, PL061_GPIOIM, im & ~bit);

    /* Interrupt sense: 0 = edge, 1 = level */
    uint32_t is = GPIO_MMIO_READ(port->base, PL061_GPIOIS);
    /* Both-edge: 0 = single-edge (controlled by GPIOIEV), 1 = both edges */
    uint32_t ibe = GPIO_MMIO_READ(port->base, PL061_GPIOIBE);
    /* Event: 0 = falling/low, 1 = rising/high */
    uint32_t iev = GPIO_MMIO_READ(port->base, PL061_GPIOIEV);

    switch (mode) {
        case GPIO_INT_LEVEL_LOW:
            is |= bit; ibe &= ~bit; iev &= ~bit; break;
        case GPIO_INT_LEVEL_HIGH:
            is |= bit; ibe &= ~bit; iev |= bit;  break;
        case GPIO_INT_EDGE_FALLING:
            is &= ~bit; ibe &= ~bit; iev &= ~bit; break;
        case GPIO_INT_EDGE_RISING:
            is &= ~bit; ibe &= ~bit; iev |= bit;  break;
        case GPIO_INT_EDGE_BOTH:
            is &= ~bit; ibe |= bit;  break;
        case GPIO_INT_NONE:
        default:
            /* Leave sense regs; caller controls enable separately */
            break;
    }

    GPIO_MMIO_WRITE(port->base, PL061_GPIOIS, is);
    GPIO_MMIO_WRITE(port->base, PL061_GPIOIBE, ibe);
    GPIO_MMIO_WRITE(port->base, PL061_GPIOIEV, iev);

    /* Clear any pending interrupt before (re)enabling */
    GPIO_MMIO_WRITE(port->base, PL061_GPIOICR, bit);
    return 0;
}

int gpio_enable_interrupt(uint8_t port_id, uint8_t pin_mask, bool enable) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr) {
        return -1;
    }
    if (port->base == 0U) {
        return 0;
    }
    uint32_t im = GPIO_MMIO_READ(port->base, PL061_GPIOIM);
    if (enable) {
        im |= pin_mask;
    } else {
        im &= ~(uint32_t)pin_mask;
    }
    GPIO_MMIO_WRITE(port->base, PL061_GPIOIM, im);
    return 0;
}

int gpio_acknowledge_interrupt(uint8_t port_id, uint8_t pin_mask) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr) {
        return -1;
    }
    if (port->base == 0U) {
        return 0;
    }
    GPIO_MMIO_WRITE(port->base, PL061_GPIOICR, pin_mask);
    return 0;
}

uint8_t gpio_get_interrupt_status(uint8_t port_id) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr || port->base == 0U) {
        return 0;
    }
    return (uint8_t)GPIO_MMIO_READ(port->base, PL061_GPIOMIS);
}

void gpio_interrupt_handler(uint8_t port_id) {
    gpio_port_t* port = find_port(port_id);
    if (port == nullptr) {
        return;
    }
    uint8_t pending = gpio_get_interrupt_status(port_id);
    if (pending == 0U) {
        return;
    }

    /* Dispatch per-pin would go to registered callbacks; framework clears all. */
    gpio_acknowledge_interrupt(port_id, pending);
}

int gpio_create_virtual(uint32_t vm_id, uint8_t physical_port_id, uint8_t allowed_mask) {
    if (physical_port_id >= MAX_GPIO_PORTS) {
        return -1;
    }
    if (!gpio_ports[physical_port_id].initialized) {
        return -2;
    }

    /* Allocate a virtual slot (after the physical ports) */
    int slot = -1;
    for (int i = 0; i < MAX_GPIO_PORTS; i++) {
        if (!gpio_ports[i].initialized) {
            slot = i;
            break;
        }
    }
    if (slot < 0) {
        return -3;
    }

    gpio_port_t* v = &gpio_ports[slot];
    v->base = gpio_ports[physical_port_id].base;
    v->initialized = true;
    v->is_virtual = true;
    v->owning_vm_id = vm_id;
    v->allowed_mask = allowed_mask;

    /* Register with the device manager so the VM sees a virtual GPIO */
    extern virtual_device_t* device_create_virtual(uint32_t vm_id, const char* name,
                                                   device_type_t type);
    virtual_device_t* vd = device_create_virtual(vm_id, "Virtual-GPIO", DEVICE_TYPE_GPIO);
    if (vd != nullptr) {
        vd->state = DEVICE_STATE_ACTIVE;
    }

    return slot;
}

void gpio_driver_init(void) {
    uart_puts("\n=== GPIO Driver Initialization ===\n");
    for (int i = 0; i < MAX_GPIO_PORTS; i++) {
        gpio_ports[i].initialized = false;
    }
    /* Arm port 0 and probe the PL061 at the QEMU virt GPIO base. With the MMU
     * now on (PikeOS-style flat map), this device read is a proper strongly-
     * ordered access and should no longer hang. */
    gpio_init(0, 0x09030000U);
    uart_puts("====================================\n\n");
}

void gpio_driver_demo(void) {
    uart_puts("\n=== GPIO Driver Demonstration ===\n");

    /* Configure pins 0-3 as outputs and pins 4-7 as inputs */
    gpio_set_direction(0, 0x0F, GPIO_DIR_OUTPUT);
    gpio_set_direction(0, 0xF0, GPIO_DIR_INPUT);

    /* Drive a pattern on the outputs */
    gpio_write(0, 0x0F, 0x0A);

    /* Read back all 8 pins */
    uint8_t value = 0;
    gpio_read(0, &value);
    uart_puts("GPIO: port 0 reads 0x");
    uart_print_hex(value);
    uart_puts("\n");

    /* Configure a rising-edge interrupt on pin 4 (demonstrates the path) */
    gpio_config_interrupt(0, 4, GPIO_INT_EDGE_RISING);
    gpio_enable_interrupt(0, (1U << 4), true);

    uart_puts("=== End GPIO Demonstration ===\n\n");
}