Fábio Coutada
9540b0528c
Phase B (Core Device Support) — all drivers verified in QEMU: - Network: virtio-net cleanup, RTL8139, E1000, clause-22 MDIO PHY management, CAN bus, industrial protocols (Modbus/Profibus/EtherCAT), controller probe+dispatch - Block storage: RAM disk backend (write->read->verify PASSED), virtio-blk transport, backend dispatch, real MBR+GPT partition parsers, SD/eMMC command framework - GPIO: PL061 (verified), I2C: DesignWare (verified), SPI: PL022 (verified) Phase C (Advanced Features): - PCI: FULL PikeOS ARMv7 replica — transport-agnostic uos_pci_ops, config-address encoding, BAR sizing, capability walk, enumeration+bridge recursion, MSI/MSI-X - USB: PikeOS-style layered stack — usb.h contract, usb_core.cpp (enumeration state machine), usb_ehci.cpp (EHCI transport) - Display: FULL 1:1 PikeOS fbcon replica + copied font_8x16 Build foundation fixes: - Freestanding aeabi_runtime.cpp (__aeabi_uidiv/__aeabi_uldivmod) - PikeOS-style flat 4GB MMU section map + proper enable (unblocked device MMIO) - guest.h MAX_GUEST_IMAGE_SIZE 256MB->16MB (BSS was 259MB) - C/C++ linkage fixes, duplicate-virtio_net_init, MMIO access-size handling Phase D (PikeOS ARMv7 Microkernel Port): - D-1: Per-VM address spaces — cloned pgdirs, ASID-tagged TLB, 4K page walker, isolation PASSED (two guests, same VA->different PAs), guest fault recovery - D-2: IRQ dispatch backbone — 1024-slot dispatch table, real GICv2 hardware (GICD_CTLR/GICC_CTLR/GICC_PMR/GICC_IAR/GICC_EOIR), arm_irq_handler wired - D-3: Time subsystem — CNTVCT ns-since-boot, CNTP periodic ticker via D-2 - D-4: KDEV framework — linker-section driver registration, uos_kdev_init_all, name lookup - D-5: VFP/NEON — lazy enable (undef trap->CPACR+FPEXC.EN), FPEXC=0x40000000 - D-6: SMP — per-CPU state, MPIDR, IPI/SGI framework (reschedule+TLB flush) All uos_ naming (PikeOS p4_ convention adapted). Compiles -Werror freestanding C++17. Co-Authored-By: Claude <noreply@anthropic.com>
127 lines
3.3 KiB
C
127 lines
3.3 KiB
C
/*
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* Universalisos GPIO Driver
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* Phase B Priority 6: Platform I/O - General Purpose I/O
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*
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* ARM PrimeCell PL061 GPIO controller (8-bit ports), as emulated by QEMU virt.
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* Provides pin configuration, read/write, edge/level interrupts, and
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* virtualization hooks for guest VM passthrough.
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*
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* MISRA C++ compliant, freestanding, no dynamic allocation.
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*
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* Author: PortugalFuturista Hypervisor Development Team
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*/
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#ifndef UNIVERSALISOS_DRIVERS_GPIO_H
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#define UNIVERSALISOS_DRIVERS_GPIO_H
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* GPIO pin direction
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*/
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typedef enum {
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GPIO_DIR_INPUT = 0,
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GPIO_DIR_OUTPUT
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} gpio_direction_t;
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/**
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* GPIO interrupt trigger mode
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*/
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typedef enum {
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GPIO_INT_NONE = 0, /* Disable interrupts */
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GPIO_INT_LEVEL_LOW, /* Level-sensitive, active low */
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GPIO_INT_LEVEL_HIGH, /* Level-sensitive, active high */
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GPIO_INT_EDGE_FALLING, /* Falling edge */
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GPIO_INT_EDGE_RISING, /* Rising edge */
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GPIO_INT_EDGE_BOTH /* Both edges */
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} gpio_int_mode_t;
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/**
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* Maximum number of PL061 ports (one PL061 = 8 pins; virt exposes several)
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*/
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#define MAX_GPIO_PORTS 8
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#define GPIO_PINS_PER_PORT 8
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/**
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* PL061 masked-data access: bits are accessed via address bits [9:2].
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* Offset 0x3FC addresses all 8 bits at once.
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*/
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#define GPIO_DATA_ALL 0x3FCU
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/**
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* Initialize a PL061 GPIO port.
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* @param port_id Logical port index (0..MAX_GPIO_PORTS-1)
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* @param base_address MMIO base of the PL061 controller
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* @return 0 on success, negative on error
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*/
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int gpio_init(uint8_t port_id, uint32_t base_address);
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/**
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* Configure pin direction(s).
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* @param port_id Port index
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* @param pin_mask Bitmask of pins to configure (1 = affected)
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* @param direction Input or output
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* @return 0 on success, negative on error
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*/
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int gpio_set_direction(uint8_t port_id, uint8_t pin_mask, gpio_direction_t direction);
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/**
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* Write to output pin(s). Only pins set in pin_mask are driven.
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*/
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int gpio_write(uint8_t port_id, uint8_t pin_mask, uint8_t value);
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/**
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* Read the current level of all 8 pins.
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*/
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int gpio_read(uint8_t port_id, uint8_t* value);
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/**
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* Configure interrupt trigger mode for a single pin.
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*/
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int gpio_config_interrupt(uint8_t port_id, uint8_t pin, gpio_int_mode_t mode);
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/**
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* Enable/disable the interrupt for a pin mask.
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*/
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int gpio_enable_interrupt(uint8_t port_id, uint8_t pin_mask, bool enable);
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/**
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* Acknowledge (clear) pending interrupts for a pin mask.
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*/
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int gpio_acknowledge_interrupt(uint8_t port_id, uint8_t pin_mask);
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/**
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* Read masked interrupt status (only enabled, pending interrupts).
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*/
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uint8_t gpio_get_interrupt_status(uint8_t port_id);
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/**
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* GPIO interrupt handler (called by the GIC dispatch for the port's IRQ).
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*/
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void gpio_interrupt_handler(uint8_t port_id);
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/**
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* Create a virtual GPIO port for a guest VM (passthrough subset).
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* @param vm_id Owning VM
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* @param physical_port_id Backing physical port
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* @param allowed_mask Bitmask of pins the VM may access
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* @return Virtual port id (>=0) on success, negative on error
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*/
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int gpio_create_virtual(uint32_t vm_id, uint8_t physical_port_id, uint8_t allowed_mask);
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/**
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* Driver init / self-test demonstration.
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*/
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void gpio_driver_init(void);
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void gpio_driver_demo(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* UNIVERSALISOS_DRIVERS_GPIO_H */
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