Fábio Coutada
9540b0528c
Phase B (Core Device Support) — all drivers verified in QEMU: - Network: virtio-net cleanup, RTL8139, E1000, clause-22 MDIO PHY management, CAN bus, industrial protocols (Modbus/Profibus/EtherCAT), controller probe+dispatch - Block storage: RAM disk backend (write->read->verify PASSED), virtio-blk transport, backend dispatch, real MBR+GPT partition parsers, SD/eMMC command framework - GPIO: PL061 (verified), I2C: DesignWare (verified), SPI: PL022 (verified) Phase C (Advanced Features): - PCI: FULL PikeOS ARMv7 replica — transport-agnostic uos_pci_ops, config-address encoding, BAR sizing, capability walk, enumeration+bridge recursion, MSI/MSI-X - USB: PikeOS-style layered stack — usb.h contract, usb_core.cpp (enumeration state machine), usb_ehci.cpp (EHCI transport) - Display: FULL 1:1 PikeOS fbcon replica + copied font_8x16 Build foundation fixes: - Freestanding aeabi_runtime.cpp (__aeabi_uidiv/__aeabi_uldivmod) - PikeOS-style flat 4GB MMU section map + proper enable (unblocked device MMIO) - guest.h MAX_GUEST_IMAGE_SIZE 256MB->16MB (BSS was 259MB) - C/C++ linkage fixes, duplicate-virtio_net_init, MMIO access-size handling Phase D (PikeOS ARMv7 Microkernel Port): - D-1: Per-VM address spaces — cloned pgdirs, ASID-tagged TLB, 4K page walker, isolation PASSED (two guests, same VA->different PAs), guest fault recovery - D-2: IRQ dispatch backbone — 1024-slot dispatch table, real GICv2 hardware (GICD_CTLR/GICC_CTLR/GICC_PMR/GICC_IAR/GICC_EOIR), arm_irq_handler wired - D-3: Time subsystem — CNTVCT ns-since-boot, CNTP periodic ticker via D-2 - D-4: KDEV framework — linker-section driver registration, uos_kdev_init_all, name lookup - D-5: VFP/NEON — lazy enable (undef trap->CPACR+FPEXC.EN), FPEXC=0x40000000 - D-6: SMP — per-CPU state, MPIDR, IPI/SGI framework (reschedule+TLB flush) All uos_ naming (PikeOS p4_ convention adapted). Compiles -Werror freestanding C++17. Co-Authored-By: Claude <noreply@anthropic.com>
84 lines
2.5 KiB
C
84 lines
2.5 KiB
C
/*
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* Universalisos I2C Master Driver
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* Phase B Priority 6: Platform I/O - Inter-IC bus
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*
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* Synopsys DesignWare I2C controller, as emulated by QEMU. Provides master
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* write, read, and combined write-then-read transfers plus bus scanning.
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*
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* Author: PortugalFuturista Hypervisor Development Team
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*/
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#ifndef UNIVERSALISOS_DRIVERS_I2C_H
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#define UNIVERSALISOS_DRIVERS_I2C_H
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#include <stdint.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** I2C standard speeds */
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#define I2C_SPEED_STANDARD 100000U /* 100 kHz */
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#define I2C_SPEED_FAST 400000U /* 400 kHz */
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#define I2C_SPEED_FAST_PLUS 1000000U /* 1 MHz */
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/** Maximum controllers and transfer sizes */
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#define MAX_I2C_CONTROLLERS 4
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#define I2C_MAX_TRANSFER 256
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/**
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* Initialize a DesignWare I2C controller.
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* @param controller_id Logical controller index
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* @param base_address MMIO base
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* @param speed_hz Bus speed in Hz (I2C_SPEED_*)
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* @return 0 on success, negative on error
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*/
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int i2c_init(uint8_t controller_id, uint32_t base_address, uint32_t speed_hz);
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/**
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* Master write: send `length` bytes from `data` to 7-bit `slave_address`.
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* @return number of bytes written, negative on error
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*/
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int i2c_master_write(uint8_t controller_id, uint8_t slave_address,
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const uint8_t* data, uint16_t length);
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/**
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* Master read: receive `length` bytes into `data` from 7-bit `slave_address`.
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* @return number of bytes read, negative on error
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*/
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int i2c_master_read(uint8_t controller_id, uint8_t slave_address,
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uint8_t* data, uint16_t length);
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/**
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* Combined transfer: write `write_len` bytes (register select), then issue a
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* repeated-start and read `read_len` bytes. Standard register-read pattern.
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* @return number of bytes read, negative on error
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*/
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int i2c_master_write_read(uint8_t controller_id, uint8_t slave_address,
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const uint8_t* write_data, uint16_t write_len,
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uint8_t* read_data, uint16_t read_len);
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/**
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* Probe the bus for an ACKing device at `slave_address` (7-bit).
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* @return true if a device responds, false otherwise
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*/
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bool i2c_probe_device(uint8_t controller_id, uint8_t slave_address);
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/**
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* Scan the full 7-bit address range and log discovered devices.
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*/
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void i2c_scan_bus(uint8_t controller_id);
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/** Controller interrupt handler (wired by the GIC dispatch). */
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void i2c_interrupt_handler(uint8_t controller_id);
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/** Driver init / self-test. */
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void i2c_driver_init(void);
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void i2c_driver_demo(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* UNIVERSALISOS_DRIVERS_I2C_H */
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