Fábio Coutada
9540b0528c
Phase B (Core Device Support) — all drivers verified in QEMU: - Network: virtio-net cleanup, RTL8139, E1000, clause-22 MDIO PHY management, CAN bus, industrial protocols (Modbus/Profibus/EtherCAT), controller probe+dispatch - Block storage: RAM disk backend (write->read->verify PASSED), virtio-blk transport, backend dispatch, real MBR+GPT partition parsers, SD/eMMC command framework - GPIO: PL061 (verified), I2C: DesignWare (verified), SPI: PL022 (verified) Phase C (Advanced Features): - PCI: FULL PikeOS ARMv7 replica — transport-agnostic uos_pci_ops, config-address encoding, BAR sizing, capability walk, enumeration+bridge recursion, MSI/MSI-X - USB: PikeOS-style layered stack — usb.h contract, usb_core.cpp (enumeration state machine), usb_ehci.cpp (EHCI transport) - Display: FULL 1:1 PikeOS fbcon replica + copied font_8x16 Build foundation fixes: - Freestanding aeabi_runtime.cpp (__aeabi_uidiv/__aeabi_uldivmod) - PikeOS-style flat 4GB MMU section map + proper enable (unblocked device MMIO) - guest.h MAX_GUEST_IMAGE_SIZE 256MB->16MB (BSS was 259MB) - C/C++ linkage fixes, duplicate-virtio_net_init, MMIO access-size handling Phase D (PikeOS ARMv7 Microkernel Port): - D-1: Per-VM address spaces — cloned pgdirs, ASID-tagged TLB, 4K page walker, isolation PASSED (two guests, same VA->different PAs), guest fault recovery - D-2: IRQ dispatch backbone — 1024-slot dispatch table, real GICv2 hardware (GICD_CTLR/GICC_CTLR/GICC_PMR/GICC_IAR/GICC_EOIR), arm_irq_handler wired - D-3: Time subsystem — CNTVCT ns-since-boot, CNTP periodic ticker via D-2 - D-4: KDEV framework — linker-section driver registration, uos_kdev_init_all, name lookup - D-5: VFP/NEON — lazy enable (undef trap->CPACR+FPEXC.EN), FPEXC=0x40000000 - D-6: SMP — per-CPU state, MPIDR, IPI/SGI framework (reschedule+TLB flush) All uos_ naming (PikeOS p4_ convention adapted). Compiles -Werror freestanding C++17. Co-Authored-By: Claude <noreply@anthropic.com>
281 lines
12 KiB
C
281 lines
12 KiB
C
/*
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* Universalisos PCI/PCIe Stack — full PikeOS-architecture replica
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*
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* Faithful adaptation of the PikeOS ARMv7 PCI driver
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* (src/target/arm/v7hf: p4pci.h, p4pci_types.h, p4pcidev.h, pci_common.c,
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* pci_enum.c, pci_msi.c, pci_msix.c) into the Universalisos freestanding kernel,
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* using the `uos_` naming convention instead of PikeOS's `p4_`.
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*
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* PikeOS philosophy: the PCI core is TRANSPORT-AGNOSTIC. All hardware-specific
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* config-space access goes through a pluggable `uos_pci_ops_t` callback table.
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* One transport variant (e.g. ECAM, Layerscape DBI+ATU) registers its ops at
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* boot; the shared core then enumerates, sizes BARs, walks capabilities, and
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* programs MSI/MSI-X for every device, independent of how config cycles are
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* produced. This file is the public contract.
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*
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* Author: PortugalFuturista Hypervisor Development Team
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*/
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#ifndef UNIVERSALISOS_DRIVERS_PCI_H
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#define UNIVERSALISOS_DRIVERS_PCI_H
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#include <stdint.h>
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#include <stdbool.h>
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#include <stddef.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ==========================================================================
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* Config-address encoding (PikeOS P4_pci_config_addr_t)
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*
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* A single 32-bit word packing domain/bus/dev/func; the low 8 bits hold the
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* register offset when the word is used as a transaction address.
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* domain [31:24] bus [23:16] dev [15:11] func [10:8] regoff [7:0]
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* ========================================================================== */
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typedef uint32_t uos_pci_config_addr_t;
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#define UOS_PCI_DOM_MAX 16u
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#define UOS_PCI_BUS_MAX 256u
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#define UOS_PCI_DEV_MAX 32u
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#define UOS_PCI_FN_MAX 8u
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#define UOS_PCI_REG_MAX 4096u
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#define UOS_PCI_CONFIG_ADDR(dom, bus, dev, fn) \
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((((uint32_t)(dom) << 24) & 0x0F000000u) | \
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(((uint32_t)(bus) << 16) & 0x00FF0000u) | \
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(((uint32_t)(dev) << 11) & 0x0000F800u) | \
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(((uint32_t)(fn) << 8) & 0x00000700u))
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#define UOS_PCI_CONFIG_DOM(a) (((a) & 0x0F000000u) >> 24)
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#define UOS_PCI_CONFIG_BUS(a) (((a) & 0x00FF0000u) >> 16)
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#define UOS_PCI_CONFIG_DEV(a) (((a) & 0x0000F800u) >> 11)
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#define UOS_PCI_CONFIG_FN(a) (((a) & 0x00000700u) >> 8)
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/* ==========================================================================
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* Config register offsets (Type-0 endpoint header)
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* ========================================================================== */
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#define UOS_PCI_R_VENDOR_ID 0x00u
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#define UOS_PCI_R_DEVICE_ID 0x02u
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#define UOS_PCI_R_COMMAND 0x04u
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#define UOS_PCI_R_STATUS 0x06u
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#define UOS_PCI_R_CLASS_REV 0x08u
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#define UOS_PCI_R_CACHE_LN_SZ 0x0cu
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#define UOS_PCI_R_PRM_LAT_TMR 0x0du
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#define UOS_PCI_R_HDR_TYPE 0x0eu
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#define UOS_PCI_R_BIST 0x0fu
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#define UOS_PCI_R_BAR_0 0x10u
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#define UOS_PCI_R_BAR_1 0x14u
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#define UOS_PCI_R_BAR_2 0x18u
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#define UOS_PCI_R_BAR_3 0x1cu
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#define UOS_PCI_R_BAR_4 0x20u
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#define UOS_PCI_R_BAR_5 0x24u
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#define UOS_PCI_R_CARDBUS_CIS_PTR 0x28u
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#define UOS_PCI_R_SUBSYS_VENDOR_ID 0x2cu
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#define UOS_PCI_R_SUBSYS_ID 0x2eu
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#define UOS_PCI_R_ROM_BAR_HDR0 0x30u
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#define UOS_PCI_R_CAP_PTR 0x34u
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#define UOS_PCI_R_ROM_BAR_HDR1 0x38u
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#define UOS_PCI_R_INT_LINE 0x3cu
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#define UOS_PCI_R_INT_PIN 0x3du
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/* Type-1 (bridge) header offsets */
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#define UOS_PCI_R_PRIMARY_BUS 0x18u
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#define UOS_PCI_R_SECONDARY_BUS 0x19u
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#define UOS_PCI_R_SUBORDINATE_BUS 0x1au
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#define UOS_PCI_R_SEC_LAT_TMR 0x1bu
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#define UOS_PCI_R_IO_BASE 0x1cu
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#define UOS_PCI_R_IO_LIMIT 0x1du
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#define UOS_PCI_R_SEC_STATUS 0x1eu
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#define UOS_PCI_R_MEM_BASE 0x20u
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#define UOS_PCI_R_MEM_LIMIT 0x22u
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#define UOS_PCI_R_PREF_MEM_BASE 0x24u
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#define UOS_PCI_R_PREF_MEM_LIMIT 0x26u
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#define UOS_PCI_R_PREF_BASE_UPPER32 0x28u
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#define UOS_PCI_R_PREF_LIMIT_UPPER32 0x2cu
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#define UOS_PCI_R_IO_BASE_UPPER16 0x30u
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#define UOS_PCI_R_IO_LIMIT_UPPER16 0x32u
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#define UOS_PCI_R_BRIDGE_CNTRL 0x3eu
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/* Header type values */
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#define UOS_PCI_HDR_TYPE_MASK 0x7Fu
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#define UOS_PCI_HDR_TYPE_NORMAL 0u
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#define UOS_PCI_HDR_TYPE_BRIDGE 1u
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#define UOS_PCI_HDR_TYPE_CARDBUS 2u
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#define UOS_PCI_HDR_TYPE_MULTIFUNC 0x80u
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/* BAR decoding masks */
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#define UOS_PCI_BAR_SPACE_MASK 0x01u
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#define UOS_PCI_BAR_SPACE_IO 0x01u
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#define UOS_PCI_BAR_SPACE_MEM 0x00u
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#define UOS_PCI_BAR_MEM_TYPE_MASK 0x06u
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#define UOS_PCI_BAR_MEM_TYPE_32 0x00u
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#define UOS_PCI_BAR_MEM_TYPE_64 0x04u
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#define UOS_PCI_BAR_MEM_PREF 0x08u
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#define UOS_PCI_BAR_MEM_MASK (~0x0fu)
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#define UOS_PCI_BAR_IO_MASK (~0x03u)
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#define UOS_PCI_ROM_ADDR_MASK (~0x7ffu)
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/* COMMAND bits */
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#define UOS_PCI_CMD_IO 0x0001u
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#define UOS_PCI_CMD_MEM 0x0002u
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#define UOS_PCI_CMD_MASTER 0x0004u
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#define UOS_PCI_CMD_SERR 0x0100u
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#define UOS_PCI_CMD_INT_DIS 0x0400u
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/* STATUS bits */
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#define UOS_PCI_STATUS_CAP 0x0010u
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/* Capability IDs */
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#define UOS_PCI_CAP_ID_PM 0x01u
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#define UOS_PCI_CAP_ID_AGP 0x02u
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#define UOS_PCI_CAP_ID_MSI 0x05u
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#define UOS_PCI_CAP_ID_PCIX 0x07u
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#define UOS_PCI_CAP_ID_EXP 0x10u /* PCI Express */
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#define UOS_PCI_CAP_ID_MSIX 0x11u
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#define UOS_PCI_CAP_LIST_ID 0x00u /* cap entry: ID byte */
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#define UOS_PCI_CAP_LIST_NEXT 0x01u /* cap entry: next-ptr byte */
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/* MSI capability register field bits (Message Control) */
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#define UOS_PCI_MSI_CNTL_ENABLE 0x0001u
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#define UOS_PCI_MSI_CNTL_MULTICA 0x000eu /* [3:1] multiple message capable */
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#define UOS_PCI_MSI_CNTL_MULTIEN 0x0070u /* [6:4] multiple message enable */
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#define UOS_PCI_MSI_CNTL_64BIT 0x0080u /* 64-bit address capable */
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#define UOS_PCI_MSI_CNTL_VECMASK 0x0100u /* per-vector mask capable */
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/* MSI-X capability Message Control bits */
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#define UOS_PCI_MSIX_CNTL_ENABLE 0x8000u
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#define UOS_PCI_MSIX_CNTL_FNMASK 0x4000u
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#define UOS_PCI_MSIX_CNTL_TABLESZ 0x07ffu /* table size field (N-1) */
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/* MSI-X table entry layout (16 bytes each) */
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#define UOS_PCI_MSIX_ENTRY_SIZE 16u
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#define UOS_PCI_MSIX_ADDRLO_OFFSET 0x00u
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#define UOS_PCI_MSIX_ADDRHI_OFFSET 0x04u
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#define UOS_PCI_MSIX_DATA_OFFSET 0x08u
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#define UOS_PCI_MSIX_MASK_OFFSET 0x0cu /* bit 0 = per-entry Mask */
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/* ==========================================================================
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* Data structures (PikeOS P4_pci_res_t / P4_pci_dev_t)
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* ========================================================================== */
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#define UOS_PCI_NUM_RES 7u /* 6 standard BARs + expansion ROM */
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/* Resource flags */
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#define UOS_PCI_RES_MEM_32 0x00000001u
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#define UOS_PCI_RES_MEM_64 0x00000002u
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#define UOS_PCI_RES_IO 0x00000004u
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#define UOS_PCI_RES_PREF 0x00000008u
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/* Device open state (simple lock, no refcount, as in PikeOS) */
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#define UOS_PCI_DEV_CLOSED 0u
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#define UOS_PCI_DEV_OPEN 1u
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typedef struct {
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uint64_t bus_addr; /* address as seen on the PCI bus */
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uint64_t cpu_addr; /* address as seen by the CPU (after ATU) */
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uint32_t size; /* size in bytes */
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uint32_t flags; /* UOS_PCI_RES_* OR'd */
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uint32_t r_normal; /* original BAR value (for BAR-size virtualization) */
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uint32_t r_sized; /* all-1s-probe readback */
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} uos_pci_res_t;
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typedef struct {
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uos_pci_res_t res[UOS_PCI_NUM_RES];
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bool force_intx_dis;
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bool ext_pci_cfg;
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int32_t irq; /* INTID, -1 = invalid */
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uos_pci_config_addr_t config_addr; /* packed domain/bus/dev/func */
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uint32_t class_code; /* class<<8 (no rev in low byte) */
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uint16_t vendor;
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uint16_t device;
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uint16_t subsysvendor;
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uint16_t subsys;
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uint8_t hdr_type; /* low 7 bits */
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uint8_t state; /* UOS_PCI_DEV_* */
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/* MSI/MSI-X probe results */
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uint8_t msi_cap; /* MSI cap offset, 0 if none */
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uint8_t msix_cap; /* MSI-X cap offset, 0 if none */
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uint16_t msi_control; /* cached Message Control */
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uint16_t msix_control; /* cached MSI-X Message Control */
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uint8_t msi_is64;
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uint8_t msi_max_irqs;
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uint8_t msix_table_bar; /* which res[] holds the MSI-X table */
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uint32_t msix_table_offset;
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} uos_pci_dev_t;
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/* ==========================================================================
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* Transport contract — the pluggable `pci_ops` (PikeOS philosophy)
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*
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* A board port implements these and registers them via uos_pci_register_ops().
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* The core never touches config space directly except through these callbacks.
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* ========================================================================== */
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typedef struct {
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void (*read_config8) (uos_pci_config_addr_t addr, uint32_t offset, uint8_t *val);
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void (*read_config16)(uos_pci_config_addr_t addr, uint32_t offset, uint16_t *val);
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void (*read_config32)(uos_pci_config_addr_t addr, uint32_t offset, uint32_t *val);
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void (*write_config8) (uos_pci_config_addr_t addr, uint32_t offset, uint8_t val);
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void (*write_config16)(uos_pci_config_addr_t addr, uint32_t offset, uint16_t val);
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void (*write_config32)(uos_pci_config_addr_t addr, uint32_t offset, uint32_t val);
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void (*find_irq) (uos_pci_dev_t *dev, uint8_t pin); /* sets dev->irq */
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void (*arch_quirk_post)(uos_pci_dev_t *dev); /* per-device hook */
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void (*set_cpu_addr) (uos_pci_dev_t *dev); /* map bus->cpu addr */
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unsigned int (*num_domains)(void);
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} uos_pci_ops_t;
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/* ==========================================================================
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* Public core API
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* ========================================================================== */
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#define UOS_PCI_MAX_DEVICES 128u
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/** Register a transport. The core uses the last registered ops. */
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void uos_pci_register_ops(const uos_pci_ops_t *ops);
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/** Convenience config accessors that dispatch through the registered ops. */
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uint8_t uos_pci_read8 (uos_pci_config_addr_t a, uint32_t off);
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uint16_t uos_pci_read16(uos_pci_config_addr_t a, uint32_t off);
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uint32_t uos_pci_read32(uos_pci_config_addr_t a, uint32_t off);
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void uos_pci_write8 (uos_pci_config_addr_t a, uint32_t off, uint8_t v);
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void uos_pci_write16(uos_pci_config_addr_t a, uint32_t off, uint16_t v);
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void uos_pci_write32(uos_pci_config_addr_t a, uint32_t off, uint32_t v);
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/** Walk the capability list, return the cap offset for `id`, or 0 if absent. */
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uint8_t uos_pci_find_cap(uos_pci_dev_t *dev, uint8_t id);
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/** Canonical BAR-sizing probe (PikeOS pci_read_bases). Sizes all BARs + ROM. */
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void uos_pci_read_bases(uos_pci_dev_t *dev, uint32_t num_bars, uint32_t rom_off);
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/** Enumerate the whole hierarchy from bus 0 (bridge recursion, BAR sizing). */
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int uos_pci_enumerate(void);
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/** Device table access. */
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uos_pci_dev_t *uos_pci_get_device(unsigned int index);
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unsigned int uos_pci_get_device_count(void);
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/** Enable a device: set I/O + memory + bus-master in COMMAND. */
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void uos_pci_enable_device(uos_pci_dev_t *dev);
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/** MSI / MSI-X programming (no-op if the device lacks the capability). */
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void uos_pci_msi_enable (uos_pci_dev_t *dev, uint32_t msg_addr, uint16_t msg_data);
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void uos_pci_msi_disable(uos_pci_dev_t *dev);
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void uos_pci_msix_enable (uos_pci_dev_t *dev); /* enables + unmasks all entries */
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void uos_pci_msix_disable(uos_pci_dev_t *dev);
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/** Init + demonstration. */
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void uos_pci_driver_init(void);
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void uos_pci_driver_demo(void);
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/* Legacy simple API (kept for the existing kernel boot wiring). */
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#define MAX_PCI_DEVICES UOS_PCI_MAX_DEVICES
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#define QEMU_VIRT_PCI_ECAM_BASE 0x3F000000u
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int pci_init(uint32_t ecam_base);
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void pci_driver_init(void);
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void pci_driver_demo(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* UNIVERSALISOS_DRIVERS_PCI_H */
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