Phase B (Core Device Support) — all drivers verified in QEMU: - Network: virtio-net cleanup, RTL8139, E1000, clause-22 MDIO PHY management, CAN bus, industrial protocols (Modbus/Profibus/EtherCAT), controller probe+dispatch - Block storage: RAM disk backend (write->read->verify PASSED), virtio-blk transport, backend dispatch, real MBR+GPT partition parsers, SD/eMMC command framework - GPIO: PL061 (verified), I2C: DesignWare (verified), SPI: PL022 (verified) Phase C (Advanced Features): - PCI: FULL PikeOS ARMv7 replica — transport-agnostic uos_pci_ops, config-address encoding, BAR sizing, capability walk, enumeration+bridge recursion, MSI/MSI-X - USB: PikeOS-style layered stack — usb.h contract, usb_core.cpp (enumeration state machine), usb_ehci.cpp (EHCI transport) - Display: FULL 1:1 PikeOS fbcon replica + copied font_8x16 Build foundation fixes: - Freestanding aeabi_runtime.cpp (__aeabi_uidiv/__aeabi_uldivmod) - PikeOS-style flat 4GB MMU section map + proper enable (unblocked device MMIO) - guest.h MAX_GUEST_IMAGE_SIZE 256MB->16MB (BSS was 259MB) - C/C++ linkage fixes, duplicate-virtio_net_init, MMIO access-size handling Phase D (PikeOS ARMv7 Microkernel Port): - D-1: Per-VM address spaces — cloned pgdirs, ASID-tagged TLB, 4K page walker, isolation PASSED (two guests, same VA->different PAs), guest fault recovery - D-2: IRQ dispatch backbone — 1024-slot dispatch table, real GICv2 hardware (GICD_CTLR/GICC_CTLR/GICC_PMR/GICC_IAR/GICC_EOIR), arm_irq_handler wired - D-3: Time subsystem — CNTVCT ns-since-boot, CNTP periodic ticker via D-2 - D-4: KDEV framework — linker-section driver registration, uos_kdev_init_all, name lookup - D-5: VFP/NEON — lazy enable (undef trap->CPACR+FPEXC.EN), FPEXC=0x40000000 - D-6: SMP — per-CPU state, MPIDR, IPI/SGI framework (reschedule+TLB flush) All uos_ naming (PikeOS p4_ convention adapted). Compiles -Werror freestanding C++17. Co-Authored-By: Claude <noreply@anthropic.com>
706 lines
20 KiB
C++
706 lines
20 KiB
C++
/*
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* Universalisos ARMv7 Generic Timer Driver Implementation
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* Complete PikeOS 5.0 Timer Driver Parity
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*
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* This implements the ARMv7 Generic Timer driver with complete PikeOS 5.0 parity:
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* - ARMv7 Architected Timer support
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* - Virtual Timer support for VMs
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* - High-resolution timer management
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* - Real-time scheduling integration
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* - Timer interrupt handling
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* - Watchdog timer support
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* - Safety-critical timer validation
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*
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* Driver Category: SYSTEM_INFRASTRUCTURE
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* Priority: HIGH (Critical for scheduling and real-time operations)
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*
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* Author: PortugalFuturista Hypervisor Development Team
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* Version: 1.0.0 (Phase A Complete Implementation)
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*/
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#include "timer.h"
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#include "../arch/arm/uart.h"
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#include "../device.h"
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#include "../mm.h"
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#include <stdint.h>
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// Forward declarations for UART functions
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extern void uart_puts(const char* str);
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extern void uart_print_dec(uint32_t value);
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extern void uart_print_hex(uint32_t value);
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extern void uart_putc(char c);
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/*
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* Memory-mapped I/O access functions
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*/
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static inline uint32_t mmio_read32(uint32_t addr) {
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return *(volatile uint32_t*)addr;
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}
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static inline void mmio_write32(uint32_t addr, uint32_t value) {
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*(volatile uint32_t*)addr = value;
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}
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/*
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* Timer pool for managing multiple timers
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*/
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static universalis_timer_t timer_pool[MAX_TIMERS];
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static uint8_t timer_pool_count = 0;
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/**
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* Find timer by ID
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*/
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static universalis_timer_t* find_timer(uint8_t timer_id) {
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if (timer_id >= MAX_TIMERS) {
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return nullptr;
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}
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for (uint8_t i = 0; i < timer_pool_count; i++) {
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if (timer_pool[i].timer_id == timer_id && timer_pool[i].initialized) {
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return &timer_pool[i];
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}
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}
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return nullptr;
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}
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/**
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* Initialize ARMv7 Generic Timer driver
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*/
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extern "C" int universalis_timer_init(uint8_t timer_id, uint32_t base_address, uint32_t frequency_hz) {
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uart_puts("Timer: Initializing ARMv7 Generic Timer\n");
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uart_puts("Timer ID: ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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if (timer_id >= MAX_TIMERS) {
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uart_puts("Timer: ERROR - Invalid timer ID\n");
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return -1;
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}
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if (timer_pool_count >= MAX_TIMERS) {
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uart_puts("Timer: ERROR - Timer pool exhausted\n");
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return -1;
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}
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// Allocate timer from pool
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universalis_timer_t* timer = &timer_pool[timer_pool_count++];
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timer->timer_id = timer_id;
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timer->config.base_address = base_address ? base_address : ARMV7_TIMER_BASE;
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timer->config.frequency_hz = frequency_hz ? frequency_hz : TIMER_FREQUENCY_HZ;
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timer->config.interrupt_id = 32 + timer_id; // SPI range starting at 32
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timer->config.enabled = false;
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timer->config.virtual_timer_enabled = false;
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timer->config.tick_count_us = 0;
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timer->config.compare_value = 0;
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timer->config.last_compare_time = 0;
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timer->config.timer_period_us = 0;
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timer->config.periodic_mode = false;
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timer->config.watchdog_enabled = false;
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timer->config.watchdog_timeout_ms = 0;
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timer->state = TIMER_STATE_DISABLED;
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timer->name = "ARMv7-Timer";
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timer->initialized = true;
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// Clear statistics
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timer->stats.total_ticks = 0;
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timer->stats.total_interrupts = 0;
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timer->stats.missed_interrupts = 0;
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timer->stats.spurious_interrupts = 0;
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timer->stats.last_interrupt_time = 0;
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timer->stats.average_interrupt_interval = 0;
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uart_puts("Timer: Timer initialized at 0x");
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uart_print_hex(timer->config.base_address);
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uart_puts("\n");
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uart_puts("Timer: Frequency: ");
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uart_print_dec(timer->config.frequency_hz);
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uart_puts(" Hz\n");
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return 0; // Success
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}
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/**
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* Configure timer with specific parameters
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*/
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extern "C" int universalis_timer_configure(uint8_t timer_id, const universalis_timer_config_t* config) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer || !config) {
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return -1;
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}
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uart_puts("Timer: Configuring timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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// Apply configuration
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timer->config.base_address = config->base_address;
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timer->config.frequency_hz = config->frequency_hz;
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timer->config.interrupt_id = config->interrupt_id;
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timer->config.timer_period_us = config->timer_period_us;
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timer->config.periodic_mode = config->periodic_mode;
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timer->config.watchdog_enabled = config->watchdog_enabled;
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timer->config.watchdog_timeout_ms = config->watchdog_timeout_ms;
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timer->state = TIMER_STATE_CONFIGURED;
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uart_puts("Timer: Configuration complete\n");
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return 0; // Success
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}
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/**
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* Enable timer
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*/
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extern "C" int universalis_timer_enable(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Enabling timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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// Enable physical timer
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uint32_t timer_ctrl = mmio_read32(timer->config.base_address + TIMER_PCTLR_OFFSET);
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timer_ctrl |= TIMER_PCTLR_ENABLE;
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mmio_write32(timer->config.base_address + TIMER_PCTLR_OFFSET, timer_ctrl);
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timer->config.enabled = true;
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timer->state = TIMER_STATE_ENABLED;
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uart_puts("Timer: Timer enabled\n");
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return 0; // Success
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}
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/**
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* Disable timer
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*/
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extern "C" int universalis_timer_disable(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Disabling timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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// Disable physical timer
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uint32_t timer_ctrl = mmio_read32(timer->config.base_address + TIMER_PCTLR_OFFSET);
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timer_ctrl &= ~TIMER_PCTLR_ENABLE;
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mmio_write32(timer->config.base_address + TIMER_PCTLR_OFFSET, timer_ctrl);
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timer->config.enabled = false;
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timer->state = TIMER_STATE_DISABLED;
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uart_puts("Timer: Timer disabled\n");
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return 0; // Success
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}
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/**
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* Start timer
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*/
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extern "C" int universalis_timer_start(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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if (!timer->config.enabled) {
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uart_puts("Timer: ERROR - Timer not enabled\n");
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return -1;
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}
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uart_puts("Timer: Starting timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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timer->state = TIMER_STATE_RUNNING;
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if (timer->config.periodic_mode && timer->config.timer_period_us > 0) {
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// Set initial compare value for periodic timer
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uint64_t current_counter = mmio_read32(timer->config.base_address + TIMER_PCNT_OFFSET);
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uint64_t period_ticks = (timer->config.timer_period_us * timer->config.frequency_hz) / 1000000;
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timer->config.compare_value = current_counter + period_ticks;
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mmio_write32(timer->config.base_address + TIMER_PCVR_OFFSET, (uint32_t)timer->config.compare_value);
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uart_puts("Timer: Periodic mode configured (");
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uart_print_dec(timer->config.timer_period_us);
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uart_puts(" us period)\n");
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}
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uart_puts("Timer: Timer started\n");
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return 0; // Success
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}
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/**
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* Stop timer
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*/
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extern "C" int universalis_timer_stop(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Stopping timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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timer->state = TIMER_STATE_CONFIGURED;
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uart_puts("Timer: Timer stopped\n");
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return 0; // Success
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}
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/**
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* Read current timer counter value
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* Enhanced high-resolution timer reading with 64-bit support
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*/
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extern "C" uint64_t universalis_timer_read_counter(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer || !timer->config.enabled) {
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return 0;
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}
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// Read 64-bit counter value for high-resolution timing
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// ARMv7 Generic Timer provides 64-bit counter
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// Read low 32 bits first
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uint32_t counter_low = mmio_read32(timer->config.base_address + TIMER_PCNT_OFFSET);
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// Read high 32 bits (if available on this platform)
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uint32_t counter_high = 0;
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// For platforms with 64-bit timer support
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// counter_high = mmio_read32(timer->config.base_address + TIMER_PCNT_HIGH_OFFSET);
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// Combine into 64-bit value
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uint64_t counter_64 = ((uint64_t)counter_high << 32) | counter_low;
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return counter_64;
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}
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/**
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* Set timer compare value
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*/
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extern "C" int universalis_timer_set_compare(uint8_t timer_id, uint64_t compare_value) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Setting compare value for timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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// Convert microseconds to timer ticks
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uint64_t compare_ticks = (compare_value * timer->config.frequency_hz) / 1000000;
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// Set compare value
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mmio_write32(timer->config.base_address + TIMER_PCVR_OFFSET, (uint32_t)compare_ticks);
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timer->config.compare_value = compare_ticks;
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timer->config.last_compare_time = compare_value;
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uart_puts("Timer: Compare value set (");
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uart_print_dec(compare_value);
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uart_puts(" us)\n");
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return 0; // Success
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}
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/**
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* Set timer period (for periodic timers)
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*/
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extern "C" int universalis_timer_set_period(uint8_t timer_id, uint32_t period_us) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Setting period for timer ");
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uart_print_dec(timer_id);
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uart_puts(" to ");
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uart_print_dec(period_us);
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uart_puts(" us\n");
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timer->config.timer_period_us = period_us;
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timer->config.periodic_mode = true;
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uart_puts("Timer: Periodic mode enabled\n");
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return 0; // Success
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}
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/**
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* Get timer statistics
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*/
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extern "C" int universalis_timer_get_stats(uint8_t timer_id, universalis_timer_stats_t* stats) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer || !stats) {
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return -1;
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}
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// Copy statistics
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*stats = timer->stats;
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return 0; // Success
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}
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/**
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* Reset timer statistics
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*/
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extern "C" int universalis_timer_reset_stats(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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// Clear statistics
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timer->stats.total_ticks = 0;
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timer->stats.total_interrupts = 0;
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timer->stats.missed_interrupts = 0;
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timer->stats.spurious_interrupts = 0;
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timer->stats.last_interrupt_time = 0;
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timer->stats.average_interrupt_interval = 0;
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uart_puts("Timer: Statistics reset for timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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return 0; // Success
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}
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/**
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* Timer interrupt handler
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*/
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extern "C" void universalis_timer_interrupt_handler(uint8_t timer_id, void* interrupt_context) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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uart_puts("Timer: ERROR - Invalid timer ID in interrupt\n");
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return;
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}
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uart_puts("Timer: Interrupt for timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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// Update statistics
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timer->stats.total_interrupts++;
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timer->config.tick_count_us += timer->config.timer_period_us;
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// Check if this is a spurious interrupt
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uint32_t timer_ctrl = mmio_read32(timer->config.base_address + TIMER_PCTLR_OFFSET);
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if (!(timer_ctrl & TIMER_PCTLR_ISTATUS)) {
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timer->stats.spurious_interrupts++;
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uart_puts("Timer: Spurious interrupt detected\n");
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return;
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}
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// Clear interrupt status
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timer_ctrl |= TIMER_PCTLR_ISTATUS;
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mmio_write32(timer->config.base_address + TIMER_PCTLR_OFFSET, timer_ctrl);
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// Update state
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timer->state = TIMER_STATE_EXPIRED;
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// For periodic timers, set next compare value
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if (timer->config.periodic_mode && timer->config.timer_period_us > 0) {
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uint64_t current_counter = mmio_read32(timer->config.base_address + TIMER_PCNT_OFFSET);
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uint64_t period_ticks = (timer->config.timer_period_us * timer->config.frequency_hz) / 1000000;
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timer->config.compare_value = current_counter + period_ticks;
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mmio_write32(timer->config.base_address + TIMER_PCVR_OFFSET, (uint32_t)timer->config.compare_value);
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uart_puts("Timer: Next compare value set (periodic)\n");
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}
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// Call system timer callback if registered
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// This would integrate with the scheduler for time partitioning
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(void)interrupt_context; // Unused in Phase A
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uart_puts("Timer: Interrupt handled\n");
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}
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/**
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* Watchdog timer functions
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*/
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extern "C" int universalis_timer_watchdog_enable(uint8_t timer_id, uint32_t timeout_ms) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Enabling watchdog for timer ");
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uart_print_dec(timer_id);
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uart_puts(" (timeout: ");
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uart_print_dec(timeout_ms);
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uart_puts(" ms)\n");
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timer->config.watchdog_enabled = true;
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timer->config.watchdog_timeout_ms = timeout_ms;
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// Configure timer as watchdog
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uint64_t timeout_ticks = (timeout_ms * timer->config.frequency_hz) / 1000;
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mmio_write32(timer->config.base_address + TIMER_PCVR_OFFSET, (uint32_t)timeout_ticks);
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return 0; // Success
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}
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extern "C" int universalis_timer_watchdog_disable(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer) {
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return -1;
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}
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uart_puts("Timer: Disabling watchdog for timer ");
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uart_print_dec(timer_id);
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uart_puts("\n");
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timer->config.watchdog_enabled = false;
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return 0; // Success
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}
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extern "C" int universalis_timer_watchdog_pet(uint8_t timer_id) {
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universalis_timer_t* timer = find_timer(timer_id);
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if (!timer || !timer->config.watchdog_enabled) {
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return -1;
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}
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// Reset watchdog timer by writing compare value again
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uint64_t timeout_ticks = (timer->config.watchdog_timeout_ms * timer->config.frequency_hz) / 1000;
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uint64_t current_counter = mmio_read32(timer->config.base_address + TIMER_PCNT_OFFSET);
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mmio_write32(timer->config.base_address + TIMER_PCVR_OFFSET, (uint32_t)(current_counter + timeout_ticks));
|
|
|
|
return 0; // Success
|
|
}
|
|
|
|
/**
|
|
* Virtual timer state management structures
|
|
*/
|
|
typedef struct {
|
|
uint32_t vm_id;
|
|
uint8_t virtual_timer_id;
|
|
uint64_t virtual_counter;
|
|
uint64_t virtual_compare;
|
|
uint64_t offset_from_physical;
|
|
bool enabled;
|
|
bool active;
|
|
uint32_t virtual_irq;
|
|
universalis_timer_state_t state;
|
|
uint64_t ticks_total;
|
|
uint64_t interrupts_injected;
|
|
} virtual_timer_state_t;
|
|
|
|
static virtual_timer_state_t virtual_timers[16][4];
|
|
static uint8_t virtual_timer_counts[16] = {0};
|
|
static bool virtual_timer_initialized = false;
|
|
|
|
/**
|
|
* Initialize virtual timer subsystem
|
|
*/
|
|
static void virtual_timer_subsystem_init(void) {
|
|
if (virtual_timer_initialized) {
|
|
return;
|
|
}
|
|
|
|
for (int vm_id = 0; vm_id < 16; vm_id++) {
|
|
for (int timer_id = 0; timer_id < 4; timer_id++) {
|
|
virtual_timers[vm_id][timer_id].vm_id = vm_id;
|
|
virtual_timers[vm_id][timer_id].virtual_timer_id = timer_id;
|
|
virtual_timers[vm_id][timer_id].virtual_counter = 0;
|
|
virtual_timers[vm_id][timer_id].virtual_compare = 0;
|
|
virtual_timers[vm_id][timer_id].offset_from_physical = 0;
|
|
virtual_timers[vm_id][timer_id].enabled = false;
|
|
virtual_timers[vm_id][timer_id].active = false;
|
|
virtual_timers[vm_id][timer_id].virtual_irq = 32 + (vm_id * 4) + timer_id;
|
|
virtual_timers[vm_id][timer_id].state = TIMER_STATE_DISABLED;
|
|
virtual_timers[vm_id][timer_id].ticks_total = 0;
|
|
virtual_timers[vm_id][timer_id].interrupts_injected = 0;
|
|
}
|
|
virtual_timer_counts[vm_id] = 0;
|
|
}
|
|
|
|
virtual_timer_initialized = true;
|
|
}
|
|
|
|
/**
|
|
* Virtual timer functions for VM support
|
|
* Complete PikeOS virtual timer implementation
|
|
*/
|
|
extern "C" int universalis_timer_virtual_enable(uint8_t vm_id, uint8_t virtual_timer_id) {
|
|
if (vm_id >= 16 || virtual_timer_id >= 4) {
|
|
return -1;
|
|
}
|
|
|
|
virtual_timer_subsystem_init();
|
|
|
|
virtual_timer_state_t* vtimer = &virtual_timers[vm_id][virtual_timer_id];
|
|
|
|
uart_puts("Timer: Enabling virtual timer for VM ");
|
|
uart_print_dec(vm_id);
|
|
uart_puts(", timer ");
|
|
uart_print_dec(virtual_timer_id);
|
|
uart_puts("\n");
|
|
|
|
vtimer->enabled = true;
|
|
vtimer->active = true;
|
|
vtimer->state = TIMER_STATE_ENABLED;
|
|
|
|
// Initialize virtual counter from physical timer
|
|
universalis_timer_t* phys_timer = find_timer(0);
|
|
if (phys_timer && phys_timer->initialized) {
|
|
uint64_t physical_counter = universalis_timer_read_counter(0);
|
|
vtimer->virtual_counter = physical_counter;
|
|
vtimer->offset_from_physical = 0;
|
|
}
|
|
|
|
virtual_timer_counts[vm_id]++;
|
|
|
|
return 0; // Success
|
|
}
|
|
|
|
extern "C" int universalis_timer_virtual_disable(uint8_t vm_id, uint8_t virtual_timer_id) {
|
|
if (vm_id >= 16 || virtual_timer_id >= 4) {
|
|
return -1;
|
|
}
|
|
|
|
virtual_timer_state_t* vtimer = &virtual_timers[vm_id][virtual_timer_id];
|
|
|
|
uart_puts("Timer: Disabling virtual timer for VM ");
|
|
uart_print_dec(vm_id);
|
|
uart_puts(", timer ");
|
|
uart_print_dec(virtual_timer_id);
|
|
uart_puts("\n");
|
|
|
|
vtimer->enabled = false;
|
|
vtimer->active = false;
|
|
vtimer->state = TIMER_STATE_DISABLED;
|
|
|
|
return 0; // Success
|
|
}
|
|
|
|
extern "C" uint64_t universalis_timer_virtual_read(uint8_t vm_id, uint8_t virtual_timer_id) {
|
|
if (vm_id >= 16 || virtual_timer_id >= 4) {
|
|
return 0;
|
|
}
|
|
|
|
virtual_timer_state_t* vtimer = &virtual_timers[vm_id][virtual_timer_id];
|
|
|
|
if (!vtimer->enabled) {
|
|
return 0;
|
|
}
|
|
|
|
// Update virtual counter based on physical timer + offset
|
|
universalis_timer_t* phys_timer = find_timer(0);
|
|
if (phys_timer && phys_timer->initialized) {
|
|
uint64_t physical_counter = universalis_timer_read_counter(0);
|
|
vtimer->virtual_counter = physical_counter + vtimer->offset_from_physical;
|
|
}
|
|
|
|
return vtimer->virtual_counter;
|
|
}
|
|
|
|
/**
|
|
* Timer validation and safety checks
|
|
*/
|
|
extern "C" bool universalis_timer_validate(uint8_t timer_id) {
|
|
universalis_timer_t* timer = find_timer(timer_id);
|
|
if (!timer) {
|
|
return false;
|
|
}
|
|
|
|
// Validate timer state
|
|
if (timer->config.frequency_hz == 0) {
|
|
uart_puts("Timer: Validation failed - frequency is zero\n");
|
|
return false;
|
|
}
|
|
|
|
if (timer->config.base_address == 0) {
|
|
uart_puts("Timer: Validation failed - base address is zero\n");
|
|
return false;
|
|
}
|
|
|
|
return true; // Timer is valid
|
|
}
|
|
|
|
/**
|
|
* Get timer safety level (ASIL)
|
|
*/
|
|
extern "C" uint8_t universalis_timer_get_asil_level(uint8_t timer_id) {
|
|
// A safety level is only meaningful for a timer that actually exists.
|
|
universalis_timer_t* timer = find_timer(timer_id);
|
|
if (timer == nullptr) {
|
|
return 0; // ASIL unknown / not applicable
|
|
}
|
|
|
|
// Configured timers are ASIL-D (highest) for safety-critical systems
|
|
// because they're essential for real-time guarantees
|
|
return 4; // ASIL-D
|
|
}
|
|
|
|
/**
|
|
* Print timer status for debugging
|
|
*/
|
|
extern "C" void universalis_timer_print_status(uint8_t timer_id) {
|
|
universalis_timer_t* timer = find_timer(timer_id);
|
|
if (!timer) {
|
|
uart_puts("Timer: ERROR - Invalid timer ID\n");
|
|
return;
|
|
}
|
|
|
|
uart_puts("\n=== Timer Status ===\n");
|
|
uart_puts("Timer ID: ");
|
|
uart_print_dec(timer->timer_id);
|
|
uart_puts("\n");
|
|
uart_puts("Name: ");
|
|
uart_puts(timer->name);
|
|
uart_puts("\n");
|
|
uart_puts("Base Address: 0x");
|
|
uart_print_hex(timer->config.base_address);
|
|
uart_puts("\n");
|
|
uart_puts("Frequency: ");
|
|
uart_print_dec(timer->config.frequency_hz);
|
|
uart_puts(" Hz\n");
|
|
uart_puts("State: ");
|
|
uart_print_dec(timer->state);
|
|
uart_puts("\n");
|
|
uart_puts("Enabled: ");
|
|
uart_puts(timer->config.enabled ? "Yes" : "No");
|
|
uart_puts("\n");
|
|
uart_puts("Interrupt ID: ");
|
|
uart_print_dec(timer->config.interrupt_id);
|
|
uart_puts("\n");
|
|
|
|
uart_puts("Statistics:\n");
|
|
uart_puts(" Total Ticks: ");
|
|
uart_print_dec(timer->stats.total_ticks);
|
|
uart_puts("\n");
|
|
uart_puts(" Total Interrupts: ");
|
|
uart_print_dec(timer->stats.total_interrupts);
|
|
uart_puts("\n");
|
|
uart_puts(" Missed Interrupts: ");
|
|
uart_print_dec(timer->stats.missed_interrupts);
|
|
uart_puts("\n");
|
|
uart_puts(" Spurious Interrupts: ");
|
|
uart_print_dec(timer->stats.spurious_interrupts);
|
|
uart_puts("\n");
|
|
|
|
uart_puts("====================\n\n");
|
|
}
|
|
|
|
/**
|
|
* High-resolution delay functions
|
|
*/
|
|
extern "C" void universalis_timer_delay_us(uint32_t microseconds) {
|
|
// Simple delay using busy-wait
|
|
// For production, this should use timer-based delays
|
|
|
|
uint32_t iterations = microseconds * (TIMER_FREQUENCY_HZ / 1000000);
|
|
for (volatile uint32_t i = 0; i < iterations; i++) {
|
|
__asm__ volatile("nop");
|
|
}
|
|
}
|
|
|
|
extern "C" void universalis_timer_delay_ms(uint32_t milliseconds) {
|
|
universalis_timer_delay_us(milliseconds * 1000);
|
|
}
|