replica-omnisciente/sessions/2026-07-10_replan-mycelium-universalisos/PARITY.md

Universalisos ↔ PikeOS 5.0 / Bao — Parity Backlog (verified)

Created: 2026-07-10 (synthesis of in-repo analyses, reconciled with verified ground truth) Author: Kimi (root agent, replica-omnisciente) Scope: /home/fabiorafaelcoutada/portugalfuturista/universalisos Supersedes: the per-doc verdicts where they are stale or mutually contradictory (see §6).

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0. How to read this

• Two reference targets, two different parity axes:
  • PikeOS 5.0 — the RTOS/partition/API/safety axis (ARINC 653 partitions, IPC, HM, personalities, syscalls, system-software layer).
  • Bao — the ARMv8/RISC-V hardware-virtualization axis (Stage-2 MMU, GICv3 VGIC, vCPU world-switch, static partitioning). Bao is the right model for the AArch64 track, not the x86 VMX/EPT/VMCS vocabulary that some older analyses use.
• Status key: ✅ done (verified) · 🟡 partial / framework · ❌ missing · — not applicable.
• Rows marked (V) are verified by build+QEMU this session; others are doc-derived and flagged.

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1. Verified ground-truth snapshot (2026-07-10) — supersedes stale docs

Track	Verified state	Supersedes
ARMv7 / qemu-arm-virt	Boots, full demo end-to-end (scheduler, ARINC sampling/queuing/shmem IPC, 3-tier HM, PV ABI, preempt A/B). 0 linker warnings. BSS 20.5 MB → 3.6 MB.	status_report "MATURE" (still accurate)
AArch64 / qemu-aarch64-virt	MP0 COMPLETE. Builds (0 warnings), boots at EL2 (virtualization=on), LPAE S1, GICv3, CNTHP @100 Hz, PikeOS scheduler, preemptive ctx switch → interleaved A/B.	status_report "build broken / MP0 ~15%" (stale)
RISC-V / polarfire	Functional parallel track (own scheduler/VMM/hypercalls/Sv39). Not exercised this session.	status_report "FUNCTIONAL" (assumed current)
Tooling (mycelium/CODEO)	mycelium XSD codegen exists & compiles; one round-trip bug + documented gaps.	VS_PIKEOS_5.0 "Tooling 0%" (stale)

The older analyses (UNIVERSALISOS_VS_PIKEOS_5.0.md, UNIVERSALISOS_PIKEOS_ANALYSIS.md) use x86 virtualization terms (VT-x, VMX, EPT, VPID, VMCS) and pre-date mycelium + the AArch64 MP0 work. Treat their percentages as directional only; this matrix re-maps everything to ARM.

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2. Parity gap matrix

A. CPU / virtualization core (axis: Bao on AArch64; PikeOS VM layer on ARMv7)

Feature	PikeOS	Bao	Universalisos ARMv7	Universalisos AArch64	Effort
Boot + EL/priv bring-up	✅	✅	✅ (V)	✅ EL2 (V)	—
Stage-1 MMU (flat identity)	✅	✅	✅ (V)	✅ LPAE (V)	—
Exception/trap vectors	✅	✅	✅ (V)	✅ VBAR_EL2 (V)	—
Context switch (kernel tasks)	✅	✅	✅ (V)	✅ + preempt fix (V)	—
Preemptive scheduling (tick)	✅	✅	✅ (V)	✅ CNTHP @100 Hz (V)	—
Stage-2 MMU (VTTBR_EL2 / IPA→PA)	✅	✅	— (no S2 on v7)	❌	L
vCPU struct + world switch (ERET to guest EL1)	✅	✅	🟡 (vm.cpp frame)	❌	L
VGIC (GICv3 ICH_ virtual interrupts)*	✅	✅	— (GICv2)	❌	M
Virtual timer to guest (CNTVOFF_EL2)	✅	✅	—	❌	S
HCR_EL2 trap config (sysreg/IO/WFI trapping)	✅	✅	—	🟡 (IMO/FMO/AMO only) (V)	M
Hypercall ABI (guest→hyp)	✅	✅	✅ PV ABI (V)	❌	M
SMP (real multi-CPU scheduler)	✅	✅	🟡 framework	❌	L

B. Partitioning, scheduling, IPC (axis: PikeOS / ARINC 653)

Feature	PikeOS	Bao	ARMv7	AArch64	Effort
Static partitions + windows	✅	✅	✅ (V)	🟡 schema only (V)	M
ARINC 653 sampling ports	✅	—	✅ (V)	❌	M
ARINC 653 queuing ports	✅	—	✅ (V)	❌	M
Shared memory + events	✅	🟡	✅ (V)	❌	M
Time-partition scheduler	✅	✅	✅ (V)	✅ (V)	—
Rate/Deadline-monotonic, PIP	✅	—	❌	❌	M
Deadline-miss detection	✅	—	🟡 (HM)	❌	S
Capability-based access (MDB)	🟡	—	✅ seL4-style (V)	❌	M

C. Health, safety, system software (axis: PikeOS)

Feature	PikeOS	Bao	ARMv7	AArch64	Effort
3-tier Health Monitoring	✅	🟡	✅ (V)	❌	M
ASIL classification / fault containment	✅	—	🟡 framework	❌	L
MISRA C++ / ISO 26262 / DAL	✅	—	❌	❌	XL (cert)
Personalities (APEX/POSIX/Linux/Ada)	✅	—	❌	❌	XL
Network stack (lwIP/TCP-IP)	✅	—	❌ (driver only)	❌	L
Certified filesystem (FAT/JFFS2)	✅	—	❌	❌	L
Real Linux guest boot	✅	✅	❌ (PV ABI only)	❌	L (needs MP1)

D. Device & I/O (axis: PikeOS + Bao)

Feature	PikeOS	Bao	ARMv7	AArch64	Effort
UART / timer / GIC drivers	✅	✅	✅ (V)	✅ (V)	—
Block / net / GPIO / I2C / SPI / USB / PCI	✅	🟡	✅ present (V)	❌	L (port)
Virtio emulation (blk/net/console)	🟡	✅	🟡 (states exist)	❌	M
Device passthrough + IOMMU (SMMU)	✅	✅	❌	❌	XL
MMIO trap-emulate for guests	✅	✅	—	❌	M (needs S2)

Driver caveat: UNIVERSALISOS_PIKEOS_ANALYSIS.md claims "drivers 95–100% stubs", while status_report.md marks ARMv7 drivers "✅ Complete". The ARMv7 demo does exercise block/network (e1000/virtio/rtl8139 BSS states exist; block demo reports 0 errors). Treat drivers as present-but-largely-emulated on QEMU, not hardware-validated. (V) for "present", not "proven on HW".

E. Tooling & config (axis: PikeOS CODEO)

Feature	PikeOS	Universalisos	Effort
XSD → C/binary codegen (pikeos-configconv)	✅	🟡 mycelium (V) — works, 1 round-trip bug + gaps	S–M
VMIT XML config → kernel	✅	✅ cfg_parser.cpp (V)	—
IDE / Theia (CODEO) integration	✅	🟡 scaffold (mycelium ide/)	M
Host test harness (configmore --test)	✅	🟡 mycelium --test (WIP)	S

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3. Prioritized, ordered backlog

Order principle: foundation before features, ARMv7 is the reference of record (don't regress it), AArch64 is the growth track (virtualization lives here), RISC-V stays the parallel HW track. Each item: ID — title — [MPx] — effort — verify.

Horizon H0 — done / keep green (this session)

• DONE-1 ARMv7 linker ENTRY + RX/RW PHDRS → 0 warnings (V). Keep as the clean baseline.
• DONE-2 BSS 20.5 MB → 3.6 MB (guest image 16→1 MiB, ramdisk 256→128 KiB) (V).
• DONE-3 AArch64 MP0: EL2 boot (virtualization=on), LPAE S1, GICv3, CNTHP timer, preemptive scheduler → interleaved A/B, 0 traps (V). This is the MP0 gate; it now passes.

Horizon H1 — virtualization foundation (the PikeOS/Bao core gap) ← next track

• MP1.1 — Stage-2 MMU (AArch64) — [MP1] — L Build VTTBR_EL2 LPAE Stage-2 tables (IPA→PA), VTCR_EL2, HCR_EL2.VM=1, per-vCPU VPIDR_EL2/VMPIDR_EL2. Verify: identity-mapped guest IPA region; a Stage-2 fault routes to EL2 with ESR.EC=0x20/0x24.
• MP1.2 — vCPU struct + world switch — [MP1] — L vCPU {GPRs, ELR_EL2, SPSR_EL2, SP_EL1, SCTLR_EL1, TTBR0_EL1, VBAR_EL1, …}; vcpu_run() saves hyp, loads guest, ERET; exit traps back to EL2. Reuse context_switch.S frame shape. Verify: enter a tiny guest at EL1, execute a few instructions, trap on hvc/WFI, return to EL2.
• MP1.3 — VGIC (GICv3 list registers) — [MP1] — M Program ICH_*_EL2 (HCR/VSEIR/LR/VMCR), inject a vIRQ to the guest, EOI/maintenance IRQ path. Verify: guest receives a virtual PPI and EOIs it without a raw trap storm.
• MP1.4 — Virtual timer to guest — [MP1] — S CNTVOFF_EL2, CNTV_CVAL_EL0/CNTV_CTL_EL0 routing; guest sees a vtimer tick. Verify: guest EL1 reads CNTVCT and takes a vtimer interrupt.
• MP1.5 — Trap config matrix — [MP1] — M Decide/encode HCR_EL2.{TWI,TWE,TSC,TVM,…} and CPACR/TIDCP traps; document the policy. Verify: table-driven test of each trap class.

Horizon H2 — core PikeOS parity (RTOS axis)

• CORE-1 — Unify AArch64 with src/core/ IPC + HM + cap — [MP1/MP3] — M Port the ARMv7 core subsystems (sampling/queuing/shmem IPC, 3-tier HM, cap MDB) to AArch64 so both ARM tracks share one core (resolves open Q1: shared src/core/ over standalone). Verify: ARMv7 IPC/HM demo runs unchanged on AArch64.
• CORE-2 — Real SMP — [MP5] — L Secondary CPU bring-up, IPI/SGI, per-CPU runqueues, TLB shootdown. ARMv7 first (core exists), then AArch64. Verify: two tasks pinned to two CPUs both preempt via tick.
• CORE-3 — ARINC 653 scheduling hardening — [—] — M RMS/DMS, priority inheritance, deadline-miss → HM action, temporal-isolation guarantees. Verify: injected overrun triggers HM; windows enforced under load.
• CORE-4 — PikeOS syscall surface — [—] — M Extend beyond the present task/TLS/ExRegs set toward partition/thread/memory/sync APIs (libpikeos-shape). Verify: a conformance test list (name→implemented?) tracked in-tree.

Horizon H3 — system-software & platform reach (the "5–10%" layer)

• SYS-1 — Linux guest boot — [MP3] — L (blocked on MP1) Load a real kernel + DTB + initramfs via Stage-2, boot to a shell under the hypervisor. Verify: Linux boots as a guest vCPU on AArch64.
• SYS-2 — Personalities (APEX first, then POSIX) — [—] — XL APEX ARINC 653 process API surface over the existing IPC; POSIX later. Verify: APEX sample app links & runs in a partition.
• SYS-3 — Network stack (lwIP) — [—] — L lwIP as a partition/personality; virtio-net or e1000 backend. Verify: ping/echo from a guest/partition.
• SYS-4 — Filesystem (FAT/JFFS2) — [—] — L Block-backed FS; certified subset documented. Verify: mount/read/write in a partition.
• PLAT-1 — Hardware ports — [MP2] — L i.MX 8M Plus (AArch64), STM32MP257 (AArch64/CA35), i.MX6 (ARMv7) platform dirs + BSP. Verify: boots on real HW (or documented bring-up checklist).
• SAFE-1 — MISRA / fault containment / ASIL enforcement — [—] — XL (certification horizon) Coding-standard gate, WCET, audit trails. Long-horizon; track, don't front-load.

Horizon H4 — tooling (mycelium/CODEO) — Track A (separate agent; non-blocking)

• MYC-1 — Fix header.rs emitter — [M3] — S (highest-leverage mycelium fix) Restore child field names + array bounds; green the offline_test_passes round-trip.
• MYC-2 — Finish xs:extension — [M3] — S (wire extension_attributes through emitter).
• MYC-3 — Clean 2 warnings — [M3] — S (unused import, unread field).
• MYC-4 — Theia/CODEO view + configmore --test — [—] — M.

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4. Recommended next execution track: MP1 (AArch64 hardware virtualization)

Why now: H0 is green on both ARM tracks; the single biggest PikeOS/Bao parity gap is hardware virtualization, and it only exists on AArch64. Everything in H2 (guest boot, real partitions with isolation, MMIO trap-emulate) is gated by MP1. Starting here unblocks the most downstream work and matches the in-repo MP0→MP5 plan.

First slice (de-risked, observable): Stage-2 identity map + a single-instruction guest.

1. Build Stage-2 L0→L1 (1 GiB block) tables mapping IPA==PA for the QEMU DRAM window; set VTCR_EL2, VTTBR_EL2, HCR_EL2.VM=1, TGE=0, RW=1.
2. Allocate one vCPU, seed ELR_EL2=guest_entry, SPSR_EL2=EL1h, SP_EL1, minimal SCTLR_EL1.
3. Guest entry = a 3-instruction blob: mov x0,#0xAB; hvc #0; b . (the hvc traps to EL2).
4. vcpu_run() → ERET into EL1 → trap on hvc → EL2 handler prints x0==0xAB → park. Verify criterion: one clean EL1 entry and one hvc round-trip to EL2 with the guest GPR intact. No VGIC, no timer, no MMIO yet — those are MP1.3/1.4 once the world-switch is proven.

Guardrails (from this session's scars): always boot QEMU with virtualization=on; add an early CurrentEL print; for the world-switch debug, temporarily force the non-reschedule path to bisect "timer vs switch" exactly as we did for MP0.

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5. Mycelium tie-in (Track A, parallel — does not block MP1)

Mycelium already builds (cargo check clean); its real blocker is the header.rs emitter (field-name loss + array-bound misplacement → gcc rejects the generated header), codified by a unit test. It is the PikeOS CODEO pikeos-configconv parity axis (Tooling, §E) — valuable but independent of the hypervisor virtualization track. Run it on the mycelium agent (it never edits universalisos).

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6. Caveats on the source analyses (why this matrix supersedes them)

• Stale: UNIVERSALISOS_VS_PIKEOS_5.0.md & UNIVERSALISOS_PIKEOS_ANALYSIS.md pre-date mycelium and the AArch64 MP0 work; e.g. "Tooling 0%", "AArch64 boot ✅" (was false until this session), "drivers 95–100% stubs" vs status_report "drivers ✅ Complete".
• x86-biased: both use VT-x/VMX/EPT/VPID/VMCS vocabulary. Universalisos is an ARM/RISC-V hypervisor; parity is measured against Stage-2/VTTBR/GICv3-VGIC/vCPU (Bao), re-mapped here.
• Now-current: status_report.md's EXISTS/MISSING + MP0–MP5 scaffold is the closest to truth, but its AArch64 row ("build broken / MP0 ~15%") is outdated by this session's MP0 pass.
• Percentages in all docs are directional. The matrix uses ✅/🟡/❌ + (V) verified flags instead.

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7. Sources

• universalisos/UNIVERSALISOS_VS_PIKEOS_5.0.md — 11-category feature % (x86-biased, directional).
• universalisos/UNIVERSALISOS_PIKEOS_ANALYSIS.md — P1/P2/P3 critical gaps + 12/18-month roadmap.
• universalisos/universalisos_status_report.md — per-arch maturity, EXISTS/MISSING, MP0–MP5.
• universalisos/RISCV_PIKEOS_PARITY_PLAN.md — RISC-V S-mode paravirt map (parallel track).
• Verified this session (build + QEMU): ARMv7 demo, AArch64 MP0, BSS cut, linker hygiene.