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Migrate from Capstone to Zydis (x86 architecture) (#5164)

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* Added build files [Capstone to Zydis]

* x86 Analysis [Capstone to Zydis]

* Changed x86 RzIL [Capstone to Zydis]

* Changed asm and arch files [Capstone to Zydis]

* Compilation, build error and test fixes [Capstone to Zydis]

* Test changes [Capstone to Zydis]

* Remaining changes [Capstone to Zydis]

* Added BE support [Capstone to Zydis]

---------

Co-authored-by: tushar3q34 <tushar3q34@gmail.com>
This commit is contained in:
NOT XVilka 2025-05-23 21:03:46 +08:00 committed by GitHub
parent 275a12a3da
commit ba8c170852
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GPG key ID: B5690EEEBB952194
120 changed files with 71460 additions and 2994 deletions
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1
.gitignore vendored
View file

@ -133,6 +133,7 @@ subprojects/blake3/
subprojects/xz-*/
subprojects/zstd-*/
subprojects/softflo*/
subprojects/zydis/
dist/windows/Output
# Core files generated by OpenBSD
*.core

5
doc/PACKAGERS.md
View file

@ -60,10 +60,14 @@ directories used by Rizin, have a look at options `rizin_sdb`,
etc. in [meson_options.txt][].
Rizin uses the Capstone disassembly engine and supports versions 3, 4, and 5.
For x86/x86_64 architecture, we use the Zydis decoder and disassembler.
By default, we use a custom version of Capstone based on v5 and statically link
it into the Rizin executables. Some distributions might prefer that a system
version of Capstone be dynamically linked at runtime. To do this, use the
`-Duse_sys_capstone=enabled` command line option when running `meson`.
Similarly we statically link Zydis into the Rizin executables.
To dynamically link the system's Zydis at runtime, use the
`-Duse_sys_zydis=enabled` command line option when running `meson`.
You can override the version of Capstone Rizin will use by setting
`use_capstone_version` to one of `v4`, `v5`, `v6` or `next`.
@ -82,6 +86,7 @@ At the time of writing, these are:
* `use_sys_pcre2`
* `use_sys_tree_sitter`
* `use_sys_softfloat`
* `use_sys_zydis`
See [meson_options.txt][] for a complete list of compile-time options.

100
librz/arch/isa/x86/common.c
View file

@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: 2023 Dhruv Maroo <dhruvmaru007@gmail.com>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#include "common.h"
@ -7,7 +8,7 @@
/**
* \brief x86 registers
*/
const char *x86_registers[X86_REG_ENDING] = {
const char *x86_registers[X86_REG_MAX_VALUE] = {
[X86_REG_AH] = "ah",
[X86_REG_AL] = "al",
[X86_REG_AX] = "ax",
@ -34,11 +35,10 @@ const char *x86_registers[X86_REG_ENDING] = {
[X86_REG_EDX] = "edx",
[X86_REG_EFLAGS] = "eflags",
[X86_REG_EIP] = "eip",
[X86_REG_EIZ] = "eiz",
[X86_REG_ES] = "es",
[X86_REG_ESI] = "esi",
[X86_REG_ESP] = "esp",
[X86_REG_FPSW] = "swd",
[X86_REG_X87STATUS] = "swd",
[X86_REG_FS] = "fs",
[X86_REG_GS] = "gs",
[X86_REG_IP] = "ip",
@ -49,7 +49,6 @@ const char *x86_registers[X86_REG_ENDING] = {
[X86_REG_RDI] = "rdi",
[X86_REG_RDX] = "rdx",
[X86_REG_RIP] = "rip",
[X86_REG_RIZ] = "riz",
[X86_REG_RSI] = "rsi",
[X86_REG_RSP] = "rsp",
[X86_REG_SI] = "si",
@ -89,14 +88,6 @@ const char *x86_registers[X86_REG_ENDING] = {
[X86_REG_DR13] = "dr13",
[X86_REG_DR14] = "dr14",
[X86_REG_DR15] = "dr15",
[X86_REG_FP0] = "fp0",
[X86_REG_FP1] = "fp1",
[X86_REG_FP2] = "fp2",
[X86_REG_FP3] = "fp3",
[X86_REG_FP4] = "fp4",
[X86_REG_FP5] = "fp5",
[X86_REG_FP6] = "fp6",
[X86_REG_FP7] = "fp7",
[X86_REG_K0] = "k0",
[X86_REG_K1] = "k1",
[X86_REG_K2] = "k2",
@ -272,12 +263,12 @@ const X86Reg gpr_hregs[] = {
X86_REG_BH, // rbx
X86_REG_CH, // rcx
X86_REG_DH, // rdx
X86_REG_INVALID, // rbp
X86_REG_INVALID, // rdi
X86_REG_INVALID, // rip
X86_REG_INVALID, // riz
X86_REG_INVALID, // rsi
X86_REG_INVALID // rsp
X86_REG_NONE, // rbp
X86_REG_NONE, // rdi
X86_REG_NONE, // rip
X86_REG_NONE, // riz
X86_REG_NONE, // rsi
X86_REG_NONE // rsp
};
const X86Reg gpr_lregs[] = {
@ -287,8 +278,8 @@ const X86Reg gpr_lregs[] = {
X86_REG_DL, // rdx
X86_REG_BPL, // rbp
X86_REG_DIL, // rdi
X86_REG_INVALID, // rip
X86_REG_INVALID, // riz
X86_REG_NONE, // rip
X86_REG_NONE, // riz
X86_REG_SIL, // rsi
X86_REG_SPL, // rsp
};
@ -301,7 +292,7 @@ const X86Reg gpr_xregs[] = {
X86_REG_BP, // rbp
X86_REG_DI, // rdi
X86_REG_IP, // rip
X86_REG_INVALID, // riz
X86_REG_NONE, // riz
X86_REG_SI, // rsi
X86_REG_SP, // rsp
};
@ -314,7 +305,7 @@ const X86Reg gpr_eregs[] = {
X86_REG_EBP, // rbp
X86_REG_EDI, // rdi
X86_REG_EIP, // rip
X86_REG_EIZ, // riz
X86_REG_NONE, // riz
X86_REG_ESI, // rsi
X86_REG_ESP, // rsp
};
@ -327,7 +318,7 @@ const X86Reg gpr_rregs[] = {
X86_REG_RBP,
X86_REG_RDI,
X86_REG_RIP,
X86_REG_RIZ,
X86_REG_NONE,
X86_REG_RSI,
X86_REG_RSP
};
@ -498,7 +489,7 @@ RzILOpEffect *x86_il_set_gpr64(X86Reg reg, RzILOpPure *val, int bits) {
*/
X86Reg get_bitness_reg(unsigned int index, int bits) {
if (index >= GPR_FAMILY_COUNT) {
return X86_REG_INVALID;
return X86_REG_NONE;
}
if (bits == 16) {
return gpr_xregs[index];
@ -544,8 +535,6 @@ const struct gpr_lookup_helper_t gpr_lookup_table[] = {
[X86_REG_DI] = { 5, x86_il_get_gpr16, x86_il_set_gpr16 },
[X86_REG_EDI] = { 5, x86_il_get_gpr32, x86_il_set_gpr32 },
[X86_REG_RDI] = { 5, x86_il_get_gpr64, x86_il_set_gpr64 },
[X86_REG_EIZ] = { 7, x86_il_get_gpr32, x86_il_set_gpr32 },
[X86_REG_RIZ] = { 7, x86_il_get_gpr64, x86_il_set_gpr64 },
[X86_REG_SIL] = { 8, x86_il_get_gprl, x86_il_set_gprl },
[X86_REG_SI] = { 8, x86_il_get_gpr16, x86_il_set_gpr16 },
[X86_REG_ESI] = { 8, x86_il_get_gpr32, x86_il_set_gpr32 },
@ -673,13 +662,13 @@ RZ_IPI RzILOpEffect *x86_il_set_reg_bits(X86Reg reg, RZ_OWN RZ_NONNULL RzILOpPur
*/
RZ_IPI RzILOpPure *x86_il_get_memaddr_segment_bits(X86Mem mem, X86Reg segment, int bits, ut64 pc) {
RzILOpPure *offset = NULL;
if (mem.base != X86_REG_INVALID) {
if (mem.base != X86_REG_NONE) {
offset = x86_il_get_reg_bits(mem.base, bits, pc);
if (x86_il_get_reg_size(mem.base) != bits) {
offset = UNSIGNED(bits, offset);
}
}
if (mem.index != X86_REG_INVALID) {
if (mem.index != X86_REG_NONE) {
RzILOpPure *reg = x86_il_get_reg_bits(mem.index, bits, pc);
if (x86_il_get_reg_size(mem.index) != bits) {
reg = UNSIGNED(bits, reg);
@ -691,19 +680,21 @@ RZ_IPI RzILOpPure *x86_il_get_memaddr_segment_bits(X86Mem mem, X86Reg segment, i
}
}
if (!offset) {
offset = UN(bits, mem.disp);
offset = UN(bits, mem.disp.value);
} else {
offset = ADD(offset, UN(bits, mem.disp));
offset = ADD(offset, UN(bits, mem.disp.value));
}
/* Segmentation not present in x86-64 */
if (bits != 64 && segment != X86_REG_INVALID) {
if (bits != 64 && segment != X86_REG_NONE) {
// TODO: Implement segmentation
/* Currently the segmentation is only implemented for real mode
Address = Segment * 0x10 + Offset */
/* Assuming real mode */
offset = ADD(offset, SHIFTL0(UNSIGNED(bits, x86_il_get_reg_bits(segment, bits, pc)), U8(4)));
if (segment != X86_REG_DS) {
offset = ADD(offset, SHIFTL0(UNSIGNED(bits, x86_il_get_reg_bits(segment, bits, pc)), U8(4)));
}
}
return offset;
@ -727,21 +718,21 @@ RZ_IPI RzILOpEffect *x86_il_set_mem_bits(X86Mem mem, RZ_OWN RZ_NONNULL RzILOpPur
* \param op
* \param analysis_bits bitness
*/
RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size) {
RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size, const X86ILIns *ins) {
switch (op.type) {
case X86_OP_INVALID:
if (implicit_size) {
return SN(implicit_size * BITS_PER_BYTE, 1);
}
RZ_LOG_ERROR("x86: RzIL: Invalid param type encountered\n");
return NULL;
case X86_OP_REG:
return x86_il_get_reg_bits(op.reg, analysis_bits, pc);
return x86_il_get_reg_bits(op.reg.value, analysis_bits, pc);
case X86_OP_IMM:
/* Immediate values are always sign extended */
return SN((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, op.imm);
return SN((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, imm_value(op, pc));
case X86_OP_MEM:
return LOADW((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc));
case X86_OP_PTR: {
RzILOpPure *offset = UN(analysis_bits, op.ptr.offset);
RzILOpPure *segment = UN(analysis_bits, op.ptr.segment);
offset = ADD(offset, SHIFTL0(UNSIGNED(analysis_bits, segment), U8(4)));
return LOADW((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, offset);
}
default:
return NULL;
}
@ -762,7 +753,7 @@ RZ_IPI RzILOpEffect *x86_il_set_operand_bits(X86Op op, RZ_OWN RZ_NONNULL RzILOpP
RzILOpEffect *ret = NULL;
switch (op.type) {
case X86_OP_REG:
ret = x86_il_set_reg_bits(op.reg, val, bits);
ret = x86_il_set_reg_bits(op.reg.value, val, bits);
break;
case X86_OP_MEM:
ret = x86_il_set_mem_bits(op.mem, val, bits, pc);
@ -1343,7 +1334,7 @@ RZ_IPI RzILOpEffect *x86_il_set_st_reg_ctx(X86Reg reg, RZ_OWN RZ_NONNULL RzILOpF
* \return RzILOpPure* Bitvector of length 3
*/
RZ_IPI RzILOpPure *x86_il_get_fpu_stack_top() {
RzILOpPure *status_word = x86_il_get_reg_bits(X86_REG_FPSW, 0, 0);
RzILOpPure *status_word = x86_il_get_reg_bits(X86_REG_X87STATUS, 0, 0);
return UNSIGNED(3, SHIFTR0(status_word, UN(8, 11)));
}
@ -1362,8 +1353,8 @@ RZ_IPI RzILOpEffect *x86_il_set_fpu_stack_top(RZ_OWN RZ_NONNULL RzILOpPure *top)
/* 0x3800 only has the 12, 13 & 14 bits set, so we take its negation for the
* mask. */
RzILOpPure *mask = UN(16, ~(0x3800));
RzILOpPure *new_fpsw = LOGOR(shifted_top, LOGAND(mask, x86_il_get_reg_bits(X86_REG_FPSW, 0, 0)));
return x86_il_set_reg_bits(X86_REG_FPSW, new_fpsw, 0);
RzILOpPure *new_fpsw = LOGOR(shifted_top, LOGAND(mask, x86_il_get_reg_bits(X86_REG_X87STATUS, 0, 0)));
return x86_il_set_reg_bits(X86_REG_X87STATUS, new_fpsw, 0);
}
#define ST_MOVE_RIGHT(l, r) x86_il_set_st_reg(X86_REG_ST##r, x86_il_get_st_reg(X86_REG_ST##l), RZ_FLOAT_IEEE754_BIN_80)
@ -1437,7 +1428,7 @@ RZ_IPI ILPureEffectPair x86_il_st_pop_with_val() {
}
RZ_IPI RzILOpBool *x86_il_get_fpu_flag(X86FPUFlags flag) {
RzILOpPure *shifted_fpsw = SHIFTR0(x86_il_get_reg_bits(X86_REG_FPSW, 0, 0), UN(8, flag));
RzILOpPure *shifted_fpsw = SHIFTR0(x86_il_get_reg_bits(X86_REG_X87STATUS, 0, 0), UN(8, flag));
return NON_ZERO(UNSIGNED(1, shifted_fpsw));
}
@ -1446,8 +1437,8 @@ RZ_IPI RzILOpEffect *x86_il_set_fpu_flag(X86FPUFlags flag, RZ_OWN RZ_NONNULL RzI
RzILOpPure *zero_mask = UN(16, ~(1 << flag));
RzILOpPure *value_mask = SHIFTL0(BOOL_TO_BV(value, 16), UN(8, flag));
RzILOpPure *new_fpsw = LOGOR(value_mask, LOGAND(zero_mask, x86_il_get_reg_bits(X86_REG_FPSW, 0, 0)));
return x86_il_set_reg_bits(X86_REG_FPSW, new_fpsw, 0);
RzILOpPure *new_fpsw = LOGOR(value_mask, LOGAND(zero_mask, x86_il_get_reg_bits(X86_REG_X87STATUS, 0, 0)));
return x86_il_set_reg_bits(X86_REG_X87STATUS, new_fpsw, 0);
}
#define FLOATING_OP_MEM_WIDTH_CASE(n) \
@ -1470,10 +1461,10 @@ RZ_IPI RzILOpEffect *x86_il_set_fpu_flag(X86FPUFlags flag, RZ_OWN RZ_NONNULL RzI
RZ_IPI RzILOpPure *x86_il_get_floating_operand_bits(X86Op op, int bits, ut64 pc) {
switch (op.type) {
case X86_OP_REG:
if (x86_il_is_st_reg(op.reg)) {
return x86_il_get_st_reg(op.reg);
if (x86_il_is_st_reg(op.reg.value)) {
return x86_il_get_st_reg(op.reg.value);
} else {
RZ_LOG_ERROR("x86: RzIL: Invalid register passed as a floating point operand: %d\n", op.reg);
RZ_LOG_ERROR("x86: RzIL: Invalid register passed as a floating point operand: %d\n", op.reg.value);
}
break;
case X86_OP_MEM:
@ -1486,7 +1477,6 @@ RZ_IPI RzILOpPure *x86_il_get_floating_operand_bits(X86Op op, int bits, ut64 pc)
RZ_LOG_ERROR("x86: RzIL: Invalid memory operand width for a floating point operand: %d\n", op.size);
}
break;
case X86_OP_INVALID:
case X86_OP_IMM:
default:
RZ_LOG_ERROR("x86: RzIL: Invalid param type encountered: %d\n", op.type);
@ -1543,7 +1533,7 @@ RZ_IPI RzILOpEffect *x86_il_set_floating_operand_bits_ctx(X86Op op, RZ_OWN RZ_NO
switch (op.type) {
case X86_OP_REG:
return x86_il_set_st_reg(op.reg, val, val_format);
return x86_il_set_st_reg(op.reg.value, val, val_format);
case X86_OP_MEM: {
ut64 required_format = x86_width_to_format(op.size * BITS_PER_BYTE);
@ -1574,8 +1564,8 @@ RZ_IPI RzILOpEffect *x86_il_set_floating_operand_bits_ctx(X86Op op, RZ_OWN RZ_NO
}
RZ_IPI RzILOpEffect *x86_il_clear_fpsw_flags() {
RzILOpPure *new_fpsw = LOGAND(x86_il_get_reg_bits(X86_REG_FPSW, 0, 0), UN(16, 0x3f80));
return x86_il_set_reg_bits(X86_REG_FPSW, new_fpsw, 0);
RzILOpPure *new_fpsw = LOGAND(x86_il_get_reg_bits(X86_REG_X87STATUS, 0, 0), UN(16, 0x3f80));
return x86_il_set_reg_bits(X86_REG_X87STATUS, new_fpsw, 0);
}
#include <rz_il/rz_il_opbuilder_end.h>

14
librz/arch/isa/x86/common.h
View file

@ -1,10 +1,12 @@
// SPDX-FileCopyrightText: 2023 Dhruv Maroo <dhruvmaru007@gmail.com>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef X86_IL_COMMON_H
#define X86_IL_COMMON_H
#include "x86_il.h"
#include "x86_mnemonics.h"
#define X86_BIT(x) UN(1, x)
#define X86_TO32(x) UNSIGNED(32, x)
@ -50,12 +52,12 @@
#define x86_il_set_mem(mem, val) x86_il_set_mem_bits(mem, val, analysis->bits, pc)
#define x86_il_get_op(opnum) \
x86_il_get_operand_bits(ins->structure->operands[opnum], analysis->bits, pc, 0)
x86_il_get_operand_bits(ins->operands[opnum], analysis->bits, pc, 0, ins)
#define x86_il_get_op_implicit(opnum, mem_sz) \
x86_il_get_operand_bits(ins->structure->operands[opnum], analysis->bits, pc, mem_sz)
x86_il_get_operand_bits(ins->operands[opnum], analysis->bits, pc, mem_sz, ins)
#define x86_il_set_operand(op, val) x86_il_set_operand_bits(op, val, analysis->bits, pc)
#define x86_il_set_op(opnum, val) x86_il_set_operand_bits(ins->structure->operands[opnum], val, analysis->bits, pc)
#define x86_il_set_op(opnum, val) x86_il_set_operand_bits(ins->operands[opnum], val, analysis->bits, pc)
#define x86_il_set_result_flags(result) x86_il_set_result_flags_bits(result, analysis->bits)
#define x86_il_set_arithmetic_flags(res, x, y, addition) x86_il_set_arithmetic_flags_bits(res, x, y, addition, analysis->bits)
@ -87,7 +89,7 @@ extern const char *x86_eflags_registers[X86_EFLAGS_ENDING];
RZ_IPI RzILOpPure *x86_il_get_reg_bits(X86Reg reg, int bits, uint64_t pc);
RZ_IPI RzILOpEffect *x86_il_set_reg_bits(X86Reg reg, RZ_OWN RZ_NONNULL RzILOpPure *val, int bits);
RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size);
RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc, int implicit_size, const X86ILIns *ins);
RZ_IPI RzILOpEffect *x86_il_set_operand_bits(X86Op op, RZ_OWN RZ_NONNULL RzILOpPure *val, int bits, ut64 pc);
RZ_IPI RzILOpPure *x86_il_get_memaddr_bits(X86Mem mem, int bits, ut64 pc);
@ -182,7 +184,7 @@ RZ_IPI ILPureEffectPair x86_il_fsqrt_with_rmode_ctx(RZ_OWN RZ_NONNULL RzILOpFloa
RZ_IPI RzILOpPure *x86_il_get_floating_operand_bits(X86Op op, int analysis_bits, ut64 pc);
#define x86_il_get_floating_op(opnum) \
x86_il_get_floating_operand_bits(ins->structure->operands[opnum], analysis->bits, pc)
x86_il_get_floating_operand_bits(ins->operands[opnum], analysis->bits, pc)
RZ_IPI RzFloatFormat x86_width_to_format(ut8 width);
RZ_IPI ut8 x86_format_to_width(RzFloatFormat format);
@ -190,7 +192,7 @@ RZ_IPI ut8 x86_format_to_width(RzFloatFormat format);
RZ_IPI RzILOpEffect *x86_il_set_floating_operand_bits_ctx(X86Op op, RZ_OWN RZ_NONNULL RzILOpFloat *val, RzFloatFormat val_format, int bits, ut64 pc, RZ_BORROW X86ILContext *ctx);
#define x86_il_set_floating_op(opnum, val, val_format) \
x86_il_set_floating_operand_bits_ctx(ins->structure->operands[opnum], val, val_format, analysis->bits, pc, ctx)
x86_il_set_floating_operand_bits_ctx(ins->operands[opnum], val, val_format, analysis->bits, pc, ctx)
RZ_IPI RzILOpEffect *x86_il_clear_fpsw_flags();

59
librz/arch/isa/x86/il_fp_ops.inc
View file

@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: 2023 Dhruv Maroo <dhruvmaru007@gmail.com>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
/**
@ -26,7 +27,7 @@ IL_LIFTER(fninit) {
RzILOpEffect *set_cw = SETG(X86_REG_FPU_CW, UN(16, 0x37f));
/* No need to set C0-C3 flags to zero, since we are setting the FPSW to 0,
* so all the flag bits will also be set to 0. */
RzILOpEffect *set_sw = x86_il_set_reg(X86_REG_FPSW, UN(16, 0x0));
RzILOpEffect *set_sw = x86_il_set_reg(X86_REG_X87STATUS, UN(16, 0x0));
RzILOpEffect *set_tw = SETG(X86_REG_FPU_TW, UN(16, 0xffff));
RzILOpEffect *set_ip = SETG(X86_REG_FPU_IP, UN(32, 0x0));
RzILOpEffect *set_dp = SETG(X86_REG_FPU_DP, UN(32, 0x0));
@ -55,7 +56,7 @@ IL_LIFTER(fnstcw) {
* Store x87 FPU Status Word
*/
IL_LIFTER(fnstsw) {
return x86_il_set_op(0, x86_il_get_reg(X86_REG_FPSW));
return x86_il_set_op(0, x86_il_get_reg(X86_REG_X87STATUS));
}
/**
@ -64,8 +65,8 @@ IL_LIFTER(fnstsw) {
*/
IL_LIFTER(fnclex) {
/* Zero out the 15th bit and 0-7 bits. */
RzILOpPure *new_sw = LOGAND(x86_il_get_reg(X86_REG_FPSW), UN(16, 0x7f00));
return SEQ2(x86_il_set_reg(X86_REG_FPSW, new_sw), x86_il_clear_fpsw_flags());
RzILOpPure *new_sw = LOGAND(x86_il_get_reg(X86_REG_X87STATUS), UN(16, 0x7f00));
return SEQ2(x86_il_set_reg(X86_REG_X87STATUS, new_sw), x86_il_clear_fpsw_flags());
}
/**
@ -74,7 +75,7 @@ IL_LIFTER(fnclex) {
*/
IL_LIFTER(fld) {
return x86_il_st_push(x86_il_get_floating_op(0),
x86_width_to_format(ins->structure->operands[0].size * BITS_PER_BYTE));
x86_width_to_format(ins->operands[0].size * BITS_PER_BYTE));
}
/**
@ -202,11 +203,11 @@ IL_LIFTER(fldln2) {
IL_LIFTER(fxch) {
X86Reg reg;
if (ins->structure->op_count == 0) {
if (ins->structure->operand_count_visible == 0) {
/* Use ST1 as the default reg in case no operand is provided. */
reg = X86_REG_ST1;
} else {
reg = ins->structure->operands[1].reg;
reg = ins->operands[0].reg.value;
}
/* TODO: The IL generated from the following code is too verbose because of
@ -235,7 +236,7 @@ IL_LIFTER(fild) {
* Store float in ST(0) after rounding to integer
*/
IL_LIFTER(fist) {
ILPureEffectPair int_val = x86_il_int_from_floating(x86_il_get_st_reg(X86_REG_ST0), ins->structure->operands[0].size * BITS_PER_BYTE);
ILPureEffectPair int_val = x86_il_int_from_floating(x86_il_get_st_reg(X86_REG_ST0), ins->operands[0].size * BITS_PER_BYTE);
return SEQ2(int_val.eff, x86_il_set_op(0, int_val.val));
}
@ -245,7 +246,7 @@ IL_LIFTER(fist) {
*/
IL_LIFTER(fistp) {
ILPureEffectPair pop = x86_il_st_pop_with_val();
ILPureEffectPair int_val = x86_il_int_from_floating(pop.val, ins->structure->operands[0].size * BITS_PER_BYTE);
ILPureEffectPair int_val = x86_il_int_from_floating(pop.val, ins->operands[0].size * BITS_PER_BYTE);
return SEQ3(int_val.eff, x86_il_set_op(0, int_val.val), pop.eff);
}
@ -257,7 +258,7 @@ IL_LIFTER(fistp) {
IL_LIFTER(fbld) {
ut8 mem_size = analysis->bits;
RzILOpEffect *mem_init = SETL("mem", x86_il_get_memaddr(ins->structure->operands[0].mem));
RzILOpEffect *mem_init = SETL("mem", x86_il_get_memaddr(ins->operands[0].mem));
RzILOpEffect *i_init = SETL("i", UN(mem_size, 8));
RzILOpEffect *val_init = SETL("val", UN(64, 0));
@ -307,7 +308,7 @@ IL_LIFTER(fbstp) {
RzILOpEffect *sgn_init = SETL("sgn", MSB(VARL("val")));
RzILOpEffect *val_abs = SETL("val", ITE(VARL("sgn"), NEG(VARL("val")), VARL("val")));
RzILOpEffect *mem_init = SETL("mem", x86_il_get_memaddr(ins->structure->operands[0].mem));
RzILOpEffect *mem_init = SETL("mem", x86_il_get_memaddr(ins->operands[0].mem));
RzILOpEffect *i_init = SETL("i", UN(mem_size, 0));
RzILOpPure *byte_mem = ADD(VARL("mem"), VARL("i"));
@ -361,7 +362,7 @@ IL_LIFTER(fabs) {
\
/* TODO: Check whether all the enumerated cases here are correct, through \
* code coverage. */ \
switch (ins->structure->op_count) { \
switch (ins->structure->operand_count_visible) { \
case 1: \
/* Need to convert a 32-bit or 64-bit memory operand */ \
dest_reg = X86_REG_ST0; \
@ -369,11 +370,14 @@ IL_LIFTER(fabs) {
src = resized.val; \
src_eff = resized.eff; \
break; \
case 2: \
case 2: { \
/* ST(i) operand, so no need for resizing */ \
dest_reg = ins->structure->operands[0].reg; \
src = x86_il_get_floating_op(0); \
dest_reg = ins->operands[0].reg.value; \
ILPureEffectPair resized = x86_il_resize_floating(x86_il_get_floating_op(1), RZ_FLOAT_IEEE754_BIN_80); \
src = resized.val; \
src_eff = resized.eff; \
break; \
} \
default: \
rz_warn_if_reached(); \
return NULL; \
@ -392,9 +396,9 @@ IL_LIFTER(fabs) {
do { \
X86Reg dest_reg = X86_REG_ST1; \
\
if (ins->structure->op_count == 2) { \
if (ins->structure->operand_count_visible == 2) { \
/* Destination register passed in as the first operand */ \
dest_reg = ins->structure->operands[0].reg; \
dest_reg = ins->operands[0].reg.value; \
} \
\
ILPureEffectPair result = x86_il_##op##_with_rmode(x86_il_get_st_reg(X86_REG_ST0), x86_il_get_st_reg(dest_reg)); \
@ -415,7 +419,7 @@ IL_LIFTER(fabs) {
IL_LIFTER(fadd) {
/* Have a unified IL lifter for FADD and FADDP since Capstone has removed the
* distinction after version 4, which I think is a terrible thing. */
if (ins->structure->opcode[0] == 0xde) {
if (ins->structure->opcode == 0xde) {
// FADDP
FLOATING_ARITHMETIC_POP_IL(fadd);
} else {
@ -558,11 +562,14 @@ RzILOpEffect *fcom_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analysis, Rz
if (op1_override) {
op1 = op1_override;
} else if (ins->structure->op_count == 0) {
} else if (ins->structure->operand_count_visible == 0) {
/* ST(1) is the default operand */
op1 = x86_il_get_st_reg(X86_REG_ST1);
} else {
} else if (ins->structure->operand_count_visible == 1) {
op1 = x86_il_get_floating_op(0);
} else {
st0 = x86_il_get_floating_op(0);
op1 = x86_il_get_floating_op(1);
}
// TODO: Set the C0, C2, C3 bits depending on invalid arithmetic operand exception (#IA).
@ -636,16 +643,6 @@ IL_LIFTER(fcomi) {
return fcomi_helper(ins, pc, analysis);
}
#if CS_API_MAJOR > 4
/**
* FCOMIP
* Compare ST(0) and ST(i), set the EFLAGS accordingly and pop the stack
*/
IL_LIFTER(fcomip) {
return SEQ2(fcomi_helper(ins, pc, analysis), x86_il_st_pop());
}
#endif
/**
* FCHS
* Change the sign of ST(0)
@ -699,7 +696,7 @@ IL_LIFTER(fnop) {
* Round ST(0) to an integer (using RZ_FLOAT_RMODE_RTZ), store the integer in the memory operand and pop the stack
*/
IL_LIFTER(fisttp) {
ILPureEffectPair int_from_float = x86_il_int_from_floating(x86_il_get_st_reg(X86_REG_ST0), ins->structure->operands[0].size * BITS_PER_BYTE);
ILPureEffectPair int_from_float = x86_il_int_from_floating(x86_il_get_st_reg(X86_REG_ST0), ins->operands[0].size * BITS_PER_BYTE);
return SEQ3(int_from_float.eff, x86_il_set_op(0, int_from_float.val), x86_il_st_pop());
}

235
librz/arch/isa/x86/il_ops.inc
View file

@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: 2023 Dhruv Maroo <dhruvmaru007@gmail.com>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
/**
@ -11,7 +12,7 @@
*/
#include "common.h"
#include "x86/x86_il.h"
#include "x86_il.h"
#include <rz_il/rz_il_opbuilder_begin.h>
/**
@ -74,7 +75,7 @@ IL_LIFTER(aad) {
RzILOpEffect *temp_ah = SETL("temp_ah", x86_il_get_reg(X86_REG_AH));
RzILOpPure *imm;
if (ins->structure->op_count == 0) {
if (ins->structure->operand_count_visible == 0) {
// Use base 10 if none specified
imm = SN(8, 0x0a);
} else {
@ -100,7 +101,7 @@ IL_LIFTER(aam) {
RzILOpEffect *temp_al = SETL("temp_al", x86_il_get_reg(X86_REG_AL));
RzILOpPure *imm;
if (ins->structure->op_count == 0) {
if (ins->structure->operand_count_visible == 0) {
imm = SN(8, 0xa);
} else {
imm = x86_il_get_op(0);
@ -157,7 +158,7 @@ IL_LIFTER(adc) {
RzILOpEffect *op2 = SETL("op2", x86_il_get_op(1));
RzILOpPure *cf = VARG(EFLAGS(CF));
RzILOpEffect *sum = SETL("sum", ADD(ADD(VARL("op1"), VARL("op2")), BOOL_TO_BV(cf, ins->structure->operands[0].size * BITS_PER_BYTE)));
RzILOpEffect *sum = SETL("sum", ADD(ADD(VARL("op1"), VARL("op2")), BOOL_TO_BV(cf, ins->operands[0].size * BITS_PER_BYTE)));
RzILOpEffect *set_dest = x86_il_set_op(0, VARL("sum"));
RzILOpEffect *set_res_flags = x86_il_set_result_flags(VARL("sum"));
RzILOpEffect *set_arith_flags = x86_il_set_arithmetic_flags(VARL("sum"), VARL("op1"), VARL("op2"), true);
@ -222,7 +223,7 @@ IL_LIFTER(bsf) {
RzILOpEffect *set_zf = SETG(EFLAGS(ZF), IL_FALSE);
uint8_t op_size = ins->structure->operands[0].size * BITS_PER_BYTE;
uint8_t op_size = ins->operands[0].size * BITS_PER_BYTE;
RzILOpEffect *tmp_var = SETL("tmpvar", UN(op_size, 0));
RzILOpEffect *calc = REPEAT(INV(LSB(SHIFTR0(src, VARL("tmpvar")))), SETL("tmpvar", ADD(VARL("tmpvar"), UN(op_size, 1))));
@ -310,7 +311,7 @@ RzILOpEffect *x86_il_cmp_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analys
ut8 mem_size = 64;
/* Address override prefix: 67H */
if (ins->structure->prefix[3]) {
if (ins->structure->raw.prefixes[3].value) {
mem_reg1 = X86_REG_ESI;
mem_reg2 = X86_REG_EDI;
mem_size = 32;
@ -334,7 +335,7 @@ RzILOpEffect *x86_il_cmp_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analys
ut8 mem_size = 32;
/* Address override prefix: 67H */
if (analysis->bits == 16 || ins->structure->prefix[3]) {
if (analysis->bits == 16 || ins->structure->raw.prefixes[3].value) {
mem_reg1 = X86_REG_SI;
mem_reg2 = X86_REG_DI;
mem_size = 16;
@ -342,15 +343,15 @@ RzILOpEffect *x86_il_cmp_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analys
X86Mem src_mem1 = {
.base = mem_reg1,
.disp = 0,
.index = X86_REG_INVALID,
.disp = { 0 },
.index = X86_REG_NONE,
.scale = 1,
.segment = X86_REG_DS
};
X86Mem src_mem2 = {
.base = mem_reg2,
.disp = 0,
.index = X86_REG_INVALID,
.disp = { 0 },
.index = X86_REG_NONE,
.scale = 1,
.segment = X86_REG_ES
};
@ -372,11 +373,11 @@ RzILOpEffect *x86_il_cmp_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analys
RzILOpPure *get_cmov_cond(X86InsMnem ins) {
switch (ins) {
case X86_INS_CMOVA:
case X86_INS_CMOVNBE:
/* Same as CMOVNBE */
/* CF = 0 and ZF = 0 */
return AND(INV(VARG(EFLAGS(CF))), INV(VARG(EFLAGS(ZF))));
case X86_INS_CMOVAE:
case X86_INS_CMOVNB:
/* Same as CMOVNB, CMOVNC */
/* CF = 0 */
return INV(VARG(EFLAGS(CF)));
@ -388,15 +389,15 @@ RzILOpPure *get_cmov_cond(X86InsMnem ins) {
/* Same as CMOVNA */
/* CF = 1 or ZF = 1*/
return OR(VARG(EFLAGS(CF)), VARG(EFLAGS(ZF)));
case X86_INS_CMOVE:
case X86_INS_CMOVZ:
/* Same as CMOVZ */
/* ZF = 1 */
return VARG(EFLAGS(ZF));
case X86_INS_CMOVG:
case X86_INS_CMOVNLE:
/* Same as CMOVNLE */
/* ZF = 0 and SF = OF */
return AND(INV(VARG(EFLAGS(ZF))), INV(XOR(VARG(EFLAGS(SF)), VARG(EFLAGS(OF)))));
case X86_INS_CMOVGE:
case X86_INS_CMOVNL:
/* Same CMOVNL */
/* SF = OF */
return INV(XOR(VARG(EFLAGS(SF)), VARG(EFLAGS(OF))));
@ -407,7 +408,7 @@ RzILOpPure *get_cmov_cond(X86InsMnem ins) {
/* Same as CMOVNG */
/* ZF = 1 or SF != OF */
return OR(VARG(EFLAGS(ZF)), XOR(VARG(EFLAGS(SF)), VARG(EFLAGS(OF))));
case X86_INS_CMOVNE:
case X86_INS_CMOVNZ:
/* Same as CMOVNZ */
/* ZF = 0 */
return INV(VARG(EFLAGS(ZF)));
@ -559,12 +560,12 @@ IL_LIFTER(das) {
*/
IL_LIFTER(dec) {
RzILOpEffect *op = SETL("_op", x86_il_get_op(0));
RzILOpEffect *dec = SETL("_dec", SUB(VARL("_op"), UN(ins->structure->operands[0].size * BITS_PER_BYTE, 1)));
RzILOpEffect *dec = SETL("_dec", SUB(VARL("_op"), UN(ins->operands[0].size * BITS_PER_BYTE, 1)));
RzILOpEffect *set_result = x86_il_set_op(0, VARL("_dec"));
RzILOpEffect *res_flags = x86_il_set_result_flags(VARL("_dec"));
RzILOpEffect *arith_flags = x86_il_set_arithmetic_flags_except_cf(VARL("_dec"), VARL("_op"), UN(ins->structure->operands[0].size * BITS_PER_BYTE, 1), false);
RzILOpEffect *arith_flags = x86_il_set_arithmetic_flags_except_cf(VARL("_dec"), VARL("_op"), UN(ins->operands[0].size * BITS_PER_BYTE, 1), false);
return SEQ5(op, dec, set_result, res_flags, arith_flags);
}
@ -577,7 +578,7 @@ IL_LIFTER(dec) {
IL_LIFTER(div) {
RzILOpEffect *ret = NULL;
switch (ins->structure->operands[0].size) {
switch (ins->operands[0].size) {
case 1: {
/* Word/Byte operation */
RzILOpEffect *ax = SETL("_ax", x86_il_get_reg(X86_REG_AX));
@ -628,7 +629,7 @@ IL_LIFTER(div) {
}
/* We need the divisor to be as wide as the operand, since the sizes of the dividend and the divisor need to match */
RzILOpEffect *op = SETL("_src", UNSIGNED(ins->structure->operands[0].size * 2 * BITS_PER_BYTE, x86_il_get_op(0)));
RzILOpEffect *op = SETL("_src", UNSIGNED(ins->operands[0].size * 2 * BITS_PER_BYTE, x86_il_get_op(0)));
/* Check if the operand is zero, return NULL if it is (to avoid divide by zero) */
return SEQ2(op, BRANCH(IS_ZERO(VARL("_src")), NULL, ret));
@ -663,7 +664,7 @@ void label_halt(RzILVM *vm, RzILOpEffect *op) {
IL_LIFTER(idiv) {
RzILOpEffect *ret = NULL;
switch (ins->structure->operands[0].size) {
switch (ins->operands[0].size) {
case 1: {
/* Word/Byte operation */
RzILOpEffect *ax = SETL("_ax", x86_il_get_reg(X86_REG_AX));
@ -714,7 +715,7 @@ IL_LIFTER(idiv) {
}
/* We need the divisor to be as wide as the operand, since the sizes of the dividend and the divisor need to match */
RzILOpEffect *op = SETL("_src", UNSIGNED(ins->structure->operands[0].size * 2 * BITS_PER_BYTE, x86_il_get_op(0)));
RzILOpEffect *op = SETL("_src", UNSIGNED(ins->operands[0].size * 2 * BITS_PER_BYTE, x86_il_get_op(0)));
/* Check if the operand is zero, return NULL if it is (to avoid divide by zero) */
return SEQ2(op, BRANCH(IS_ZERO(VARL("_src")), NULL, ret));
@ -729,9 +730,9 @@ IL_LIFTER(idiv) {
* - Three operands (Encoding: RMI)
*/
IL_LIFTER(imul) {
switch (ins->structure->op_count) {
switch (ins->structure->operand_count_visible) {
case 1: {
switch (ins->structure->operands[0].size) {
switch (ins->operands[0].size) {
case 1: {
RzILOpEffect *tmp_xp = SETL("_tmp_xp", MUL(SIGNED(16, x86_il_get_reg(X86_REG_AL)), SIGNED(16, x86_il_get_op(0))));
RzILOpEffect *set_ax = x86_il_set_reg(X86_REG_AX, VARL("_tmp_xp"));
@ -786,24 +787,24 @@ IL_LIFTER(imul) {
}
case 2: {
RzILOpEffect *dest = SETL("_dest", x86_il_get_op(0));
RzILOpEffect *tmp_xp = SETL("_tmp_xp", MUL(SIGNED(ins->structure->operands[0].size * 2 * BITS_PER_BYTE, VARL("_dest")), SIGNED(ins->structure->operands[0].size * 2 * BITS_PER_BYTE, x86_il_get_op(1))));
RzILOpEffect *set_dest = SETL("_dest", UNSIGNED(ins->structure->operands[0].size * BITS_PER_BYTE, VARL("_tmp_xp")));
RzILOpEffect *tmp_xp = SETL("_tmp_xp", MUL(SIGNED(ins->operands[0].size * 2 * BITS_PER_BYTE, VARL("_dest")), SIGNED(ins->operands[0].size * 2 * BITS_PER_BYTE, x86_il_get_op(1))));
RzILOpEffect *set_dest = SETL("_dest", UNSIGNED(ins->operands[0].size * BITS_PER_BYTE, VARL("_tmp_xp")));
RzILOpEffect *set_operand = x86_il_set_op(0, VARL("_dest"));
/* Check if the result fits in the destination */
RzILOpPure *cond = EQ(SIGNED(ins->structure->operands[0].size * 2 * BITS_PER_BYTE, VARL("_dest")), VARL("_tmp_xp"));
RzILOpPure *cond = EQ(SIGNED(ins->operands[0].size * 2 * BITS_PER_BYTE, VARL("_dest")), VARL("_tmp_xp"));
RzILOpEffect *true_branch = SEQ2(SETG(EFLAGS(CF), IL_FALSE), SETG(EFLAGS(OF), IL_FALSE));
RzILOpEffect *false_branch = SEQ2(SETG(EFLAGS(CF), IL_TRUE), SETG(EFLAGS(OF), IL_TRUE));
return SEQ5(dest, tmp_xp, set_dest, set_operand, BRANCH(cond, true_branch, false_branch));
}
case 3: {
RzILOpEffect *tmp_xp = SETL("_tmp_xp", MUL(SIGNED(ins->structure->operands[1].size * 2 * BITS_PER_BYTE, x86_il_get_op(1)), SIGNED(ins->structure->operands[1].size * 2 * BITS_PER_BYTE, x86_il_get_op(2))));
RzILOpEffect *set_dest = SETL("_dest", UNSIGNED(ins->structure->operands[0].size * BITS_PER_BYTE, VARL("_tmp_xp")));
RzILOpEffect *tmp_xp = SETL("_tmp_xp", MUL(SIGNED(ins->operands[1].size * 2 * BITS_PER_BYTE, x86_il_get_op(1)), SIGNED(ins->operands[1].size * 2 * BITS_PER_BYTE, x86_il_get_op(2))));
RzILOpEffect *set_dest = SETL("_dest", UNSIGNED(ins->operands[0].size * BITS_PER_BYTE, VARL("_tmp_xp")));
RzILOpEffect *set_operand = x86_il_set_op(0, VARL("_dest"));
/* Check if the result fits in the destination */
RzILOpPure *cond = EQ(SIGNED(ins->structure->operands[0].size * 2 * BITS_PER_BYTE, VARL("_dest")), VARL("_tmp_xp"));
RzILOpPure *cond = EQ(SIGNED(ins->operands[0].size * 2 * BITS_PER_BYTE, VARL("_dest")), VARL("_tmp_xp"));
RzILOpEffect *true_branch = SEQ2(SETG(EFLAGS(CF), IL_FALSE), SETG(EFLAGS(OF), IL_FALSE));
RzILOpEffect *false_branch = SEQ2(SETG(EFLAGS(CF), IL_TRUE), SETG(EFLAGS(OF), IL_TRUE));
@ -839,10 +840,10 @@ void label_port(RzILVM *vm, RzILOpEffect *op) {
*/
IL_LIFTER(inc) {
RzILOpEffect *op = SETL("_op", x86_il_get_op(0));
RzILOpEffect *result = SETL("_result", ADD(VARL("_op"), UN(ins->structure->operands[0].size * BITS_PER_BYTE, 1)));
RzILOpEffect *result = SETL("_result", ADD(VARL("_op"), UN(ins->operands[0].size * BITS_PER_BYTE, 1)));
RzILOpEffect *set_result = x86_il_set_op(0, VARL("_result"));
RzILOpEffect *arith_flags = x86_il_set_arithmetic_flags_except_cf(VARL("_result"), VARL("_op"), UN(ins->structure->operands[0].size * BITS_PER_BYTE, 1), true);
RzILOpEffect *arith_flags = x86_il_set_arithmetic_flags_except_cf(VARL("_result"), VARL("_op"), UN(ins->operands[0].size * BITS_PER_BYTE, 1), true);
RzILOpEffect *res_flags = x86_il_set_result_flags(VARL("_result"));
return SEQ5(op, result, set_result, arith_flags, res_flags);
@ -879,8 +880,8 @@ IL_LIFTER(into) {
#define JUMP_IL() \
do { \
RzILOpPure *jmp_addr = UN(analysis->bits, ins->structure->operands[0].imm); \
if (ins->structure->operands[0].size == 16 && analysis->bits != 64) { \
RzILOpPure *jmp_addr = UN(analysis->bits, imm_value(ins->operands[0], pc)); \
if (ins->operands[0].size == 16 && analysis->bits != 64) { \
jmp_addr = LOGAND(jmp_addr, UN(analysis->bits, 0x0000ffff)); \
} \
return BRANCH(cond, JMP(jmp_addr), NOP()); \
@ -1106,7 +1107,7 @@ IL_LIFTER(lahf) {
* Encoding: RM
*/
IL_LIFTER(lds) {
return x86_il_set_op(0, x86_il_get_memaddr_segment(ins->structure->operands[1].mem, X86_REG_DS));
return x86_il_set_op(0, x86_il_get_memaddr_segment(ins->operands[1].mem, X86_REG_DS));
}
/**
@ -1116,7 +1117,7 @@ IL_LIFTER(lds) {
* Cast the M to R in an unsigned cast
*/
IL_LIFTER(lea) {
return x86_il_set_op(0, UNSIGNED(ins->structure->operands[1].size * BITS_PER_BYTE, x86_il_get_memaddr(ins->structure->operands[1].mem)));
return x86_il_set_op(0, UNSIGNED(ins->operands[1].size * BITS_PER_BYTE, x86_il_get_memaddr(ins->operands[1].mem)));
}
/**
@ -1125,7 +1126,7 @@ IL_LIFTER(lea) {
* Encoding: RM
*/
IL_LIFTER(les) {
return x86_il_set_op(0, x86_il_get_memaddr_segment(ins->structure->operands[1].mem, X86_REG_ES));
return x86_il_set_op(0, x86_il_get_memaddr_segment(ins->operands[1].mem, X86_REG_ES));
}
RzILOpEffect *x86_il_lods_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analysis, ut8 size) {
@ -1152,7 +1153,7 @@ RzILOpEffect *x86_il_lods_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Reg mem_reg = X86_REG_RSI;
ut8 mem_size = 64;
/* Address override prefix: 67H */
if (ins->structure->prefix[3]) {
if (ins->structure->raw.prefixes[3].value) {
mem_reg = X86_REG_ESI;
mem_size = 32;
}
@ -1169,15 +1170,15 @@ RzILOpEffect *x86_il_lods_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Reg mem_reg = X86_REG_ESI;
ut8 mem_size = 32;
/* Address override prefix: 67H */
if (analysis->bits == 16 || ins->structure->prefix[3]) {
if (analysis->bits == 16 || ins->structure->raw.prefixes[3].value) {
mem_reg = X86_REG_SI;
mem_size = 16;
}
X86Mem src_mem;
src_mem.base = mem_reg;
src_mem.disp = 0;
src_mem.index = X86_REG_INVALID;
src_mem.disp.value = 0;
src_mem.index = X86_REG_NONE;
src_mem.scale = 1;
src_mem.segment = X86_REG_DS;
@ -1235,13 +1236,13 @@ IL_LIFTER(lodsq) {
\
uint8_t addr_size = analysis->bits; \
/* Check address override prefix (67H) */ \
if (analysis->bits == 64 && ins->structure->prefix[3]) { \
if (analysis->bits == 64 && ins->structure->raw.prefixes[3].value) { \
addr_size >>= 1; \
count_reg = X86_REG_ECX; \
} \
\
RzILOpEffect *dec_counter = x86_il_set_reg(count_reg, SUB(x86_il_get_reg(count_reg), UN(addr_size, 1))); \
RzILOpEffect *true_cond = JMP(UN(analysis->bits, pc + ins->structure->operands[0].imm)); \
RzILOpEffect *true_cond = JMP(UN(analysis->bits, pc + imm_value(ins->operands[0], pc))); \
RzILOpEffect *branch = BRANCH(cond, true_cond, NOP()); \
\
return SEQ2(dec_counter, branch); \
@ -1299,7 +1300,7 @@ RzILOpEffect *x86_il_movs_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
ut8 mem_size = 64;
/* Address override prefix: 67H */
if (ins->structure->prefix[3]) {
if (ins->structure->raw.prefixes[3].value) {
mem_reg1 = X86_REG_ESI;
mem_reg2 = X86_REG_EDI;
mem_size = 32;
@ -1319,7 +1320,7 @@ RzILOpEffect *x86_il_movs_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
ut8 mem_size = 32;
/* Address override prefix: 67H */
if (analysis->bits == 16 || ins->structure->prefix[3]) {
if (analysis->bits == 16 || ins->structure->raw.prefixes[3].value) {
src_reg = X86_REG_SI;
dst_reg = X86_REG_DI;
mem_size = 16;
@ -1327,15 +1328,15 @@ RzILOpEffect *x86_il_movs_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Mem src_mem = {
.base = src_reg,
.disp = 0,
.index = X86_REG_INVALID,
.disp = { 0 },
.index = X86_REG_NONE,
.scale = 1,
.segment = X86_REG_DS
};
X86Mem dst_mem = {
.base = dst_reg,
.disp = 0,
.index = X86_REG_INVALID,
.disp = { 0 },
.index = X86_REG_NONE,
.scale = 1,
.segment = X86_REG_ES
};
@ -1392,7 +1393,7 @@ IL_LIFTER(movsq) {
* Encoding: RM
*/
IL_LIFTER(movsx) {
return x86_il_set_op(0, SIGNED(ins->structure->operands[0].size * BITS_PER_BYTE, x86_il_get_op(1)));
return x86_il_set_op(0, SIGNED(ins->operands[0].size * BITS_PER_BYTE, x86_il_get_op(1)));
}
/**
@ -1401,7 +1402,7 @@ IL_LIFTER(movsx) {
* Encoding: RM
*/
IL_LIFTER(movzx) {
return x86_il_set_op(0, UNSIGNED(ins->structure->operands[0].size * BITS_PER_BYTE, x86_il_get_op(1)));
return x86_il_set_op(0, UNSIGNED(ins->operands[0].size * BITS_PER_BYTE, x86_il_get_op(1)));
}
/**
@ -1410,11 +1411,11 @@ IL_LIFTER(movzx) {
* Encoding: M
*/
IL_LIFTER(mul) {
RzILOpPure *op = UNSIGNED(ins->structure->operands[0].size * BITS_PER_BYTE * 2, x86_il_get_op(0));
RzILOpPure *op = UNSIGNED(ins->operands[0].size * BITS_PER_BYTE * 2, x86_il_get_op(0));
RzILOpEffect *true_cond = SEQ2(SETG(EFLAGS(OF), IL_FALSE), SETG(EFLAGS(CF), IL_FALSE));
RzILOpEffect *false_cond = SEQ2(SETG(EFLAGS(OF), IL_TRUE), SETG(EFLAGS(CF), IL_TRUE));
switch (ins->structure->operands[0].size) {
switch (ins->operands[0].size) {
case 1: {
RzILOpEffect *set = SETL("_mul", MUL(UNSIGNED(16, x86_il_get_reg(X86_REG_AL)), op));
RzILOpEffect *ax = x86_il_set_reg(X86_REG_AX, VARL("_mul"));
@ -1529,8 +1530,8 @@ PopHelper x86_pop_helper_bits(unsigned int op_size, unsigned int bitness, ut64 p
X86Mem stack_mem;
/* The correct register will automatically be chosen if we use RSP */
stack_mem.base = X86_REG_RSP;
stack_mem.disp = 0;
stack_mem.index = X86_REG_INVALID;
stack_mem.disp.value = 0;
stack_mem.index = X86_REG_NONE;
stack_mem.scale = 1;
stack_mem.segment = X86_REG_SS;
@ -1556,7 +1557,7 @@ IL_LIFTER(pop) {
/* Ideally, we should use the stack size instead of the address size (analysis->bits),
but there seems to be no way to do that using Capstone */
/* Also, it is very rare to use have a different stack size and address size */
PopHelper pop = x86_pop_helper(ins->structure->operands[0].size);
PopHelper pop = x86_pop_helper(ins->operands[0].size);
RzILOpEffect *copy = x86_il_set_op(0, pop.val);
return SEQ2(copy, pop.eff);
@ -1602,12 +1603,12 @@ RzILOpEffect *x86_push_helper_impl(RzILOpPure *val, unsigned int user_op_size, u
if (ins) {
if (bitness == 64) {
dflag = ins->structure->rex ? 8 : ins->structure->prefix[2] ? 2
: 4; /* in bytes */
dflag = ins->structure->raw.rex.W ? 8 : ins->structure->raw.prefixes[2].value ? 2
: 4;
stack_size = 8; /* in bytes */
} else {
/* We use the other operand and address size if the prefix is set */
if ((bitness == 32) ^ ins->structure->prefix[2]) {
if ((bitness == 32) ^ ins->structure->raw.prefixes[2].value) {
dflag = 4;
} else {
dflag = 2;
@ -1664,7 +1665,7 @@ IL_LIFTER(call) {
* - ZO
*/
IL_LIFTER(push) {
return x86_push_helper_impl(x86_il_get_op(0), ins->structure->operands->size, analysis->bits, ins, pc);
return x86_push_helper_impl(x86_il_get_op(0), ins->operands->size, analysis->bits, ins, pc);
}
/**
@ -1717,33 +1718,10 @@ IL_LIFTER(pushaw) {
return SEQ2(temp, push);
}
/**
* PUSHAD
* Push all general-purpose registers (32-bits)
* Encoding: ZO
*/
IL_LIFTER(pushal) {
if (analysis->bits != 32) {
return NULL;
}
RzILOpEffect *temp = SETL("_esp", x86_il_get_reg(X86_REG_ESP));
RzILOpEffect *push = x86_push_helper(x86_il_get_reg(X86_REG_EAX), 4);
push = SEQ2(push, x86_push_helper(x86_il_get_reg(X86_REG_ECX), 4));
push = SEQ2(push, x86_push_helper(x86_il_get_reg(X86_REG_EDX), 4));
push = SEQ2(push, x86_push_helper(x86_il_get_reg(X86_REG_EBX), 4));
push = SEQ2(push, x86_push_helper(VARL("_esp"), 4));
push = SEQ2(push, x86_push_helper(x86_il_get_reg(X86_REG_EBP), 4));
push = SEQ2(push, x86_push_helper(x86_il_get_reg(X86_REG_ESI), 4));
push = SEQ2(push, x86_push_helper(x86_il_get_reg(X86_REG_EDI), 4));
return SEQ2(temp, push);
}
#define RCX_MACRO() \
ut8 size_in_bytes = ins->structure->operands[0].size; \
ut8 size_in_bytes = ins->operands[0].size; \
ut8 size = size_in_bytes * BITS_PER_BYTE; \
ut8 shift_size = (size_in_bytes == 8 || (analysis->bits == 64 && ins->structure->rex)) ? 6 : 5; \
ut8 shift_size = (size_in_bytes == 8 || (analysis->bits == 64 && ins->structure->raw.rex.W)) ? 6 : 5; \
ut8 shift_max = size + 1; \
RzILOpEffect *pre_dest = SETL("_pre_dest", x86_il_get_op(0)); \
RzILOpEffect *shift = NULL; \
@ -1818,9 +1796,9 @@ IL_LIFTER(rcr) {
#undef RCX_MACRO
#define ROX_MACRO() \
ut8 size_in_bytes = ins->structure->operands[0].size; \
ut8 size_in_bytes = ins->operands[0].size; \
ut8 size = size_in_bytes * BITS_PER_BYTE; \
ut8 shift_size = (size_in_bytes == 8 || (analysis->bits == 64 && ins->structure->rex)) ? 6 : 5; \
ut8 shift_size = (size_in_bytes == 8 || (analysis->bits == 64 && ins->structure->raw.rex.W)) ? 6 : 5; \
ut8 shift_max = size; \
RzILOpEffect *pre_dest = SETL("_pre_dest", x86_il_get_op(0)); \
RzILOpEffect *shift = SETL("_shift", MOD(UNSIGNED(shift_size, x86_il_get_op_implicit(1, size_in_bytes)), UN(shift_size, shift_max)));
@ -1890,10 +1868,10 @@ IL_LIFTER(ret) {
RzILOpEffect *ret = SEQ2(SETL("tgt", ph.val), ph.eff);
if (ins->structure->op_count == 1) {
if (ins->structure->operand_count_visible == 1) {
/* Immediate operand (Encoding: I)
* Reduce RSP by that many bytes. */
ret = SEQ2(ret, x86_il_set_reg(X86_REG_RSP, ADD(x86_il_get_reg(X86_REG_RSP), UN(analysis->bits, ins->structure->operands[0].imm))));
ret = SEQ2(ret, x86_il_set_reg(X86_REG_RSP, ADD(x86_il_get_reg(X86_REG_RSP), UN(analysis->bits, imm_value(ins->operands[0], pc)))));
}
return SEQ2(ret, JMP(VARL("tgt")));
@ -1923,37 +1901,14 @@ IL_LIFTER(sahf) {
}
#define SHIFT_MACRO() \
ut8 size = ins->structure->operands[0].size * BITS_PER_BYTE; \
ut8 shift_size = ins->structure->operands[1].size * BITS_PER_BYTE; \
ut8 shift_mask = (analysis->bits == 64 && ins->structure->rex) ? 0x3f : 0x1f; \
ut8 size = ins->operands[0].size * BITS_PER_BYTE; \
ut8 shift_size = ins->operands[1].size * BITS_PER_BYTE; \
ut8 shift_mask = (analysis->bits == 64 && ins->structure->raw.rex.W) ? 0x3f : 0x1f; \
RzILOpEffect *pre_dest = SETL("_pre_dest", x86_il_get_op(0)); \
RzILOpEffect *shift = SETL("_shift", LOGAND(x86_il_get_op(1), UN(shift_size, shift_mask))); \
RzILOpEffect *set_dest = x86_il_set_op(0, VARL("_dest")); \
RzILOpEffect *set_flags = BRANCH(IS_ZERO(VARL("_shift")), NULL, x86_il_set_result_flags(VARL("_dest")));
/**
* SAL
* Shift arithmetically left (signed shift left)
* Encoding: M1, MC, MI
* (Functionally the same as SHL)
*/
IL_LIFTER(sal) {
SHIFT_MACRO();
RzILOpEffect *shifted = SETL("_shifted", SHIFTL0(UNSIGNED(size + 1, VARL("_pre_dest")), VARL("_shift")));
RzILOpEffect *result = SETL("_dest", UNSIGNED(size, VARL("_shifted")));
// if _shift == 0, CF is unaffected.
RzILOpEffect *set_cf = SETG(EFLAGS(CF), MSB(VARL("_shifted")));
// if _shift == 1, OF is set to 'CF xor MSB (after shift)'.
// otherwise, OF is undefined.
RzILOpEffect *set_of = SETG(EFLAGS(OF), XOR(VARG(EFLAGS(CF)), MSB(VARL("_dest"))));
return SEQ8(pre_dest, shift, shifted, result, set_cf, set_of, set_flags, set_dest);
}
/**
* SAR
* Shift arithmetically right (signed shift right)
@ -2034,7 +1989,7 @@ IL_LIFTER(sbb) {
RzILOpEffect *op2 = SETL("_op2", x86_il_get_op(1));
RzILOpPure *cf = VARG(EFLAGS(CF));
RzILOpEffect *diff = SETL("_diff", SUB(SUB(VARL("_op1"), VARL("_op2")), BOOL_TO_BV(cf, ins->structure->operands[0].size * BITS_PER_BYTE)));
RzILOpEffect *diff = SETL("_diff", SUB(SUB(VARL("_op1"), VARL("_op2")), BOOL_TO_BV(cf, ins->operands[0].size * BITS_PER_BYTE)));
RzILOpEffect *set_dest = x86_il_set_op(0, VARL("_diff"));
RzILOpEffect *set_res_flags = x86_il_set_result_flags(VARL("_diff"));
RzILOpEffect *set_arith_flags = x86_il_set_arithmetic_flags(VARL("_diff"), VARL("_op1"), VARL("_op2"), false);
@ -2067,7 +2022,7 @@ RzILOpEffect *x86_il_scas_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Reg mem_reg = X86_REG_RDI;
ut8 mem_size = 64;
/* Address override prefix: 67H */
if (ins->structure->prefix[3]) {
if (ins->structure->raw.prefixes[3].value) {
mem_reg = X86_REG_EDI;
mem_size = 32;
}
@ -2089,15 +2044,15 @@ RzILOpEffect *x86_il_scas_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Reg mem_reg = X86_REG_EDI;
ut8 mem_size = 32;
/* Check bitness and address override prefix: 67H */
if (analysis->bits == 16 || ins->structure->prefix[3]) {
if (analysis->bits == 16 || ins->structure->raw.prefixes[3].value) {
mem_reg = X86_REG_DI;
mem_size = 16;
}
X86Mem src_mem;
src_mem.base = mem_reg;
src_mem.disp = 0;
src_mem.index = X86_REG_INVALID;
src_mem.disp.value = 0;
src_mem.index = X86_REG_NONE;
src_mem.scale = 1;
src_mem.segment = X86_REG_ES;
@ -2211,7 +2166,7 @@ RzILOpEffect *x86_il_stos_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Reg mem_reg = X86_REG_RDI;
ut8 mem_size = 64;
/* Address override prefix: 67H */
if (ins->structure->prefix[3]) {
if (ins->structure->raw.prefixes[3].value) {
mem_reg = X86_REG_EDI;
mem_size = 32;
}
@ -2227,15 +2182,15 @@ RzILOpEffect *x86_il_stos_helper(const X86ILIns *ins, ut64 pc, RzAnalysis *analy
X86Reg mem_reg = X86_REG_EDI;
ut8 mem_size = 32;
/* Check bitness and address override prefix: 67H */
if (analysis->bits == 16 || ins->structure->prefix[3]) {
if (analysis->bits == 16 || ins->structure->raw.prefixes[3].value) {
mem_reg = X86_REG_DI;
mem_size = 16;
}
X86Mem src_mem;
src_mem.base = mem_reg;
src_mem.disp = 0;
src_mem.index = X86_REG_INVALID;
src_mem.disp.value = 0;
src_mem.index = X86_REG_NONE;
src_mem.scale = 1;
src_mem.segment = X86_REG_ES;
@ -2323,7 +2278,7 @@ IL_LIFTER(test) {
* Wait until not busy
* ZO
*/
IL_LIFTER(wait) {
IL_LIFTER(fwait) {
/* NOP seems to be a reasonable implementation */
return NOP();
}
@ -2346,16 +2301,16 @@ IL_LIFTER(xchg) {
* Table look-up translation
* Encoding: ZO
*/
IL_LIFTER(xlatb) {
IL_LIFTER(xlat) {
X86Mem mem;
mem.disp = 0;
mem.index = X86_REG_INVALID;
mem.disp.value = 0;
mem.index = X86_REG_NONE;
mem.scale = 1;
mem.segment = X86_REG_DS;
mem.base = X86_REG_EBX;
if (analysis->bits == 64) {
mem.segment = X86_REG_INVALID;
mem.segment = X86_REG_NONE;
mem.base = X86_REG_RBX;
} else if (analysis->bits == 16) {
mem.base = X86_REG_BX;
@ -2391,10 +2346,14 @@ IL_LIFTER(xor) {
IL_LIFTER(bound) {
RzILOpEffect *index = SETL("_index", x86_il_get_op(0));
X86Mem mem = ins->structure->operands[1].mem;
RzILOpEffect *lower = SETL("_lower", LOADW(ins->structure->operands[0].size * BITS_PER_BYTE, x86_il_get_memaddr(mem)));
mem.disp += ins->structure->operands[1].size / mem.scale;
RzILOpEffect *upper = SETL("_upper", LOADW(ins->structure->operands[0].size * BITS_PER_BYTE, x86_il_get_memaddr(mem)));
X86Mem mem = ins->operands[1].mem;
RzILOpEffect *lower = SETL("_lower", LOADW(ins->operands[0].size * BITS_PER_BYTE, x86_il_get_memaddr(mem)));
if (mem.scale != 0) {
mem.disp.value += ins->operands[1].size / mem.scale;
} else {
mem.disp.value += ins->operands[1].size;
}
RzILOpEffect *upper = SETL("_upper", LOADW(ins->operands[0].size * BITS_PER_BYTE, x86_il_get_memaddr(mem)));
RzILOpBool *cond = OR(ULT(VARL("_index"), VARL("_lower")), UGT(VARL("_index"), VARL("_upper")));
@ -2421,7 +2380,7 @@ IL_LIFTER(enter) {
switch (analysis->bits) {
case 64:
/* Operand-size override (66H) */
if (ins->structure->prefix[2]) {
if (ins->structure->raw.prefixes[2].value) {
bp_reg = X86_REG_EBP;
bp_size = 4;
} else {
@ -2431,7 +2390,7 @@ IL_LIFTER(enter) {
break;
case 32:
/* Operand-size override (66H) */
if (ins->structure->prefix[2]) {
if (ins->structure->raw.prefixes[2].value) {
bp_reg = X86_REG_BP;
bp_size = 2;
} else {
@ -2483,7 +2442,7 @@ IL_LIFTER(leave) {
switch (analysis->bits) {
case 64:
/* Operand-size override (66H) */
if (ins->structure->prefix[2]) {
if (ins->structure->raw.prefixes[2].value) {
bp_reg = X86_REG_EBP;
bp_size = 4;
} else {
@ -2493,7 +2452,7 @@ IL_LIFTER(leave) {
break;
case 32:
/* Operand-size override (66H) */
if (ins->structure->prefix[2]) {
if (ins->structure->raw.prefixes[2].value) {
bp_reg = X86_REG_BP;
bp_size = 2;
} else {

7
librz/arch/isa/x86/x86_dwarf_regnum_table.h
View file

@ -2,6 +2,11 @@
// SPDX-FileCopyrightText: 2024 Billow <billow.fun@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef X86_DWARF_REGNUM_TABLE_H
#define X86_DWARF_REGNUM_TABLE_H
#include <rz_types_base.h>
/* x86_64 https://software.intel.com/sites/default/files/article/402129/mpx-linux64-abi.pdf */
static const char *map_dwarf_reg_to_x86_64_reg(ut32 reg_num) {
switch (reg_num) {
@ -82,3 +87,5 @@ static const char *map_dwarf_reg_to_x86_reg(ut32 reg_num) {
return "unsupported_reg";
}
}
#endif // X86_DWARF_REGNUM_TABLE_H

36
librz/arch/isa/x86/x86_il.c
View file

@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: 2023 Dhruv Maroo <dhruvmaru007@gmail.com>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#include "x86_il.h"
@ -46,7 +47,6 @@ const char *x86_bound_regs_16[] = {
"bx", /* X86_REG_BX */
"cx", /* X86_REG_CX */
"dx", /* X86_REG_DX */
// "ip", /* X86_REG_IP */
"sp", /* X86_REG_SP */
"bp", /* X86_REG_BP */
"si", /* X86_REG_SI */
@ -63,7 +63,6 @@ const char *x86_bound_regs_32[] = {
"ebx", /* X86_REG_EBX */
"ecx", /* X86_REG_ECX */
"edx", /* X86_REG_EDX */
// "eip", /* X86_REG_EIP */
"esp", /* X86_REG_ESP */
"ebp", /* X86_REG_EBP */
"esi", /* X86_REG_ESI */
@ -87,7 +86,6 @@ const char *x86_bound_regs_64[] = {
"rbx", /* X86_REG_RBX */
"rcx", /* X86_REG_RCX */
"rdx", /* X86_REG_RDX */
// "rip", /* X86_REG_RIP */
"rsp", /* X86_REG_RSP */
"rbp", /* X86_REG_RBP */
"rsi", /* X86_REG_RSI */
@ -116,7 +114,7 @@ typedef RzILOpEffect *(*x86_il_ins)(const X86ILIns *, ut64, RzAnalysis *, X86ILC
/**
* \brief RzIL handlers for x86 instructions
*/
x86_il_ins x86_ins[X86_INS_ENDING] = {
x86_il_ins x86_ins[X86_INS_MAX_VALUE] = {
[X86_INS_INVALID] = x86_il_invalid,
[X86_INS_AAA] = x86_il_aaa,
[X86_INS_AAD] = x86_il_aad,
@ -133,16 +131,16 @@ x86_il_ins x86_ins[X86_INS_ENDING] = {
[X86_INS_CLI] = x86_il_cli,
[X86_INS_CMC] = x86_il_cmc,
[X86_INS_CMP] = x86_il_cmp,
[X86_INS_CMOVA] = x86_il_cmov,
[X86_INS_CMOVAE] = x86_il_cmov,
[X86_INS_CMOVNBE] = x86_il_cmov,
[X86_INS_CMOVNB] = x86_il_cmov,
[X86_INS_CMOVB] = x86_il_cmov,
[X86_INS_CMOVBE] = x86_il_cmov,
[X86_INS_CMOVE] = x86_il_cmov,
[X86_INS_CMOVG] = x86_il_cmov,
[X86_INS_CMOVGE] = x86_il_cmov,
[X86_INS_CMOVZ] = x86_il_cmov,
[X86_INS_CMOVNLE] = x86_il_cmov,
[X86_INS_CMOVNL] = x86_il_cmov,
[X86_INS_CMOVL] = x86_il_cmov,
[X86_INS_CMOVLE] = x86_il_cmov,
[X86_INS_CMOVNE] = x86_il_cmov,
[X86_INS_CMOVNZ] = x86_il_cmov,
[X86_INS_CMOVNO] = x86_il_cmov,
[X86_INS_CMOVNP] = x86_il_cmov,
[X86_INS_CMOVNS] = x86_il_cmov,
@ -196,7 +194,6 @@ x86_il_ins x86_ins[X86_INS_ENDING] = {
[X86_INS_LOOPE] = x86_il_loope,
[X86_INS_LOOPNE] = x86_il_loopne,
[X86_INS_MOV] = x86_il_mov,
[X86_INS_MOVABS] = x86_il_mov,
[X86_INS_MOVSB] = x86_il_movsb,
[X86_INS_MOVSW] = x86_il_movsw,
[X86_INS_MOVSD] = x86_il_movsd,
@ -218,15 +215,13 @@ x86_il_ins x86_ins[X86_INS_ENDING] = {
[X86_INS_PUSHF] = x86_il_pushf,
[X86_INS_PUSHFD] = x86_il_pushfd,
[X86_INS_PUSHFQ] = x86_il_pushfq,
[X86_INS_PUSHAW] = x86_il_pushaw,
[X86_INS_PUSHAL] = x86_il_pushal,
[X86_INS_PUSHAD] = x86_il_pushaw,
[X86_INS_RCL] = x86_il_rcl,
[X86_INS_RCR] = x86_il_rcr,
[X86_INS_ROL] = x86_il_rol,
[X86_INS_ROR] = x86_il_ror,
[X86_INS_RET] = x86_il_ret,
[X86_INS_SAHF] = x86_il_sahf,
[X86_INS_SAL] = x86_il_sal,
[X86_INS_SAR] = x86_il_sar,
[X86_INS_SHL] = x86_il_shl,
[X86_INS_SHR] = x86_il_shr,
@ -245,9 +240,9 @@ x86_il_ins x86_ins[X86_INS_ENDING] = {
[X86_INS_STOSW] = x86_il_stosw,
[X86_INS_SUB] = x86_il_sub,
[X86_INS_TEST] = x86_il_test,
[X86_INS_WAIT] = x86_il_wait,
[X86_INS_FWAIT] = x86_il_fwait,
[X86_INS_XCHG] = x86_il_xchg,
[X86_INS_XLATB] = x86_il_xlatb,
[X86_INS_XLAT] = x86_il_xlat,
[X86_INS_XOR] = x86_il_xor,
[X86_INS_BOUND] = x86_il_bound,
[X86_INS_ENTER] = x86_il_enter,
@ -302,10 +297,7 @@ x86_il_ins x86_ins[X86_INS_ENDING] = {
[X86_INS_FCOMPP] = x86_il_fcompp,
[X86_INS_FICOMP] = x86_il_ficomp,
[X86_INS_FCOMI] = x86_il_fcomi,
#if CS_API_MAJOR > 4
[X86_INS_FCOMPI] = x86_il_fcomip,
[X86_INS_FUCOMPI] = x86_il_fcomip,
#endif
/* Using the same FCOM & FCOMI family IL lifters for FUCOM & FUCOMI family instructions
* since we don't support invalid arithmetic operand exceptions (#IA) anyways. */
[X86_INS_FUCOM] = x86_il_fcom,
@ -321,8 +313,6 @@ x86_il_ins x86_ins[X86_INS_ENDING] = {
/* unimplemented instructions */
[X86_INS_IRET] = x86_il_unimpl,
[X86_INS_RETF] = x86_il_unimpl,
[X86_INS_RETFQ] = x86_il_unimpl,
[X86_INS_INSB] = x86_il_unimpl,
[X86_INS_INSW] = x86_il_unimpl,
[X86_INS_OUTSB] = x86_il_unimpl,
@ -339,7 +329,7 @@ void label_port(RzILVM *vm, RzILOpEffect *op);
RZ_IPI bool rz_x86_il_opcode(RZ_NONNULL RzAnalysis *analysis, RZ_NONNULL RzAnalysisOp *aop, ut64 pc, RZ_BORROW RZ_NONNULL const X86ILIns *ins) {
rz_return_val_if_fail(analysis && aop && ins && ins->ins_size > 0, false);
if (ins->mnem >= X86_INS_ENDING) {
if (ins->mnem >= X86_INS_MAX_VALUE) {
RZ_LOG_ERROR("RzIL: x86: Invalid instruction type %d\n", ins->mnem);
return false;
}

17
librz/arch/isa/x86/x86_il.h
View file

@ -1,4 +1,5 @@
// SPDX-FileCopyrightText: 2023 Dhruv Maroo <dhruvmaru007@gmail.com>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef RZIL_ANALYSIS_X86_IL_H
@ -6,20 +7,20 @@
#include <rz_lib.h>
#include <rz_analysis.h>
#include <capstone/capstone.h>
#include <capstone/x86.h>
#include <Zydis.h>
#define BITS_PER_BYTE 8
#define GPR_FAMILY_COUNT 10
typedef x86_reg X86Reg;
typedef cs_x86_op X86Op;
typedef x86_op_mem X86Mem;
typedef cs_x86 X86Ins;
typedef x86_insn X86InsMnem;
typedef ZydisRegister X86Reg;
typedef ZydisDecodedOperand X86Op;
typedef ZydisDecodedOperandMem X86Mem;
typedef ZydisDecodedInstruction X86Ins;
typedef ZydisMnemonic X86InsMnem;
typedef struct x86_il_instruction_t {
const X86Ins *structure; ///< Capstone instruction data
const X86Op *operands;
X86InsMnem mnem; ///< Instruction mnemonic (enum)
ut8 ins_size; ///< Size of instruction (in bytes)
} X86ILIns;
@ -35,4 +36,6 @@ typedef struct x86_il_context_t {
RZ_IPI bool rz_x86_il_opcode(RZ_NONNULL RzAnalysis *analysis, RZ_NONNULL RzAnalysisOp *aop, ut64 pc, RZ_BORROW RZ_NONNULL const X86ILIns *ins);
RZ_IPI RzAnalysisILConfig *rz_x86_il_config(RZ_NONNULL RzAnalysis *analysis);
#define imm_value(op, pc) (ut64)((op.imm.is_relative) ? (op.imm.value.s + pc) : (op.imm.value.u))
#endif /* RZIL_ANALYSIS_X86_IL_H */

778
librz/arch/isa/x86/x86_mnemonics.h Normal file
View file

@ -0,0 +1,778 @@
// SPDX-FileCopyrightText: 2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef X86_MNEMONIC_H
#define X86_MNEMONIC_H
#include <Zydis.h>
// Instructions
#define X86_INS_ENDING ZYDIS_MNEMONIC_MAX_VALUE
#define X86_INS_INVALID ZYDIS_MNEMONIC_INVALID
#define X86_INS_AAA ZYDIS_MNEMONIC_AAA
#define X86_INS_AAD ZYDIS_MNEMONIC_AAD
#define X86_INS_AAM ZYDIS_MNEMONIC_AAM
#define X86_INS_AAS ZYDIS_MNEMONIC_AAS
#define X86_INS_ADC ZYDIS_MNEMONIC_ADC
#define X86_INS_ADD ZYDIS_MNEMONIC_ADD
#define X86_INS_AND ZYDIS_MNEMONIC_AND
#define X86_INS_BSF ZYDIS_MNEMONIC_BSF
#define X86_INS_CALL ZYDIS_MNEMONIC_CALL
#define X86_INS_CBW ZYDIS_MNEMONIC_CBW
#define X86_INS_CLC ZYDIS_MNEMONIC_CLC
#define X86_INS_CLD ZYDIS_MNEMONIC_CLD
#define X86_INS_CLI ZYDIS_MNEMONIC_CLI
#define X86_INS_CMC ZYDIS_MNEMONIC_CMC
#define X86_INS_CMP ZYDIS_MNEMONIC_CMP
#define X86_INS_CMOVA ZYDIS_MNEMONIC_CMOVNBE
#define X86_INS_CMOVAE ZYDIS_MNEMONIC_CMOVNB
#define X86_INS_CMOVB ZYDIS_MNEMONIC_CMOVB
#define X86_INS_CMOVBE ZYDIS_MNEMONIC_CMOVBE
#define X86_INS_CMOVE ZYDIS_MNEMONIC_CMOVZ
#define X86_INS_CMOVG ZYDIS_MNEMONIC_CMOVNLE
#define X86_INS_CMOVGE ZYDIS_MNEMONIC_CMOVNL
#define X86_INS_CMOVL ZYDIS_MNEMONIC_CMOVL
#define X86_INS_CMOVLE ZYDIS_MNEMONIC_CMOVLE
#define X86_INS_CMOVNE ZYDIS_MNEMONIC_CMOVNZ
#define X86_INS_CMOVNO ZYDIS_MNEMONIC_CMOVNO
#define X86_INS_CMOVNP ZYDIS_MNEMONIC_CMOVNP
#define X86_INS_CMOVNS ZYDIS_MNEMONIC_CMOVNS
#define X86_INS_CMOVO ZYDIS_MNEMONIC_CMOVO
#define X86_INS_CMOVP ZYDIS_MNEMONIC_CMOVP
#define X86_INS_CMOVS ZYDIS_MNEMONIC_CMOVS
#define X86_INS_CMPSB ZYDIS_MNEMONIC_CMPSB
#define X86_INS_CMPSW ZYDIS_MNEMONIC_CMPSW
#define X86_INS_CMPSD ZYDIS_MNEMONIC_CMPSD
#define X86_INS_CMPSQ ZYDIS_MNEMONIC_CMPSQ
#define X86_INS_DAA ZYDIS_MNEMONIC_DAA
#define X86_INS_DAS ZYDIS_MNEMONIC_DAS
#define X86_INS_DEC ZYDIS_MNEMONIC_DEC
#define X86_INS_DIV ZYDIS_MNEMONIC_DIV
#define X86_INS_HLT ZYDIS_MNEMONIC_HLT
#define X86_INS_IDIV ZYDIS_MNEMONIC_IDIV
#define X86_INS_IMUL ZYDIS_MNEMONIC_IMUL
#define X86_INS_IN ZYDIS_MNEMONIC_IN
#define X86_INS_INC ZYDIS_MNEMONIC_INC
#define X86_INS_INT ZYDIS_MNEMONIC_INT
#define X86_INS_INTO ZYDIS_MNEMONIC_INTO
#define X86_INS_JA ZYDIS_MNEMONIC_JNBE
#define X86_INS_JAE ZYDIS_MNEMONIC_JNB
#define X86_INS_JB ZYDIS_MNEMONIC_JB
#define X86_INS_JBE ZYDIS_MNEMONIC_JBE
#define X86_INS_JCXZ ZYDIS_MNEMONIC_JCXZ
#define X86_INS_JECXZ ZYDIS_MNEMONIC_JECXZ
#define X86_INS_JRCXZ ZYDIS_MNEMONIC_JRCXZ
#define X86_INS_JE ZYDIS_MNEMONIC_JZ
#define X86_INS_JG ZYDIS_MNEMONIC_JNLE
#define X86_INS_JGE ZYDIS_MNEMONIC_JNL
#define X86_INS_JL ZYDIS_MNEMONIC_JL
#define X86_INS_JLE ZYDIS_MNEMONIC_JLE
#define X86_INS_JNE ZYDIS_MNEMONIC_JNZ
#define X86_INS_JNO ZYDIS_MNEMONIC_JNO
#define X86_INS_JNP ZYDIS_MNEMONIC_JNP
#define X86_INS_JNS ZYDIS_MNEMONIC_JNS
#define X86_INS_JO ZYDIS_MNEMONIC_JO
#define X86_INS_JP ZYDIS_MNEMONIC_JP
#define X86_INS_JS ZYDIS_MNEMONIC_JS
#define X86_INS_JMP ZYDIS_MNEMONIC_JMP
#define X86_INS_LAHF ZYDIS_MNEMONIC_LAHF
#define X86_INS_LDS ZYDIS_MNEMONIC_LDS
#define X86_INS_LEA ZYDIS_MNEMONIC_LEA
#define X86_INS_LES ZYDIS_MNEMONIC_LES
#define X86_INS_LODSB ZYDIS_MNEMONIC_LODSB
#define X86_INS_LODSW ZYDIS_MNEMONIC_LODSW
#define X86_INS_LODSD ZYDIS_MNEMONIC_LODSD
#define X86_INS_LODSQ ZYDIS_MNEMONIC_LODSQ
#define X86_INS_LOOP ZYDIS_MNEMONIC_LOOP
#define X86_INS_LOOPE ZYDIS_MNEMONIC_LOOPE
#define X86_INS_LOOPNE ZYDIS_MNEMONIC_LOOPNE
#define X86_INS_MOV ZYDIS_MNEMONIC_MOV
#define X86_INS_MOVABS ZYDIS_MNEMONIC_MOVABS
#define X86_INS_MOVSB ZYDIS_MNEMONIC_MOVSB
#define X86_INS_MOVSW ZYDIS_MNEMONIC_MOVSW
#define X86_INS_MOVSD ZYDIS_MNEMONIC_MOVSD
#define X86_INS_MOVSQ ZYDIS_MNEMONIC_MOVSQ
#define X86_INS_MOVSX ZYDIS_MNEMONIC_MOVSX
#define X86_INS_MOVSXD ZYDIS_MNEMONIC_MOVSXD
#define X86_INS_MOVZX ZYDIS_MNEMONIC_MOVZX
#define X86_INS_MUL ZYDIS_MNEMONIC_MUL
#define X86_INS_NEG ZYDIS_MNEMONIC_NEG
#define X86_INS_NOP ZYDIS_MNEMONIC_NOP
#define X86_INS_NOT ZYDIS_MNEMONIC_NOT
#define X86_INS_OR ZYDIS_MNEMONIC_OR
#define X86_INS_OUT ZYDIS_MNEMONIC_OUT
#define X86_INS_POP ZYDIS_MNEMONIC_POP
#define X86_INS_POPF ZYDIS_MNEMONIC_POPF
#define X86_INS_POPFD ZYDIS_MNEMONIC_POPFD
#define X86_INS_POPFQ ZYDIS_MNEMONIC_POPFQ
#define X86_INS_PUSH ZYDIS_MNEMONIC_PUSH
#define X86_INS_PUSHF ZYDIS_MNEMONIC_PUSHF
#define X86_INS_PUSHFD ZYDIS_MNEMONIC_PUSHFD
#define X86_INS_PUSHFQ ZYDIS_MNEMONIC_PUSHFQ
#define X86_INS_PUSHAW ZYDIS_MNEMONIC_PUSHAD
#define X86_INS_PUSHAL ZYDIS_MNEMONIC_PUSHAL
#define X86_INS_RCL ZYDIS_MNEMONIC_RCL
#define X86_INS_RCR ZYDIS_MNEMONIC_RCR
#define X86_INS_ROL ZYDIS_MNEMONIC_ROL
#define X86_INS_ROR ZYDIS_MNEMONIC_ROR
#define X86_INS_RET ZYDIS_MNEMONIC_RET
#define X86_INS_SAHF ZYDIS_MNEMONIC_SAHF
#define X86_INS_SAL ZYDIS_MNEMONIC_SAL
#define X86_INS_SAR ZYDIS_MNEMONIC_SAR
#define X86_INS_SHL ZYDIS_MNEMONIC_SHL
#define X86_INS_SHR ZYDIS_MNEMONIC_SHR
#define X86_INS_SBB ZYDIS_MNEMONIC_SBB
#define X86_INS_SCASB ZYDIS_MNEMONIC_SCASB
#define X86_INS_SCASW ZYDIS_MNEMONIC_SCASW
#define X86_INS_SCASD ZYDIS_MNEMONIC_SCASD
#define X86_INS_SCASQ ZYDIS_MNEMONIC_SCASQ
#define X86_INS_STAC ZYDIS_MNEMONIC_STAC
#define X86_INS_STC ZYDIS_MNEMONIC_STC
#define X86_INS_STD ZYDIS_MNEMONIC_STD
#define X86_INS_STI ZYDIS_MNEMONIC_STI
#define X86_INS_STOSB ZYDIS_MNEMONIC_STOSB
#define X86_INS_STOSD ZYDIS_MNEMONIC_STOSD
#define X86_INS_STOSQ ZYDIS_MNEMONIC_STOSQ
#define X86_INS_STOSW ZYDIS_MNEMONIC_STOSW
#define X86_INS_SUB ZYDIS_MNEMONIC_SUB
#define X86_INS_TEST ZYDIS_MNEMONIC_TEST
#define X86_INS_WAIT ZYDIS_MNEMONIC_FWAIT
#define X86_INS_XCHG ZYDIS_MNEMONIC_XCHG
#define X86_INS_XLATB ZYDIS_MNEMONIC_XLAT
#define X86_INS_XOR ZYDIS_MNEMONIC_XOR
#define X86_INS_BOUND ZYDIS_MNEMONIC_BOUND
#define X86_INS_ENTER ZYDIS_MNEMONIC_ENTER
#define X86_INS_LEAVE ZYDIS_MNEMONIC_LEAVE
#define X86_INS_FNINIT ZYDIS_MNEMONIC_FNINIT
#define X86_INS_FLDCW ZYDIS_MNEMONIC_FLDCW
#define X86_INS_FNSTCW ZYDIS_MNEMONIC_FNSTCW
#define X86_INS_FNSTSW ZYDIS_MNEMONIC_FNSTSW
#define X86_INS_FNCLEX ZYDIS_MNEMONIC_FNCLEX
#define X86_INS_FLD ZYDIS_MNEMONIC_FLD
#define X86_INS_FST ZYDIS_MNEMONIC_FST
#define X86_INS_FSTP ZYDIS_MNEMONIC_FSTP
#define X86_INS_FLD1 ZYDIS_MNEMONIC_FLD1
#define X86_INS_FLDZ ZYDIS_MNEMONIC_FLDZ
#define X86_INS_FLDL2T ZYDIS_MNEMONIC_FLDL2T
#define X86_INS_FLDL2E ZYDIS_MNEMONIC_FLDL2E
#define X86_INS_FLDPI ZYDIS_MNEMONIC_FLDPI
#define X86_INS_FLDLG2 ZYDIS_MNEMONIC_FLDLG2
#define X86_INS_FLDLN2 ZYDIS_MNEMONIC_FLDLN2
#define X86_INS_FXCH ZYDIS_MNEMONIC_FXCH
#define X86_INS_FILD ZYDIS_MNEMONIC_FILD
#define X86_INS_FIST ZYDIS_MNEMONIC_FIST
#define X86_INS_FISTP ZYDIS_MNEMONIC_FISTP
#define X86_INS_FBLD ZYDIS_MNEMONIC_FBLD
#define X86_INS_FBSTP ZYDIS_MNEMONIC_FBSTP
#define X86_INS_FABS ZYDIS_MNEMONIC_FABS
#define X86_INS_FADD ZYDIS_MNEMONIC_FADD
#define X86_INS_FIADD ZYDIS_MNEMONIC_FIADD
#define X86_INS_FMUL ZYDIS_MNEMONIC_FMUL
#define X86_INS_FMULP ZYDIS_MNEMONIC_FMULP
#define X86_INS_FIMUL ZYDIS_MNEMONIC_FIMUL
#define X86_INS_FSUB ZYDIS_MNEMONIC_FSUB
#define X86_INS_FSUBP ZYDIS_MNEMONIC_FSUBP
#define X86_INS_FISUB ZYDIS_MNEMONIC_FISUB
#define X86_INS_FSUBR ZYDIS_MNEMONIC_FSUBR
#define X86_INS_FSUBRP ZYDIS_MNEMONIC_FSUBRP
#define X86_INS_FISUBR ZYDIS_MNEMONIC_FISUBR
#define X86_INS_FDIV ZYDIS_MNEMONIC_FDIV
#define X86_INS_FDIVP ZYDIS_MNEMONIC_FDIVP
#define X86_INS_FIDIV ZYDIS_MNEMONIC_FIDIV
#define X86_INS_FDIVR ZYDIS_MNEMONIC_FDIVR
#define X86_INS_FDIVRP ZYDIS_MNEMONIC_FDIVRP
#define X86_INS_FIDIVR ZYDIS_MNEMONIC_FIDIVR
#define X86_INS_FCOM ZYDIS_MNEMONIC_FCOM
#define X86_INS_FCOMP ZYDIS_MNEMONIC_FCOMP
#define X86_INS_FICOM ZYDIS_MNEMONIC_FICOM
#define X86_INS_FCOMPP ZYDIS_MNEMONIC_FCOMPP
#define X86_INS_FICOMP ZYDIS_MNEMONIC_FICOMP
#define X86_INS_FCOMI ZYDIS_MNEMONIC_FCOMI
#define X86_INS_FCOMPI ZYDIS_MNEMONIC_FCOMPI
#define X86_INS_FUCOMPI ZYDIS_MNEMONIC_FUCOMPI
#define X86_INS_FUCOM ZYDIS_MNEMONIC_FUCOM
#define X86_INS_FUCOMP ZYDIS_MNEMONIC_FUCOMP
#define X86_INS_FUCOMPP ZYDIS_MNEMONIC_FUCOMPP
#define X86_INS_FUCOMI ZYDIS_MNEMONIC_FUCOMI
#define X86_INS_FCHS ZYDIS_MNEMONIC_FCHS
#define X86_INS_FTST ZYDIS_MNEMONIC_FTST
#define X86_INS_FRNDINT ZYDIS_MNEMONIC_FRNDINT
#define X86_INS_FSQRT ZYDIS_MNEMONIC_FSQRT
#define X86_INS_FNOP ZYDIS_MNEMONIC_FNOP
#define X86_INS_FISTTP ZYDIS_MNEMONIC_FISTTP
#define X86_INS_IRET ZYDIS_MNEMONIC_IRET
#define X86_INS_RETF ZYDIS_MNEMONIC_RETF
#define X86_INS_RETFQ ZYDIS_MNEMONIC_RETFQ
#define X86_INS_INSB ZYDIS_MNEMONIC_INSB
#define X86_INS_INSW ZYDIS_MNEMONIC_INSW
#define X86_INS_OUTSB ZYDIS_MNEMONIC_OUTSB
#define X86_INS_OUTSW ZYDIS_MNEMONIC_OUTSW
#define X86_INS_FLDENV ZYDIS_MNEMONIC_FLDENV
#define X86_INS_FNSTENV ZYDIS_MNEMONIC_FNSTENV
#define X86_INS_FNSAVE ZYDIS_MNEMONIC_FNSAVE
#define X86_INS_FRSTOR ZYDIS_MNEMONIC_FRSTOR
#define X86_INS_PAUSE ZYDIS_MNEMONIC_PAUSE
#define X86_INS_FDECSTP ZYDIS_MNEMONIC_FDECSTP
#define X86_INS_FEMMS ZYDIS_MNEMONIC_FEMMS
#define X86_INS_FFREE ZYDIS_MNEMONIC_FFREE
#define X86_INS_FINCSTP ZYDIS_MNEMONIC_FINCSTP
#define X86_INS_FPATAN ZYDIS_MNEMONIC_FPATAN
#define X86_INS_FPREM ZYDIS_MNEMONIC_FPREM
#define X86_INS_FPREM1 ZYDIS_MNEMONIC_FPREM1
#define X86_INS_FPTAN ZYDIS_MNEMONIC_FPTAN
#define X86_INS_FFREEP ZYDIS_MNEMONIC_FFREEP
#define X86_INS_FSCALE ZYDIS_MNEMONIC_FSCALE
#define X86_INS_FSETPM287_NOP ZYDIS_MNEMONIC_FSETPM287_NOP
#define X86_INS_FSINCOS ZYDIS_MNEMONIC_FSINCOS
#define X86_INS_FXAM ZYDIS_MNEMONIC_FXAM
#define X86_INS_FXSAVE ZYDIS_MNEMONIC_FXSAVE
#define X86_INS_FXSAVE64 ZYDIS_MNEMONIC_FXSAVE64
#define X86_INS_FXTRACT ZYDIS_MNEMONIC_FXTRACT
#define X86_INS_FYL2X ZYDIS_MNEMONIC_FYL2X
#define X86_INS_FYL2XP1 ZYDIS_MNEMONIC_FYL2XP1
#define X86_INS_FSTPNCE ZYDIS_MNEMONIC_FSTPNCE
#define X86_INS_FXRSTOR ZYDIS_MNEMONIC_FXRSTOR
#define X86_INS_FXRSTOR64 ZYDIS_MNEMONIC_FXRSTOR64
#define X86_INS_CLAC ZYDIS_MNEMONIC_CLAC
#define X86_INS_CLGI ZYDIS_MNEMONIC_CLGI
#define X86_INS_CLTS ZYDIS_MNEMONIC_CLTS
#define X86_INS_CLWB ZYDIS_MNEMONIC_CLWB
#define X86_INS_STGI ZYDIS_MNEMONIC_STGI
#define X86_INS_SETNZ ZYDIS_MNEMONIC_SETNZ
#define X86_INS_SETNO ZYDIS_MNEMONIC_SETNO
#define X86_INS_SETNP ZYDIS_MNEMONIC_SETNP
#define X86_INS_SETNS ZYDIS_MNEMONIC_SETNS
#define X86_INS_SETO ZYDIS_MNEMONIC_SETO
#define X86_INS_SETP ZYDIS_MNEMONIC_SETP
#define X86_INS_SETS ZYDIS_MNEMONIC_SETS
#define X86_INS_SETL ZYDIS_MNEMONIC_SETL
#define X86_INS_SETLE ZYDIS_MNEMONIC_SETLE
#define X86_INS_SETB ZYDIS_MNEMONIC_SETB
#define X86_INS_SETNLE ZYDIS_MNEMONIC_SETNLE
#define X86_INS_SETNB ZYDIS_MNEMONIC_SETNB
#define X86_INS_SETNBE ZYDIS_MNEMONIC_SETNBE
#define X86_INS_SETBE ZYDIS_MNEMONIC_SETBE
#define X86_INS_SETZ ZYDIS_MNEMONIC_SETZ
#define X86_INS_SETNL ZYDIS_MNEMONIC_SETNL
#define X86_INS_FCMOVBE ZYDIS_MNEMONIC_FCMOVBE
#define X86_INS_FCMOVB ZYDIS_MNEMONIC_FCMOVB
#define X86_INS_FCMOVNBE ZYDIS_MNEMONIC_FCMOVNBE
#define X86_INS_FCMOVNB ZYDIS_MNEMONIC_FCMOVNB
#define X86_INS_FCMOVE ZYDIS_MNEMONIC_FCMOVE
#define X86_INS_FCMOVNE ZYDIS_MNEMONIC_FCMOVNE
#define X86_INS_FCMOVNU ZYDIS_MNEMONIC_FCMOVNU
#define X86_INS_FCMOVU ZYDIS_MNEMONIC_FCMOVU
#define X86_INS_CMOVNBE ZYDIS_MNEMONIC_CMOVNBE
#define X86_INS_CMOVNB ZYDIS_MNEMONIC_CMOVNB
#define X86_INS_CMOVZ ZYDIS_MNEMONIC_CMOVZ
#define X86_INS_CMOVNLE ZYDIS_MNEMONIC_CMOVNLE
#define X86_INS_CMOVNL ZYDIS_MNEMONIC_CMOVNL
#define X86_INS_CMOVNZ ZYDIS_MNEMONIC_CMOVNZ
#define X86_INS_PEXTRB ZYDIS_MNEMONIC_PEXTRB
#define X86_INS_COMISS ZYDIS_MNEMONIC_COMISS
#define X86_INS_UCOMISS ZYDIS_MNEMONIC_UCOMISS
#define X86_INS_VCOMISS ZYDIS_MNEMONIC_VCOMISS
#define X86_INS_VUCOMISS ZYDIS_MNEMONIC_VUCOMISS
#define X86_INS_MOVSS ZYDIS_MNEMONIC_MOVSS
#define X86_INS_MOVAPS ZYDIS_MNEMONIC_MOVAPS
#define X86_INS_MOVAPD ZYDIS_MNEMONIC_MOVAPD
#define X86_INS_MOVUPS ZYDIS_MNEMONIC_MOVUPS
#define X86_INS_MOVHPD ZYDIS_MNEMONIC_MOVHPD
#define X86_INS_MOVHPS ZYDIS_MNEMONIC_MOVHPS
#define X86_INS_MOVLPD ZYDIS_MNEMONIC_MOVLPD
#define X86_INS_MOVLPS ZYDIS_MNEMONIC_MOVLPS
#define X86_INS_MOVBE ZYDIS_MNEMONIC_MOVBE
#define X86_INS_MOVQ ZYDIS_MNEMONIC_MOVQ
#define X86_INS_MOVDQU ZYDIS_MNEMONIC_MOVDQU
#define X86_INS_MOVDQA ZYDIS_MNEMONIC_MOVDQA
#define X86_INS_MOVDQ2Q ZYDIS_MNEMONIC_MOVDQ2Q
#define X86_INS_MOVD ZYDIS_MNEMONIC_MOVD
#define X86_INS_CPUID ZYDIS_MNEMONIC_CPUID
#define X86_INS_SHLD ZYDIS_MNEMONIC_SHLD
#define X86_INS_SHLX ZYDIS_MNEMONIC_SHLX
#define X86_INS_SARX ZYDIS_MNEMONIC_SARX
#define X86_INS_SALC ZYDIS_MNEMONIC_SALC
#define X86_INS_SHRD ZYDIS_MNEMONIC_SHRD
#define X86_INS_SHRX ZYDIS_MNEMONIC_SHRX
#define X86_INS_CWDE ZYDIS_MNEMONIC_CWDE
#define X86_INS_CDQ ZYDIS_MNEMONIC_CDQ
#define X86_INS_CDQE ZYDIS_MNEMONIC_CDQE
#define X86_INS_CMPPD ZYDIS_MNEMONIC_CMPPD
#define X86_INS_CMPPS ZYDIS_MNEMONIC_CMPPS
#define X86_INS_CMPSS ZYDIS_MNEMONIC_CMPSS
#define X86_INS_PUSHAD ZYDIS_MNEMONIC_PUSHAD
#define X86_INS_POPAD ZYDIS_MNEMONIC_POPAD
#define X86_INS_IRETD ZYDIS_MNEMONIC_IRETD
#define X86_INS_IRETQ ZYDIS_MNEMONIC_IRETQ
#define X86_INS_SYSRET ZYDIS_MNEMONIC_SYSRET
#define X86_INS_INT3 ZYDIS_MNEMONIC_INT3
#define X86_INS_INT1 ZYDIS_MNEMONIC_INT1
#define X86_INS_SYSCALL ZYDIS_MNEMONIC_SYSCALL
#define X86_INS_SYSENTER ZYDIS_MNEMONIC_SYSENTER
#define X86_INS_SYSEXIT ZYDIS_MNEMONIC_SYSEXIT
#define X86_INS_VMCALL ZYDIS_MNEMONIC_VMCALL
#define X86_INS_VMMCALL ZYDIS_MNEMONIC_VMMCALL
#define X86_INS_INSD ZYDIS_MNEMONIC_INSD
#define X86_INS_OUTSD ZYDIS_MNEMONIC_OUTSD
#define X86_INS_VXORPD ZYDIS_MNEMONIC_VXORPD
#define X86_INS_VXORPS ZYDIS_MNEMONIC_VXORPS
#define X86_INS_VPXORD ZYDIS_MNEMONIC_VPXORD
#define X86_INS_VPXORQ ZYDIS_MNEMONIC_VPXORQ
#define X86_INS_VPXOR ZYDIS_MNEMONIC_VPXOR
#define X86_INS_XORPS ZYDIS_MNEMONIC_XORPS
#define X86_INS_KXORW ZYDIS_MNEMONIC_KXORW
#define X86_INS_PXOR ZYDIS_MNEMONIC_PXOR
#define X86_INS_BSR ZYDIS_MNEMONIC_BSR
#define X86_INS_BSWAP ZYDIS_MNEMONIC_BSWAP
#define X86_INS_PSUBB ZYDIS_MNEMONIC_PSUBB
#define X86_INS_PSUBW ZYDIS_MNEMONIC_PSUBW
#define X86_INS_PSUBD ZYDIS_MNEMONIC_PSUBD
#define X86_INS_PSUBQ ZYDIS_MNEMONIC_PSUBQ
#define X86_INS_PSUBSB ZYDIS_MNEMONIC_PSUBSB
#define X86_INS_PSUBSW ZYDIS_MNEMONIC_PSUBSW
#define X86_INS_PSUBUSB ZYDIS_MNEMONIC_PSUBUSB
#define X86_INS_PSUBUSW ZYDIS_MNEMONIC_PSUBUSW
#define X86_INS_LIDT ZYDIS_MNEMONIC_LIDT
#define X86_INS_SIDT ZYDIS_MNEMONIC_SIDT
#define X86_INS_RDRAND ZYDIS_MNEMONIC_RDRAND
#define X86_INS_RDSEED ZYDIS_MNEMONIC_RDSEED
#define X86_INS_RDMSR ZYDIS_MNEMONIC_RDMSR
#define X86_INS_RDPMC ZYDIS_MNEMONIC_RDPMC
#define X86_INS_RDTSC ZYDIS_MNEMONIC_RDTSC
#define X86_INS_RDTSCP ZYDIS_MNEMONIC_RDTSCP
#define X86_INS_CRC32 ZYDIS_MNEMONIC_CRC32
#define X86_INS_SHA1MSG1 ZYDIS_MNEMONIC_SHA1MSG1
#define X86_INS_SHA1MSG2 ZYDIS_MNEMONIC_SHA1MSG2
#define X86_INS_SHA1NEXTE ZYDIS_MNEMONIC_SHA1NEXTE
#define X86_INS_SHA1RNDS4 ZYDIS_MNEMONIC_SHA1RNDS4
#define X86_INS_SHA256MSG1 ZYDIS_MNEMONIC_SHA256MSG1
#define X86_INS_SHA256MSG2 ZYDIS_MNEMONIC_SHA256MSG2
#define X86_INS_SHA256RNDS2 ZYDIS_MNEMONIC_SHA256RNDS2
#define X86_INS_AESDECLAST ZYDIS_MNEMONIC_AESDECLAST
#define X86_INS_AESDEC ZYDIS_MNEMONIC_AESDEC
#define X86_INS_AESENCLAST ZYDIS_MNEMONIC_AESENCLAST
#define X86_INS_AESENC ZYDIS_MNEMONIC_AESENC
#define X86_INS_AESIMC ZYDIS_MNEMONIC_AESIMC
#define X86_INS_AESKEYGENASSIST ZYDIS_MNEMONIC_AESKEYGENASSIST
#define X86_INS_ANDN ZYDIS_MNEMONIC_ANDN
#define X86_INS_ANDPD ZYDIS_MNEMONIC_ANDPD
#define X86_INS_ANDPS ZYDIS_MNEMONIC_ANDPS
#define X86_INS_ANDNPD ZYDIS_MNEMONIC_ANDNPD
#define X86_INS_ANDNPS ZYDIS_MNEMONIC_ANDNPS
#define X86_INS_MULX ZYDIS_MNEMONIC_MULX
#define X86_INS_MULPD ZYDIS_MNEMONIC_MULPD
#define X86_INS_MULPS ZYDIS_MNEMONIC_MULPS
#define X86_INS_MULSD ZYDIS_MNEMONIC_MULSD
#define X86_INS_MULSS ZYDIS_MNEMONIC_MULSS
#define X86_INS_PACKSSDW ZYDIS_MNEMONIC_PACKSSDW
#define X86_INS_PACKSSWB ZYDIS_MNEMONIC_PACKSSWB
#define X86_INS_PACKUSWB ZYDIS_MNEMONIC_PACKUSWB
#define X86_INS_PADDB ZYDIS_MNEMONIC_PADDB
#define X86_INS_PADDD ZYDIS_MNEMONIC_PADDD
#define X86_INS_PADDW ZYDIS_MNEMONIC_PADDW
#define X86_INS_PADDSB ZYDIS_MNEMONIC_PADDSB
#define X86_INS_PADDSW ZYDIS_MNEMONIC_PADDSW
#define X86_INS_PADDUSB ZYDIS_MNEMONIC_PADDUSB
#define X86_INS_PADDUSW ZYDIS_MNEMONIC_PADDUSW
#define X86_INS_XADD ZYDIS_MNEMONIC_XADD
#define X86_INS_FADDP ZYDIS_MNEMONIC_FADDP
#define X86_INS_PFADD ZYDIS_MNEMONIC_PFADD
#define X86_INS_ADDPS ZYDIS_MNEMONIC_ADDPS
#define X86_INS_ADDSD ZYDIS_MNEMONIC_ADDSD
#define X86_INS_ADDSS ZYDIS_MNEMONIC_ADDSS
#define X86_INS_ADDSUBPD ZYDIS_MNEMONIC_ADDSUBPD
#define X86_INS_ADDSUBPS ZYDIS_MNEMONIC_ADDSUBPS
#define X86_INS_ADDPD ZYDIS_MNEMONIC_ADDPD
#define X86_INS_SUBSD ZYDIS_MNEMONIC_SUBSD
#define X86_INS_CVTSS2SD ZYDIS_MNEMONIC_CVTSS2SD
#define X86_INS_BT ZYDIS_MNEMONIC_BT
#define X86_INS_BTC ZYDIS_MNEMONIC_BTC
#define X86_INS_BTR ZYDIS_MNEMONIC_BTR
#define X86_INS_BTS ZYDIS_MNEMONIC_BTS
#define X86_INS_PALIGNR ZYDIS_MNEMONIC_PALIGNR
#define X86_INS_VALIGND ZYDIS_MNEMONIC_VALIGND
#define X86_INS_VALIGNQ ZYDIS_MNEMONIC_VALIGNQ
#define X86_INS_VPALIGNR ZYDIS_MNEMONIC_VPALIGNR
#define X86_INS_SFENCE ZYDIS_MNEMONIC_SFENCE
#define X86_INS_LFENCE ZYDIS_MNEMONIC_LFENCE
#define X86_INS_MFENCE ZYDIS_MNEMONIC_MFENCE
#define X86_INS_MOVNTQ ZYDIS_MNEMONIC_MOVNTQ
#define X86_INS_MOVNTDQA ZYDIS_MNEMONIC_MOVNTDQA
#define X86_INS_MOVNTDQ ZYDIS_MNEMONIC_MOVNTDQ
#define X86_INS_MOVNTI ZYDIS_MNEMONIC_MOVNTI
#define X86_INS_MOVNTPD ZYDIS_MNEMONIC_MOVNTPD
#define X86_INS_MOVNTPS ZYDIS_MNEMONIC_MOVNTPS
#define X86_INS_MOVNTSD ZYDIS_MNEMONIC_MOVNTSD
#define X86_INS_MOVNTSS ZYDIS_MNEMONIC_MOVNTSS
#define X86_INS_VMOVNTDQA ZYDIS_MNEMONIC_VMOVNTDQA
#define X86_INS_VMOVNTDQ ZYDIS_MNEMONIC_VMOVNTDQ
#define X86_INS_VMOVNTPD ZYDIS_MNEMONIC_VMOVNTPD
#define X86_INS_VMOVNTPS ZYDIS_MNEMONIC_VMOVNTPS
#define X86_INS_PCMPEQB ZYDIS_MNEMONIC_PCMPEQB
#define X86_INS_PCMPEQD ZYDIS_MNEMONIC_PCMPEQD
#define X86_INS_PCMPEQW ZYDIS_MNEMONIC_PCMPEQW
#define X86_INS_PCMPGTB ZYDIS_MNEMONIC_PCMPGTB
#define X86_INS_PCMPGTD ZYDIS_MNEMONIC_PCMPGTD
#define X86_INS_PCMPGTW ZYDIS_MNEMONIC_PCMPGTW
#define X86_INS_PCMPEQQ ZYDIS_MNEMONIC_PCMPEQQ
#define X86_INS_PCMPESTRI ZYDIS_MNEMONIC_PCMPESTRI
#define X86_INS_PCMPESTRM ZYDIS_MNEMONIC_PCMPESTRM
#define X86_INS_PCMPGTQ ZYDIS_MNEMONIC_PCMPGTQ
#define X86_INS_PCMPISTRI ZYDIS_MNEMONIC_PCMPISTRI
#define X86_INS_PCMPISTRM ZYDIS_MNEMONIC_PCMPISTRM
#define X86_INS_VPCMPB ZYDIS_MNEMONIC_VPCMPB
#define X86_INS_VPCMPD ZYDIS_MNEMONIC_VPCMPD
#define X86_INS_VPCMPEQB ZYDIS_MNEMONIC_VPCMPEQB
#define X86_INS_VPCMPEQD ZYDIS_MNEMONIC_VPCMPEQD
#define X86_INS_VPCMPEQQ ZYDIS_MNEMONIC_VPCMPEQQ
#define X86_INS_VPCMPEQW ZYDIS_MNEMONIC_VPCMPEQW
#define X86_INS_VPCMPESTRI ZYDIS_MNEMONIC_VPCMPESTRI
#define X86_INS_VPCMPESTRM ZYDIS_MNEMONIC_VPCMPESTRM
#define X86_INS_VPCMPGTB ZYDIS_MNEMONIC_VPCMPGTB
#define X86_INS_VPCMPGTD ZYDIS_MNEMONIC_VPCMPGTD
#define X86_INS_VPCMPGTQ ZYDIS_MNEMONIC_VPCMPGTQ
#define X86_INS_VPCMPGTW ZYDIS_MNEMONIC_VPCMPGTW
#define X86_INS_VPCMPISTRI ZYDIS_MNEMONIC_VPCMPISTRI
#define X86_INS_VPCMPISTRM ZYDIS_MNEMONIC_VPCMPISTRM
#define X86_INS_VPCMPQ ZYDIS_MNEMONIC_VPCMPQ
#define X86_INS_VPCMPUB ZYDIS_MNEMONIC_VPCMPUB
#define X86_INS_VPCMPUD ZYDIS_MNEMONIC_VPCMPUD
#define X86_INS_VPCMPUQ ZYDIS_MNEMONIC_VPCMPUQ
#define X86_INS_VPCMPUW ZYDIS_MNEMONIC_VPCMPUW
#define X86_INS_VPCMPW ZYDIS_MNEMONIC_VPCMPW
#define X86_INS_UD0 ZYDIS_MNEMONIC_UD0
#define X86_INS_UD2 ZYDIS_MNEMONIC_UD2
#define X86_INS_PMULHW ZYDIS_MNEMONIC_PMULHW
#define X86_INS_PMULLW ZYDIS_MNEMONIC_PMULLW
#define X86_INS_PMADDWD ZYDIS_MNEMONIC_PMADDWD
#define X86_INS_PAND ZYDIS_MNEMONIC_PAND
#define X86_INS_PANDN ZYDIS_MNEMONIC_PANDN
#define X86_INS_POR ZYDIS_MNEMONIC_POR
#define X86_INS_PSLLD ZYDIS_MNEMONIC_PSLLD
#define X86_INS_PSLLW ZYDIS_MNEMONIC_PSLLW
#define X86_INS_PSRLQ ZYDIS_MNEMONIC_PSRLQ
#define X86_INS_PADDQ ZYDIS_MNEMONIC_PADDQ
#define X86_INS_DIVPS ZYDIS_MNEMONIC_DIVPS
#define X86_INS_DIVSS ZYDIS_MNEMONIC_DIVSS
#define X86_INS_MAXPS ZYDIS_MNEMONIC_MAXPS
#define X86_INS_MAXSS ZYDIS_MNEMONIC_MAXSS
#define X86_INS_MINPS ZYDIS_MNEMONIC_MINPS
#define X86_INS_MINSS ZYDIS_MNEMONIC_MINSS
#define X86_INS_RSQRTPS ZYDIS_MNEMONIC_RSQRTPS
#define X86_INS_RSQRTSS ZYDIS_MNEMONIC_RSQRTSS
#define X86_INS_SUBPS ZYDIS_MNEMONIC_SUBPS
#define X86_INS_SUBSS ZYDIS_MNEMONIC_SUBSS
#define X86_INS_SQRTPS ZYDIS_MNEMONIC_SQRTPS
#define X86_INS_SQRTSS ZYDIS_MNEMONIC_SQRTSS
#define X86_INS_CVTPI2PS ZYDIS_MNEMONIC_CVTPI2PS
#define X86_INS_CVTSS2SI ZYDIS_MNEMONIC_CVTSS2SI
#define X86_INS_CVTPS2PI ZYDIS_MNEMONIC_CVTPS2PI
#define X86_INS_CVTSI2SS ZYDIS_MNEMONIC_CVTSI2SS
#define X86_INS_CVTTPD2DQ ZYDIS_MNEMONIC_CVTTPD2DQ
#define X86_INS_CVTPD2PS ZYDIS_MNEMONIC_CVTPD2PS
#define X86_INS_CVTPS2PD ZYDIS_MNEMONIC_CVTPS2PD
#define X86_INS_CVTSD2SI ZYDIS_MNEMONIC_CVTSD2SI
#define X86_INS_CVTSD2SS ZYDIS_MNEMONIC_CVTSD2SS
#define X86_INS_PMOVMSKB ZYDIS_MNEMONIC_PMOVMSKB
#define X86_INS_PSHUFD ZYDIS_MNEMONIC_PSHUFD
#define X86_INS_PSHUFHW ZYDIS_MNEMONIC_PSHUFHW
#define X86_INS_PSHUFLW ZYDIS_MNEMONIC_PSHUFLW
#define X86_INS_PTEST ZYDIS_MNEMONIC_PTEST
#define X86_INS_CVTDQ2PS ZYDIS_MNEMONIC_CVTDQ2PS
#define X86_INS_CVTPS2DQ ZYDIS_MNEMONIC_CVTPS2DQ
#define X86_INS_MOVDDUP ZYDIS_MNEMONIC_MOVDDUP
#define X86_INS_RCPPS ZYDIS_MNEMONIC_RCPPS
#define X86_INS_ORPS ZYDIS_MNEMONIC_ORPS
#define X86_INS_FWAIT ZYDIS_MNEMONIC_FWAIT
#define X86_INS_XLAT ZYDIS_MNEMONIC_XLAT
#define X86_INS_MAX_VALUE ZYDIS_MNEMONIC_MAX_VALUE
// Operand types
#define X86_OP_REG ZYDIS_OPERAND_TYPE_REGISTER
#define X86_OP_IMM ZYDIS_OPERAND_TYPE_IMMEDIATE
#define X86_OP_MEM ZYDIS_OPERAND_TYPE_MEMORY
#define X86_OP_PTR ZYDIS_OPERAND_TYPE_POINTER
// Registers
#define X86_REG_AH ZYDIS_REGISTER_AH
#define X86_REG_AL ZYDIS_REGISTER_AL
#define X86_REG_AX ZYDIS_REGISTER_AX
#define X86_REG_BH ZYDIS_REGISTER_BH
#define X86_REG_BL ZYDIS_REGISTER_BL
#define X86_REG_BP ZYDIS_REGISTER_BP
#define X86_REG_BPL ZYDIS_REGISTER_BPL
#define X86_REG_BX ZYDIS_REGISTER_BX
#define X86_REG_CH ZYDIS_REGISTER_CH
#define X86_REG_CL ZYDIS_REGISTER_CL
#define X86_REG_CS ZYDIS_REGISTER_CS
#define X86_REG_CX ZYDIS_REGISTER_CX
#define X86_REG_DH ZYDIS_REGISTER_DH
#define X86_REG_DI ZYDIS_REGISTER_DI
#define X86_REG_DIL ZYDIS_REGISTER_DIL
#define X86_REG_DL ZYDIS_REGISTER_DL
#define X86_REG_DS ZYDIS_REGISTER_DS
#define X86_REG_DX ZYDIS_REGISTER_DX
#define X86_REG_EAX ZYDIS_REGISTER_EAX
#define X86_REG_EBP ZYDIS_REGISTER_EBP
#define X86_REG_EBX ZYDIS_REGISTER_EBX
#define X86_REG_ECX ZYDIS_REGISTER_ECX
#define X86_REG_EDI ZYDIS_REGISTER_EDI
#define X86_REG_EDX ZYDIS_REGISTER_EDX
#define X86_REG_EFLAGS ZYDIS_REGISTER_EFLAGS
#define X86_REG_EIP ZYDIS_REGISTER_EIP
#define X86_REG_ES ZYDIS_REGISTER_ES
#define X86_REG_ESI ZYDIS_REGISTER_ESI
#define X86_REG_ESP ZYDIS_REGISTER_ESP
#define X86_REG_X87STATUS ZYDIS_REGISTER_X87STATUS
#define X86_REG_FS ZYDIS_REGISTER_FS
#define X86_REG_GS ZYDIS_REGISTER_GS
#define X86_REG_IP ZYDIS_REGISTER_IP
#define X86_REG_RAX ZYDIS_REGISTER_RAX
#define X86_REG_RBP ZYDIS_REGISTER_RBP
#define X86_REG_RBX ZYDIS_REGISTER_RBX
#define X86_REG_RCX ZYDIS_REGISTER_RCX
#define X86_REG_RDI ZYDIS_REGISTER_RDI
#define X86_REG_RDX ZYDIS_REGISTER_RDX
#define X86_REG_RIP ZYDIS_REGISTER_RIP
#define X86_REG_RSI ZYDIS_REGISTER_RSI
#define X86_REG_RSP ZYDIS_REGISTER_RSP
#define X86_REG_SI ZYDIS_REGISTER_SI
#define X86_REG_SIL ZYDIS_REGISTER_SIL
#define X86_REG_SP ZYDIS_REGISTER_SP
#define X86_REG_SPL ZYDIS_REGISTER_SPL
#define X86_REG_SS ZYDIS_REGISTER_SS
#define X86_REG_CR0 ZYDIS_REGISTER_CR0
#define X86_REG_CR1 ZYDIS_REGISTER_CR1
#define X86_REG_CR2 ZYDIS_REGISTER_CR2
#define X86_REG_CR3 ZYDIS_REGISTER_CR3
#define X86_REG_CR4 ZYDIS_REGISTER_CR4
#define X86_REG_CR5 ZYDIS_REGISTER_CR5
#define X86_REG_CR6 ZYDIS_REGISTER_CR6
#define X86_REG_CR7 ZYDIS_REGISTER_CR7
#define X86_REG_CR8 ZYDIS_REGISTER_CR8
#define X86_REG_CR9 ZYDIS_REGISTER_CR9
#define X86_REG_CR10 ZYDIS_REGISTER_CR10
#define X86_REG_CR11 ZYDIS_REGISTER_CR11
#define X86_REG_CR12 ZYDIS_REGISTER_CR12
#define X86_REG_CR13 ZYDIS_REGISTER_CR13
#define X86_REG_CR14 ZYDIS_REGISTER_CR14
#define X86_REG_CR15 ZYDIS_REGISTER_CR15
#define X86_REG_DR0 ZYDIS_REGISTER_DR0
#define X86_REG_DR1 ZYDIS_REGISTER_DR1
#define X86_REG_DR2 ZYDIS_REGISTER_DR2
#define X86_REG_DR3 ZYDIS_REGISTER_DR3
#define X86_REG_DR4 ZYDIS_REGISTER_DR4
#define X86_REG_DR5 ZYDIS_REGISTER_DR5
#define X86_REG_DR6 ZYDIS_REGISTER_DR6
#define X86_REG_DR7 ZYDIS_REGISTER_DR7
#define X86_REG_DR8 ZYDIS_REGISTER_DR8
#define X86_REG_DR9 ZYDIS_REGISTER_DR9
#define X86_REG_DR10 ZYDIS_REGISTER_DR10
#define X86_REG_DR11 ZYDIS_REGISTER_DR11
#define X86_REG_DR12 ZYDIS_REGISTER_DR12
#define X86_REG_DR13 ZYDIS_REGISTER_DR13
#define X86_REG_DR14 ZYDIS_REGISTER_DR14
#define X86_REG_DR15 ZYDIS_REGISTER_DR15
#define X86_REG_K0 ZYDIS_REGISTER_K0
#define X86_REG_K1 ZYDIS_REGISTER_K1
#define X86_REG_K2 ZYDIS_REGISTER_K2
#define X86_REG_K3 ZYDIS_REGISTER_K3
#define X86_REG_K4 ZYDIS_REGISTER_K4
#define X86_REG_K5 ZYDIS_REGISTER_K5
#define X86_REG_K6 ZYDIS_REGISTER_K6
#define X86_REG_K7 ZYDIS_REGISTER_K7
#define X86_REG_MM0 ZYDIS_REGISTER_MM0
#define X86_REG_MM1 ZYDIS_REGISTER_MM1
#define X86_REG_MM2 ZYDIS_REGISTER_MM2
#define X86_REG_MM3 ZYDIS_REGISTER_MM3
#define X86_REG_MM4 ZYDIS_REGISTER_MM4
#define X86_REG_MM5 ZYDIS_REGISTER_MM5
#define X86_REG_MM6 ZYDIS_REGISTER_MM6
#define X86_REG_MM7 ZYDIS_REGISTER_MM7
#define X86_REG_R8 ZYDIS_REGISTER_R8
#define X86_REG_R9 ZYDIS_REGISTER_R9
#define X86_REG_R10 ZYDIS_REGISTER_R10
#define X86_REG_R11 ZYDIS_REGISTER_R11
#define X86_REG_R12 ZYDIS_REGISTER_R12
#define X86_REG_R13 ZYDIS_REGISTER_R13
#define X86_REG_R14 ZYDIS_REGISTER_R14
#define X86_REG_R15 ZYDIS_REGISTER_R15
#define X86_REG_ST0 ZYDIS_REGISTER_ST0
#define X86_REG_ST1 ZYDIS_REGISTER_ST1
#define X86_REG_ST2 ZYDIS_REGISTER_ST2
#define X86_REG_ST3 ZYDIS_REGISTER_ST3
#define X86_REG_ST4 ZYDIS_REGISTER_ST4
#define X86_REG_ST5 ZYDIS_REGISTER_ST5
#define X86_REG_ST6 ZYDIS_REGISTER_ST6
#define X86_REG_ST7 ZYDIS_REGISTER_ST7
#define X86_REG_XMM0 ZYDIS_REGISTER_XMM0
#define X86_REG_XMM1 ZYDIS_REGISTER_XMM1
#define X86_REG_XMM2 ZYDIS_REGISTER_XMM2
#define X86_REG_XMM3 ZYDIS_REGISTER_XMM3
#define X86_REG_XMM4 ZYDIS_REGISTER_XMM4
#define X86_REG_XMM5 ZYDIS_REGISTER_XMM5
#define X86_REG_XMM6 ZYDIS_REGISTER_XMM6
#define X86_REG_XMM7 ZYDIS_REGISTER_XMM7
#define X86_REG_XMM8 ZYDIS_REGISTER_XMM8
#define X86_REG_XMM9 ZYDIS_REGISTER_XMM9
#define X86_REG_XMM10 ZYDIS_REGISTER_XMM10
#define X86_REG_XMM11 ZYDIS_REGISTER_XMM11
#define X86_REG_XMM12 ZYDIS_REGISTER_XMM12
#define X86_REG_XMM13 ZYDIS_REGISTER_XMM13
#define X86_REG_XMM14 ZYDIS_REGISTER_XMM14
#define X86_REG_XMM15 ZYDIS_REGISTER_XMM15
#define X86_REG_XMM16 ZYDIS_REGISTER_XMM16
#define X86_REG_XMM17 ZYDIS_REGISTER_XMM17
#define X86_REG_XMM18 ZYDIS_REGISTER_XMM18
#define X86_REG_XMM19 ZYDIS_REGISTER_XMM19
#define X86_REG_XMM20 ZYDIS_REGISTER_XMM20
#define X86_REG_XMM21 ZYDIS_REGISTER_XMM21
#define X86_REG_XMM22 ZYDIS_REGISTER_XMM22
#define X86_REG_XMM23 ZYDIS_REGISTER_XMM23
#define X86_REG_XMM24 ZYDIS_REGISTER_XMM24
#define X86_REG_XMM25 ZYDIS_REGISTER_XMM25
#define X86_REG_XMM26 ZYDIS_REGISTER_XMM26
#define X86_REG_XMM27 ZYDIS_REGISTER_XMM27
#define X86_REG_XMM28 ZYDIS_REGISTER_XMM28
#define X86_REG_XMM29 ZYDIS_REGISTER_XMM29
#define X86_REG_XMM30 ZYDIS_REGISTER_XMM30
#define X86_REG_XMM31 ZYDIS_REGISTER_XMM31
#define X86_REG_YMM0 ZYDIS_REGISTER_YMM0
#define X86_REG_YMM1 ZYDIS_REGISTER_YMM1
#define X86_REG_YMM2 ZYDIS_REGISTER_YMM2
#define X86_REG_YMM3 ZYDIS_REGISTER_YMM3
#define X86_REG_YMM4 ZYDIS_REGISTER_YMM4
#define X86_REG_YMM5 ZYDIS_REGISTER_YMM5
#define X86_REG_YMM6 ZYDIS_REGISTER_YMM6
#define X86_REG_YMM7 ZYDIS_REGISTER_YMM7
#define X86_REG_YMM8 ZYDIS_REGISTER_YMM8
#define X86_REG_YMM9 ZYDIS_REGISTER_YMM9
#define X86_REG_YMM10 ZYDIS_REGISTER_YMM10
#define X86_REG_YMM11 ZYDIS_REGISTER_YMM11
#define X86_REG_YMM12 ZYDIS_REGISTER_YMM12
#define X86_REG_YMM13 ZYDIS_REGISTER_YMM13
#define X86_REG_YMM14 ZYDIS_REGISTER_YMM14
#define X86_REG_YMM15 ZYDIS_REGISTER_YMM15
#define X86_REG_YMM16 ZYDIS_REGISTER_YMM16
#define X86_REG_YMM17 ZYDIS_REGISTER_YMM17
#define X86_REG_YMM18 ZYDIS_REGISTER_YMM18
#define X86_REG_YMM19 ZYDIS_REGISTER_YMM19
#define X86_REG_YMM20 ZYDIS_REGISTER_YMM20
#define X86_REG_YMM21 ZYDIS_REGISTER_YMM21
#define X86_REG_YMM22 ZYDIS_REGISTER_YMM22
#define X86_REG_YMM23 ZYDIS_REGISTER_YMM23
#define X86_REG_YMM24 ZYDIS_REGISTER_YMM24
#define X86_REG_YMM25 ZYDIS_REGISTER_YMM25
#define X86_REG_YMM26 ZYDIS_REGISTER_YMM26
#define X86_REG_YMM27 ZYDIS_REGISTER_YMM27
#define X86_REG_YMM28 ZYDIS_REGISTER_YMM28
#define X86_REG_YMM29 ZYDIS_REGISTER_YMM29
#define X86_REG_YMM30 ZYDIS_REGISTER_YMM30
#define X86_REG_YMM31 ZYDIS_REGISTER_YMM31
#define X86_REG_ZMM0 ZYDIS_REGISTER_ZMM0
#define X86_REG_ZMM1 ZYDIS_REGISTER_ZMM1
#define X86_REG_ZMM2 ZYDIS_REGISTER_ZMM2
#define X86_REG_ZMM3 ZYDIS_REGISTER_ZMM3
#define X86_REG_ZMM4 ZYDIS_REGISTER_ZMM4
#define X86_REG_ZMM5 ZYDIS_REGISTER_ZMM5
#define X86_REG_ZMM6 ZYDIS_REGISTER_ZMM6
#define X86_REG_ZMM7 ZYDIS_REGISTER_ZMM7
#define X86_REG_ZMM8 ZYDIS_REGISTER_ZMM8
#define X86_REG_ZMM9 ZYDIS_REGISTER_ZMM9
#define X86_REG_ZMM10 ZYDIS_REGISTER_ZMM10
#define X86_REG_ZMM11 ZYDIS_REGISTER_ZMM11
#define X86_REG_ZMM12 ZYDIS_REGISTER_ZMM12
#define X86_REG_ZMM13 ZYDIS_REGISTER_ZMM13
#define X86_REG_ZMM14 ZYDIS_REGISTER_ZMM14
#define X86_REG_ZMM15 ZYDIS_REGISTER_ZMM15
#define X86_REG_ZMM16 ZYDIS_REGISTER_ZMM16
#define X86_REG_ZMM17 ZYDIS_REGISTER_ZMM17
#define X86_REG_ZMM18 ZYDIS_REGISTER_ZMM18
#define X86_REG_ZMM19 ZYDIS_REGISTER_ZMM19
#define X86_REG_ZMM20 ZYDIS_REGISTER_ZMM20
#define X86_REG_ZMM21 ZYDIS_REGISTER_ZMM21
#define X86_REG_ZMM22 ZYDIS_REGISTER_ZMM22
#define X86_REG_ZMM23 ZYDIS_REGISTER_ZMM23
#define X86_REG_ZMM24 ZYDIS_REGISTER_ZMM24
#define X86_REG_ZMM25 ZYDIS_REGISTER_ZMM25
#define X86_REG_ZMM26 ZYDIS_REGISTER_ZMM26
#define X86_REG_ZMM27 ZYDIS_REGISTER_ZMM27
#define X86_REG_ZMM28 ZYDIS_REGISTER_ZMM28
#define X86_REG_ZMM29 ZYDIS_REGISTER_ZMM29
#define X86_REG_ZMM30 ZYDIS_REGISTER_ZMM30
#define X86_REG_ZMM31 ZYDIS_REGISTER_ZMM31
#define X86_REG_R8B ZYDIS_REGISTER_R8B
#define X86_REG_R9B ZYDIS_REGISTER_R9B
#define X86_REG_R10B ZYDIS_REGISTER_R10B
#define X86_REG_R11B ZYDIS_REGISTER_R11B
#define X86_REG_R12B ZYDIS_REGISTER_R12B
#define X86_REG_R13B ZYDIS_REGISTER_R13B
#define X86_REG_R14B ZYDIS_REGISTER_R14B
#define X86_REG_R15B ZYDIS_REGISTER_R15B
#define X86_REG_R8D ZYDIS_REGISTER_R8D
#define X86_REG_R9D ZYDIS_REGISTER_R9D
#define X86_REG_R10D ZYDIS_REGISTER_R10D
#define X86_REG_R11D ZYDIS_REGISTER_R11D
#define X86_REG_R12D ZYDIS_REGISTER_R12D
#define X86_REG_R13D ZYDIS_REGISTER_R13D
#define X86_REG_R14D ZYDIS_REGISTER_R14D
#define X86_REG_R15D ZYDIS_REGISTER_R15D
#define X86_REG_R8W ZYDIS_REGISTER_R8W
#define X86_REG_R9W ZYDIS_REGISTER_R9W
#define X86_REG_R10W ZYDIS_REGISTER_R10W
#define X86_REG_R11W ZYDIS_REGISTER_R11W
#define X86_REG_R12W ZYDIS_REGISTER_R12W
#define X86_REG_R13W ZYDIS_REGISTER_R13W
#define X86_REG_R14W ZYDIS_REGISTER_R14W
#define X86_REG_R15W ZYDIS_REGISTER_R15W
#define X86_REG_AH ZYDIS_REGISTER_AH
#define X86_REG_BH ZYDIS_REGISTER_BH
#define X86_REG_CH ZYDIS_REGISTER_CH
#define X86_REG_DH ZYDIS_REGISTER_DH
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_AL ZYDIS_REGISTER_AL
#define X86_REG_BL ZYDIS_REGISTER_BL
#define X86_REG_CL ZYDIS_REGISTER_CL
#define X86_REG_DL ZYDIS_REGISTER_DL
#define X86_REG_BPL ZYDIS_REGISTER_BPL
#define X86_REG_DIL ZYDIS_REGISTER_DIL
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_SIL ZYDIS_REGISTER_SIL
#define X86_REG_SPL ZYDIS_REGISTER_SPL
#define X86_REG_AX ZYDIS_REGISTER_AX
#define X86_REG_BX ZYDIS_REGISTER_BX
#define X86_REG_CX ZYDIS_REGISTER_CX
#define X86_REG_DX ZYDIS_REGISTER_DX
#define X86_REG_BP ZYDIS_REGISTER_BP
#define X86_REG_DI ZYDIS_REGISTER_DI
#define X86_REG_IP ZYDIS_REGISTER_IP
#define X86_REG_NONE ZYDIS_REGISTER_NONE
#define X86_REG_SI ZYDIS_REGISTER_SI
#define X86_REG_SP ZYDIS_REGISTER_SP
#define X86_REG_EAX ZYDIS_REGISTER_EAX
#define X86_REG_EBX ZYDIS_REGISTER_EBX
#define X86_REG_ECX ZYDIS_REGISTER_ECX
#define X86_REG_EDX ZYDIS_REGISTER_EDX
#define X86_REG_EBP ZYDIS_REGISTER_EBP
#define X86_REG_EDI ZYDIS_REGISTER_EDI
#define X86_REG_EIP ZYDIS_REGISTER_EIP
#define X86_REG_ESI ZYDIS_REGISTER_ESI
#define X86_REG_ESP ZYDIS_REGISTER_ESP
#define X86_REG_RAX ZYDIS_REGISTER_RAX
#define X86_REG_RBX ZYDIS_REGISTER_RBX
#define X86_REG_RCX ZYDIS_REGISTER_RCX
#define X86_REG_RDX ZYDIS_REGISTER_RDX
#define X86_REG_RBP ZYDIS_REGISTER_RBP
#define X86_REG_RDI ZYDIS_REGISTER_RDI
#define X86_REG_RIP ZYDIS_REGISTER_RIP
#define X86_REG_RSI ZYDIS_REGISTER_RSI
#define X86_REG_RSP ZYDIS_REGISTER_RSP
#define X86_REG_MAX_VALUE ZYDIS_REGISTER_MAX_VALUE
#endif // X86_MNEMONIC_H

5
librz/arch/meson.build
View file

@ -53,11 +53,11 @@ arch_plugins_list = [
'v850',
'wasm',
'x86_as',
'x86_cs',
'x86_nasm',
'x86_nz',
'xap',
'xcore_cs',
'x86_zydis'
]
arch_plugin_sources = [
@ -110,11 +110,11 @@ arch_plugin_sources = [
'p/arch_v850.c',
'p/arch_wasm.c',
'p/arch_x86_as.c',
'p/arch_x86_cs.c',
'p/arch_x86_nasm.c',
'p/arch_x86_nz.c',
'p/arch_xap.c',
'p/arch_xcore_cs.c',
'p/arch_x86_zydis.c'
]
arch_esil_sources = [
@ -478,6 +478,7 @@ rz_arch = library('rz_arch', rz_arch_sources,
rz_type_dep,
rz_il_dep,
capstone_dep,
zydis_dep,
mth,
dependency('rzspp'),
],

1610
librz/arch/p/analysis/analysis_x86_cs.c → librz/arch/p/analysis/analysis_x86_zydis.c
View file

File diff suppressed because it is too large Load diff

8
librz/arch/p/arch_x86_cs.c → librz/arch/p/arch_x86_zydis.c
View file

@ -4,8 +4,8 @@
#include <deprecated_arch_helper.h>
#include "analysis/analysis_x86_cs.c"
#include "asm/asm_x86_cs.c"
#include "parse/parse_x86_pseudo.c"
#include "analysis/analysis_x86_zydis.c"
#include "asm/asm_x86_zydis.c"
#include "parse/parse_x86_pseudo_zydis.c"
RZ_ARCH_WITH_PARSE_PLUGIN_DEFINE_DEPRECATED(x86_cs);
RZ_ARCH_WITH_PARSE_PLUGIN_DEFINE_DEPRECATED(x86_zydis);

2
librz/arch/p/asm/asm_x86_vm.c
View file

@ -28,7 +28,7 @@
#define VPCEXT2(y, x) ((y)[2] == (x))
void decompile_vm(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
static inline void decompile_vm(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
if (len > 3 && buf[0] == 0x0F && buf[1] == 0x3F && (VPCEXT2(buf, 0x01) || VPCEXT2(buf, 0x05) || VPCEXT2(buf, 0x07) || VPCEXT2(buf, 0x0D) || VPCEXT2(buf, 0x10))) {
if (a->syntax == RZ_ASM_SYNTAX_ATT) {
rz_asm_op_setf_asm(op, "vpcext $0x%x, $0x%x", buf[3], buf[2]);

176
librz/arch/p/asm/asm_x86_zydis.c Normal file
View file

@ -0,0 +1,176 @@
// SPDX-FileCopyrightText: 2013-2019 pancake <pancake@nopcode.org>
// SPDX-FileCopyrightText: 2024-2025 tushar3q34 <tushar3q34@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
#include <rz_asm.h>
#include <rz_lib.h>
#include <Zydis.h>
#include "asm_x86_vm.c"
typedef struct {
ZydisMachineMode omode;
ZydisStackWidth owidth;
ZydisFormatter oformat;
size_t obits;
} ZydisContext;
static bool x86_zydis_asm_init(void **user) {
ZydisContext *zydx = RZ_NEW0(ZydisContext);
if (!zydx) {
return false;
}
zydx->omode = -1;
*user = zydx;
return true;
}
static bool x86_zydis_asm_fini(void *p) {
if (!p) {
return true;
}
ZydisContext *zydx = (ZydisContext *)p;
free(zydx);
return true;
}
static char *x86_zydis_asm_mnemonics(RzAsm *a, int id, bool json) {
rz_return_val_if_fail(a && a->cur, NULL);
if (!a->plugin_data) {
return NULL;
}
a->cur->disassemble(a, NULL, NULL, -1);
if (id != -1) {
const char *vname = ZydisMnemonicGetString(id);
if (json) {
return vname ? rz_str_newf("[\"%s\"]\n", vname) : NULL;
}
return rz_str_dup(vname);
}
RzStrBuf *buf = rz_strbuf_new("");
if (json) {
rz_strbuf_append(buf, "[");
}
for (int i = 1;; i++) {
const char *op = ZydisMnemonicGetString(i);
if (!op) {
break;
}
if (json) {
rz_strbuf_append(buf, "\"");
}
rz_strbuf_append(buf, op);
if (!json) {
rz_strbuf_append(buf, "\n");
continue;
}
if (ZydisMnemonicGetString(i + 1)) {
rz_strbuf_append(buf, "\",");
} else {
rz_strbuf_append(buf, "\"]\n");
}
}
return rz_strbuf_drain(buf);
}
static int x86_zydis_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
rz_return_val_if_fail(a, 0);
ZydisContext *zydx = (ZydisContext *)a->plugin_data;
ut64 off = a->pc;
ZydisMachineMode mode = (a->bits == 64) ? ZYDIS_MACHINE_MODE_LONG_64 : (a->bits == 32) ? ZYDIS_MACHINE_MODE_LONG_COMPAT_32
: (a->bits == 16) ? ZYDIS_MACHINE_MODE_LONG_COMPAT_16
: 0;
ZydisStackWidth width = (a->bits == 64) ? ZYDIS_STACK_WIDTH_64 : (a->bits == 32) ? ZYDIS_STACK_WIDTH_32
: (a->bits == 16) ? ZYDIS_STACK_WIDTH_16
: 0;
if (op) {
op->size = 0;
}
if (zydx->omode != mode || zydx->owidth != width) {
zydx->omode = -1;
zydx->owidth = -1;
}
ZydisFormatter format;
if (a->syntax == RZ_ASM_SYNTAX_MASM) {
ZydisFormatterInit(&format, ZYDIS_FORMATTER_STYLE_INTEL_MASM);
} else if (a->syntax == RZ_ASM_SYNTAX_ATT) {
ZydisFormatterInit(&format, ZYDIS_FORMATTER_STYLE_ATT);
} else {
ZydisFormatterInit(&format, ZYDIS_FORMATTER_STYLE_INTEL);
}
ZydisFormatterSetProperty(&format, ZYDIS_FORMATTER_PROP_FORCE_SIZE, ZYAN_TRUE);
ZydisFormatterSetProperty(&format, ZYDIS_FORMATTER_PROP_HEX_UPPERCASE, ZYAN_FALSE);
ZydisFormatterSetProperty(&format, ZYDIS_FORMATTER_PROP_FORCE_RELATIVE_RIPREL, ZYAN_TRUE);
ZydisFormatterSetProperty(&format, ZYDIS_FORMATTER_PROP_ADDR_PADDING_ABSOLUTE, ZYDIS_PADDING_DISABLED);
if (!op) {
return true;
}
op->size = 1;
ZydisDecodedInstruction zydecode;
ZydisDecodedOperand zydeop[ZYDIS_MAX_OPERAND_COUNT];
ZydisDecoder decoder;
ZydisDecoderInit(&decoder, mode, width);
bool check = false;
while (ZYAN_SUCCESS(ZydisDecoderDecodeFull(
&decoder, buf, len, &zydecode, zydeop))) {
op->size = 0;
check = true;
break;
}
if (op->size == 0 && check && zydecode.length > 0) {
char *ptrstr;
op->size = zydecode.length;
char buf_asm[256] = { 0 };
ZydisFormatterFormatInstruction(&format, &zydecode, zydeop,
zydecode.operand_count_visible, buf_asm, sizeof(buf_asm), off, ZYAN_NULL);
ptrstr = strstr(buf_asm, "ptr ");
if (ptrstr) {
memmove(ptrstr, ptrstr + 4, strlen(ptrstr + 4) + 1);
}
rz_asm_op_set_asm(op, buf_asm);
} else {
decompile_vm(a, op, buf, len);
}
return op->size;
}
static bool x86_sw_breakpoint(RzAsm *a, RzAsmOp *op) {
// { 0, 1, 0, "\xcc" }, // valid for 16, 32, 64
// { 0, 2, 0, "\xcd\x03" },
rz_asm_op_set_buf(op, (const ut8 *)"\xcc", 1);
return true;
}
RzAsmPlugin rz_asm_plugin_x86_zydis = {
.name = "x86",
.desc = "X86/X86_64 Zydis-based disassembler",
.license = "MIT",
.arch = "x86",
.bits = 16 | 32 | 64,
.endian = RZ_SYS_ENDIAN_LITTLE,
.init = x86_zydis_asm_init,
.fini = x86_zydis_asm_fini,
.mnemonics = x86_zydis_asm_mnemonics,
.disassemble = &x86_zydis_disassemble,
.sw_breakpoint = x86_sw_breakpoint,
.features = "adox_adcx,aes,amd3dnow,amd3dnow_prefetch,amd_invlpgb,amx_bf16,"
"amx_fp16,amx_int8,amx_tile,avx,avx2,avx2gather,avx512evex,avx512vex,avxaes,"
"avx_ifma,avx_ne_convert,avx_vnni,avx_vnni_int16,avx_vnni_int8,base,bmi1,bmi2,"
"cet,cldemote,clflushopt,clfsh,clwb,clzero,enqcmd,f16c,fma,fma4,fred,gfni,"
"hreset,icache_prefetch,invpcid,keylocker,keylocker_wide,knc,knce,kncv,lkgs,"
"longmode,lzcnt,mcommit,mmx,monitor,monitorx,movbe,movdir,mpx,msrlist,padlock,"
"pause,pbndkb,pclmulqdq,pcommit,pconfig,pku,prefetchwt1,pt,rao_int,rdpid,rdpru,"
"rdrand,rdseed,rdtscp,rdwrfsgs,rtm,serialize,sgx,sgx_enclv,sha,sha512,sm3,sm4,"
"smap,smx,snp,sse,sse2,sse3,sse4,sse4a,ssse3,svm,tbm,tdx,tsx_ldtrk,uintr,vaes,"
"vmfunc,vpclmulqdq,vtx,waitpkg,wrmsrns,x87,xop,xsave,xsavec,xsaveopt,xsaves"
};
#ifndef RZ_PLUGIN_INCORE
RZ_API RzLibStruct rizin_plugin = {
.type = RZ_LIB_TYPE_ASM,
.data = &rz_asm_plugin_x86_zydis,
.version = RZ_VERSION
};
#endif

2
librz/arch/p/parse/parse_x86_pseudo.c → librz/arch/p/parse/parse_x86_pseudo_zydis.c
View file

@ -461,7 +461,7 @@ static bool subvar(RzParse *p, RzAnalysisFunction *f, RzAnalysisOp *op, char *da
return ret;
}
RzParsePlugin rz_parse_plugin_x86_cs_pseudo = {
RzParsePlugin rz_parse_plugin_x86_zydis_pseudo = {
.name = "x86.pseudo",
.desc = "X86 pseudo syntax",
.parse = &parse,

17
meson.build
View file

@ -242,6 +242,22 @@ if sys_magic_opt.enabled() or sys_magic_opt.auto()
endif
endif
# Handle Zydis library
sys_zydis_opt = get_option('use_sys_zydis')
zydis_dep = disabler()
if sys_zydis_opt.enabled() or sys_zydis_opt.auto()
zydis_dep = dependency('zydis', required: false, static: is_static_build)
if not zydis_dep.found()
zydis_dep = cc.find_library('zydis', required: sys_zydis_opt, static: is_static_build)
endif
endif
if (sys_zydis_opt.auto() and not zydis_dep.found()) or sys_zydis_opt.disabled()
zydis_proj = subproject('zydis', default_options: ['default_library=static'])
zydis_dep = zydis_proj.get_variable('zydis_dep')
add_project_arguments(['-DZYDIS_STATIC_BUILD'], language: 'c')
endif
# handle libmspack library
sys_libmspack_opt = get_option('use_sys_libmspack')
libmspack_dep = disabler()
@ -819,6 +835,7 @@ summary({
'System libmspack library': libmspack_dep.found() and libmspack_dep.type_name() != 'internal',
'System openssl library': sys_openssl.found() and sys_openssl.type_name() != 'internal',
'System capstone library': capstone_dep.found() and capstone_dep.type_name() != 'internal',
'System zydis library': zydis_dep.found() and zydis_dep.type_name() != 'internal',
'System tree-sitter library': tree_sitter_dep.found() and tree_sitter_dep.type_name() != 'internal',
'System lz4 library': lz4_dep.found() and lz4_dep.type_name() != 'internal',
'System lzma library': liblzma_dep.found() and liblzma_dep.type_name() != 'internal',

1
meson_options.txt
View file

@ -23,6 +23,7 @@ option('checks_level', type: 'integer', value: 2, description: 'Value between 0
option('use_sys_capstone', type: 'feature', value: 'disabled')
option('use_capstone_version', type: 'combo', choices: ['v4', 'v5', 'v6', 'next'], value: 'next', description: 'Specify which version of capstone to use')
option('use_sys_magic', type: 'feature', value: 'disabled')
option('use_sys_zydis', type: 'feature', value: 'disabled')
option('use_sys_libzip', type: 'feature', value: 'disabled')
option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip')
option('use_sys_zlib', type: 'feature', value: 'disabled')

1
subprojects/packagefiles/capstone-4.0.2/meson.build
View file

@ -81,7 +81,6 @@ libcapstone_c_args = [
'-DCAPSTONE_HAS_POWERPC',
'-DCAPSTONE_HAS_SPARC',
'-DCAPSTONE_HAS_SYSZ',
'-DCAPSTONE_HAS_X86',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_TMS320C64X',
]

1
subprojects/packagefiles/capstone-5.0.1/meson.build
View file

@ -87,7 +87,6 @@ libcapstone_c_args = [
'-DCAPSTONE_HAS_POWERPC',
'-DCAPSTONE_HAS_SPARC',
'-DCAPSTONE_HAS_SYSZ',
'-DCAPSTONE_HAS_X86',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_TMS320C64X',
'-DCAPSTONE_HAS_TRICORE',

1
subprojects/packagefiles/capstone-6.0.0-alpha4/meson.build
View file

@ -107,7 +107,6 @@ libcapstone_c_args = [
'-DCAPSTONE_HAS_POWERPC',
'-DCAPSTONE_HAS_SPARC',
'-DCAPSTONE_HAS_SYSTEMZ',
'-DCAPSTONE_HAS_X86',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_TMS320C64X',
'-DCAPSTONE_HAS_TRICORE',

55012
subprojects/packagefiles/zydis/amalgamated-dist/Zydis.c Normal file
View file

File diff suppressed because one or more lines are too long

12262
subprojects/packagefiles/zydis/amalgamated-dist/Zydis.h Normal file
View file

File diff suppressed because it is too large Load diff

55
subprojects/packagefiles/zydis/meson.build Normal file
View file

@ -0,0 +1,55 @@
project('zydis', 'c', version: '4.1.0', meson_version: '>=0.55.0')
cc = meson.get_compiler('c')
if cc.has_argument('--std=gnu99')
add_project_arguments('--std=gnu99', language: ['c'])
elif cc.has_argument('--std=c99')
add_project_arguments('--std=c99', language: ['c'])
endif
if cc.get_argument_syntax() == 'msvc'
if get_option('b_lto')
add_project_arguments(
'/GL', # Compiler optimisation for MSVC
language: 'c',
)
add_project_link_arguments(
'/LTCG', # Used for Linking when compiling with /GL
language: 'c',
)
endif
endif
zydis_c_args = []
if get_option('default_library') == 'static'
zydis_c_args += ['-DZYDIS_STATIC_BUILD']
else
zydis_c_args += ['-DZYDIS_SHOULD_EXPORT']
endif
if cc.get_id() == 'msvc'
add_project_arguments('/W0', language: 'c')
elif cc.has_argument('-w')
add_project_arguments('-w', language: 'c')
endif
zydis_sources = [
'amalgamated-dist/Zydis.c'
]
zydis_includes = [
'./amalgamated-dist'
]
libzydis = library('zydis', zydis_sources,
c_args: zydis_c_args,
include_directories: zydis_includes,
install: false,
)
zydis_dep = declare_dependency(
link_with: libzydis,
include_directories: zydis_includes,
)

7
subprojects/zydis.wrap Normal file
View file

@ -0,0 +1,7 @@
[wrap-file]
directory = zydis
source_url = https://github.com/zyantific/zydis/releases/download/v4.1.0/zydis-amalgamated.tar.gz
source_filename = zydis-amalgamated.tar.gz
source_hash = aa9b82be3a37a2998bd8e16cf583bbf2b6c3d80e97dc20504169dc32ca1ced59
lead_directory_missing = true
patch_directory = zydis

2
test/db/abi/compilers/pelles_c
View file

@ -20,7 +20,7 @@ EXPECT=<<EOF
108 * functions
38 * imports
0 * platform.ports
76 * pointers
66 * pointers
0 * registers
0 * registers.extended
0 * registers.mmio

6
test/db/abi/languages/rust
View file

@ -22,8 +22,8 @@ mov rdx, rsp
and rsp, 0xfffffffffffffff0
push rax
push rsp
lea r8, sym.__libc_csu_fini
lea rcx, sym.__libc_csu_init
lea rdi, main
lea r8, qword sym.__libc_csu_fini
lea rcx, qword sym.__libc_csu_init
lea rdi, qword main
EOF
RUN

4
test/db/analysis/golang
View file

@ -150,6 +150,9 @@ EXPECT=<<EOF
0x0066dc76 str.
0x0066e68d str.Addr
;-- str.flag:
;-- str.sort:
;-- str.sync:
;-- str.AAAA:
14534
bufio
bytes
@ -707,6 +710,7 @@ EOF
EXPECT=<<EOF
1788
0x004a699b str.hello__hacktivity
0x004a69d5 str.reflect.__funcTypeFixed64_.AssignableTo
9557
compiler go1.15 Linker 03.00
errors

158
test/db/analysis/vars
View file

@ -73,31 +73,31 @@ afvW
var_38h
var_36h
* var_648h
R 0x100001072 lea rax, [var_648h]
R 0x100001072 lea rax, qword [var_648h]
* var_650h
R 0x100001617 lea rbx, [var_650h]
R 0x100001691 lea rsi, [var_650h]
R 0x100001617 lea rbx, qword [var_650h]
R 0x100001691 lea rsi, qword [var_650h]
W 0x100001079 mov qword [var_650h], rax
* var_65ch
R 0x100001784 cmp dword [var_65ch], 0
W 0x100001137 mov dword [var_65ch], 0
W 0x100001315 mov dword [var_65ch], 1
R 0x100001784 cmp dword [var_65ch], 0x00
W 0x100001137 mov dword [var_65ch], 0x00
W 0x100001315 mov dword [var_65ch], 0x01
* var_658h
R 0x10000173c or ebx, dword [var_658h]
R 0x100001807 cmp dword [var_658h], 0
R 0x10000181c cmp dword [var_658h], 0
W 0x10000114c mov dword [var_658h], 0
W 0x1000014f2 mov dword [var_658h], 1
R 0x100001807 cmp dword [var_658h], 0x00
R 0x10000181c cmp dword [var_658h], 0x00
W 0x10000114c mov dword [var_658h], 0x00
W 0x1000014f2 mov dword [var_658h], 0x01
* var_654h
R 0x100001736 mov ebx, dword [var_654h]
R 0x1000017dd cmp dword [var_654h], 0
R 0x1000017f2 cmp dword [var_654h], 0
W 0x100001156 mov dword [var_654h], 0
W 0x1000012d8 mov dword [var_654h], 1
R 0x1000017dd cmp dword [var_654h], 0x00
R 0x1000017f2 cmp dword [var_654h], 0x00
W 0x100001156 mov dword [var_654h], 0x00
W 0x1000012d8 mov dword [var_654h], 0x01
* var_660h
R 0x1000017d4 cmp dword [var_660h], 0
W 0x100001160 mov dword [var_660h], 0
W 0x1000014ce mov dword [var_660h], 1
R 0x1000017d4 cmp dword [var_660h], 0x00
W 0x100001160 mov dword [var_660h], 0x00
W 0x1000014ce mov dword [var_660h], 0x01
* var_668h
R 0x1000018f1 mov rax, qword [var_668h]
W 0x100001597 mov qword [var_668h], rcx
@ -108,11 +108,11 @@ W 0x1000015a3 mov dword [var_66ch], eax
R 0x100001911 mov rsi, qword [var_678h]
W 0x1000015ad mov qword [var_678h], rax
* var_3ch
R 0x10000179e lea rdi, [var_3ch]
R 0x10000179e lea rdi, qword [var_3ch]
* var_448h
R 0x1000015f8 lea rdi, [var_448h]
R 0x1000015f8 lea rdi, qword [var_448h]
* var_38h
R 0x1000010d6 lea rdx, [var_38h]
R 0x1000010d6 lea rdx, qword [var_38h]
* var_36h
R 0x1000010f0 movzx eax, word [var_36h]
* argv
@ -146,31 +146,31 @@ afvxa
EOF
EXPECT=<<EOF
* var_648h
R 0x100001072 lea rax, [var_648h]
R 0x100001072 lea rax, qword [var_648h]
* var_650h
R 0x100001617 lea rbx, [var_650h]
R 0x100001691 lea rsi, [var_650h]
R 0x100001617 lea rbx, qword [var_650h]
R 0x100001691 lea rsi, qword [var_650h]
W 0x100001079 mov qword [var_650h], rax
* var_65ch
R 0x100001784 cmp dword [var_65ch], 0
W 0x100001137 mov dword [var_65ch], 0
W 0x100001315 mov dword [var_65ch], 1
R 0x100001784 cmp dword [var_65ch], 0x00
W 0x100001137 mov dword [var_65ch], 0x00
W 0x100001315 mov dword [var_65ch], 0x01
* var_658h
R 0x10000173c or ebx, dword [var_658h]
R 0x100001807 cmp dword [var_658h], 0
R 0x10000181c cmp dword [var_658h], 0
W 0x10000114c mov dword [var_658h], 0
W 0x1000014f2 mov dword [var_658h], 1
R 0x100001807 cmp dword [var_658h], 0x00
R 0x10000181c cmp dword [var_658h], 0x00
W 0x10000114c mov dword [var_658h], 0x00
W 0x1000014f2 mov dword [var_658h], 0x01
* var_654h
R 0x100001736 mov ebx, dword [var_654h]
R 0x1000017dd cmp dword [var_654h], 0
R 0x1000017f2 cmp dword [var_654h], 0
W 0x100001156 mov dword [var_654h], 0
W 0x1000012d8 mov dword [var_654h], 1
R 0x1000017dd cmp dword [var_654h], 0x00
R 0x1000017f2 cmp dword [var_654h], 0x00
W 0x100001156 mov dword [var_654h], 0x00
W 0x1000012d8 mov dword [var_654h], 0x01
* var_660h
R 0x1000017d4 cmp dword [var_660h], 0
W 0x100001160 mov dword [var_660h], 0
W 0x1000014ce mov dword [var_660h], 1
R 0x1000017d4 cmp dword [var_660h], 0x00
W 0x100001160 mov dword [var_660h], 0x00
W 0x1000014ce mov dword [var_660h], 0x01
* var_668h
R 0x1000018f1 mov rax, qword [var_668h]
W 0x100001597 mov qword [var_668h], rcx
@ -181,11 +181,11 @@ W 0x1000015a3 mov dword [var_66ch], eax
R 0x100001911 mov rsi, qword [var_678h]
W 0x1000015ad mov qword [var_678h], rax
* var_3ch
R 0x10000179e lea rdi, [var_3ch]
R 0x10000179e lea rdi, qword [var_3ch]
* var_448h
R 0x1000015f8 lea rdi, [var_448h]
R 0x1000015f8 lea rdi, qword [var_448h]
* var_38h
R 0x1000010d6 lea rdx, [var_38h]
R 0x1000010d6 lea rdx, qword [var_38h]
* var_36h
R 0x1000010f0 movzx eax, word [var_36h]
* argv
@ -225,31 +225,31 @@ afvxv
EOF
EXPECT=<<EOF
* var_648h
R 0x100001072 lea rax, [var_648h]
R 0x100001072 lea rax, qword [var_648h]
* var_650h
R 0x100001617 lea rbx, [var_650h]
R 0x100001691 lea rsi, [var_650h]
R 0x100001617 lea rbx, qword [var_650h]
R 0x100001691 lea rsi, qword [var_650h]
W 0x100001079 mov qword [var_650h], rax
* var_65ch
R 0x100001784 cmp dword [var_65ch], 0
W 0x100001137 mov dword [var_65ch], 0
W 0x100001315 mov dword [var_65ch], 1
R 0x100001784 cmp dword [var_65ch], 0x00
W 0x100001137 mov dword [var_65ch], 0x00
W 0x100001315 mov dword [var_65ch], 0x01
* var_658h
R 0x10000173c or ebx, dword [var_658h]
R 0x100001807 cmp dword [var_658h], 0
R 0x10000181c cmp dword [var_658h], 0
W 0x10000114c mov dword [var_658h], 0
W 0x1000014f2 mov dword [var_658h], 1
R 0x100001807 cmp dword [var_658h], 0x00
R 0x10000181c cmp dword [var_658h], 0x00
W 0x10000114c mov dword [var_658h], 0x00
W 0x1000014f2 mov dword [var_658h], 0x01
* var_654h
R 0x100001736 mov ebx, dword [var_654h]
R 0x1000017dd cmp dword [var_654h], 0
R 0x1000017f2 cmp dword [var_654h], 0
W 0x100001156 mov dword [var_654h], 0
W 0x1000012d8 mov dword [var_654h], 1
R 0x1000017dd cmp dword [var_654h], 0x00
R 0x1000017f2 cmp dword [var_654h], 0x00
W 0x100001156 mov dword [var_654h], 0x00
W 0x1000012d8 mov dword [var_654h], 0x01
* var_660h
R 0x1000017d4 cmp dword [var_660h], 0
W 0x100001160 mov dword [var_660h], 0
W 0x1000014ce mov dword [var_660h], 1
R 0x1000017d4 cmp dword [var_660h], 0x00
W 0x100001160 mov dword [var_660h], 0x00
W 0x1000014ce mov dword [var_660h], 0x01
* var_668h
R 0x1000018f1 mov rax, qword [var_668h]
W 0x100001597 mov qword [var_668h], rcx
@ -260,11 +260,11 @@ W 0x1000015a3 mov dword [var_66ch], eax
R 0x100001911 mov rsi, qword [var_678h]
W 0x1000015ad mov qword [var_678h], rax
* var_3ch
R 0x10000179e lea rdi, [var_3ch]
R 0x10000179e lea rdi, qword [var_3ch]
* var_448h
R 0x1000015f8 lea rdi, [var_448h]
R 0x1000015f8 lea rdi, qword [var_448h]
* var_38h
R 0x1000010d6 lea rdx, [var_38h]
R 0x1000010d6 lea rdx, qword [var_38h]
* var_36h
R 0x1000010f0 movzx eax, word [var_36h]
* argv
@ -413,9 +413,9 @@ afvW
| 0x0000000b 48897818 mov qword [var_s18h], rdi
| 0x0000000f 4157 push r15
| 0x00000011 4881ecb00000. sub rsp, 0xb0
| 0x00000018 8364242000 and dword [var_98h], 0
| 0x0000001d 488d4888 lea rcx, [var_78h]
| 0x00000021 4c8d9c24b000. lea r11, [var_8h]
| 0x00000018 8364242000 and dword [var_98h], 0x00
| 0x0000001d 488d4888 lea rcx, qword [var_78h]
| 0x00000021 4c8d9c24b000. lea r11, qword [var_8h]
| 0x00000029 498b5b10 mov rbx, qword [var_s8h]
| 0x0000002d 498b7318 mov rsi, qword [var_s10h]
| 0x00000031 498b7b20 mov rdi, qword [var_s18h]
@ -565,11 +565,11 @@ EXPECT=<<EOF
| 0x0000113c push rbp ; main.c:9
| 0x0000113d mov rbp, rsp
| 0x00001140 sub rsp, 0x10
| 0x00001144 mov dword [lightbulb], 1 ; main.c:15
| 0x0000114b mov dword [sun], 2 ; main.c:16
| 0x00001152 mov dword [last], 3 ; main.c:17
| 0x00001159 mov dword [chance], 4 ; main.c:18
| 0x00001160 mov eax, 0 ; main.c:20
| 0x00001144 mov dword [lightbulb], 0x01 ; main.c:15
| 0x0000114b mov dword [sun], 0x02 ; main.c:16
| 0x00001152 mov dword [last], 0x03 ; main.c:17
| 0x00001159 mov dword [chance], 0x04 ; main.c:18
| 0x00001160 mov eax, 0x00 ; main.c:20
| 0x00001165 call dbg.leaffunc
| 0x0000116a mov eax, dword [chance] ; main.c:22
| 0x0000116d mov dword [sun], eax
@ -609,11 +609,11 @@ EXPECT=<<EOF
| ; var int last @ stack - 0x8
| ; var int chance @ stack - 0x4
| 0x00001137 sub rsp, 0x10 ; main.c:9
| 0x0000113b mov dword [rsp], 1 ; main.c:15
| 0x00001142 mov dword [sun], 2 ; main.c:16
| 0x0000114a mov dword [last], 3 ; main.c:17
| 0x00001152 mov dword [chance], 4 ; main.c:18
| 0x0000115a mov eax, 0 ; main.c:20
| 0x0000113b mov dword [rsp], 0x01 ; main.c:15
| 0x00001142 mov dword [sun], 0x02 ; main.c:16
| 0x0000114a mov dword [last], 0x03 ; main.c:17
| 0x00001152 mov dword [chance], 0x04 ; main.c:18
| 0x0000115a mov eax, 0x00 ; main.c:20
| 0x0000115f call dbg.leaffunc
| 0x00001164 mov eax, dword [chance] ; main.c:22
| 0x00001168 mov dword [sun], eax
@ -645,7 +645,7 @@ EXPECT=<<EOF
| 0x0000113a mov rbp, rsp
| 0x0000113d sub rsp, 0x30
| 0x00001141 mov dword [num], edi ; arg1
| 0x00001144 mov dword [int_one], 1 ; example.c:4
| 0x00001144 mov dword [int_one], 0x01 ; example.c:4
| 0x0000114b mov qword [long_twenty], 0x14 ; example.c:5
| 0x00001153 mov word [minus_seven], 0xfff9 ; example.c:6
| 0x00001159 mov edx, dword [int_one] ; example.c:7
@ -655,10 +655,10 @@ EXPECT=<<EOF
| 0x00001162 add eax, eax
| 0x00001164 mov dword [mult_int], eax
| 0x00001167 mov rax, qword [long_twenty] ; example.c:8
| 0x0000116b add rax, 7
| 0x0000116b add rax, 0x07
| 0x0000116f mov qword [add_long], rax
| 0x00001173 movzx eax, word [minus_seven] ; example.c:9
| 0x00001177 sub eax, 9
| 0x00001177 sub eax, 0x09
| 0x0000117a mov word [sub_short], ax
| 0x0000117e movsx esi, word [sub_short] ; example.c:11
| 0x00001182 mov rcx, qword [add_long]
@ -666,11 +666,11 @@ EXPECT=<<EOF
| 0x00001189 mov eax, dword [num]
| 0x0000118c mov r8d, esi
| 0x0000118f mov esi, eax
| 0x00001191 lea rax, str.result__d__d__ld__ld ; 0x2004 ; "result %d %d %ld %ld\n"
| 0x00001191 lea rax, qword str.result__d__d__ld__ld ; 0x2004 ; "result %d %d %ld %ld\n"
| 0x00001198 mov rdi, rax ; const char *format
| 0x0000119b mov eax, 0
| 0x0000119b mov eax, 0x00
| 0x000011a0 call sym.imp.printf ; int printf(const char *format)
| 0x000011a5 mov eax, 0xa ; example.c:13
| 0x000011a5 mov eax, 0x0a ; example.c:13
| 0x000011aa leave ; example.c:14
\ 0x000011ab ret
EOF

8
test/db/analysis/x86_16
View file

@ -480,25 +480,25 @@ EXPECT=<<EOF
},
"sign": false,
"prefix": 0,
"id": 612,
"id": 668,
"opex": {
"operands": [
{
"size": 2,
"rw": 1,
"type": "reg",
"value": "flags"
"value": "eflags"
}
]
},
"addr": 0,
"bytes": "9c",
"size": 1,
"type": "upush",
"type": "rpush",
"esilcost": 0,
"scale": 0,
"refptr": 0,
"cycles": 2,
"cycles": 1,
"failcycles": 0,
"delay": 0,
"stack": "inc",

150
test/db/analysis/x86_32
View file

@ -26,8 +26,8 @@ EOF
EXPECT=<<EOF
/ (loc) entry0(int32_t arg_31h, int32_t arg_44h);
| 0x006453a1 e8d8170000 call fcn.00646b7e
| 0x006453a6 8d642444 lea esp, [arg_44h]
| ,=< 0x006453aa 0f85a6300000 jne 0x648456
| 0x006453a6 8d642444 lea esp, dword [arg_44h]
| ,=< 0x006453aa 0f85a6300000 jnz 0x648456
EOF
RUN
@ -1151,7 +1151,7 @@ s f000:ffaa
pi 1
EOF
EXPECT=<<EOF
jmp 0xf0070
jmp 0x70
EOF
RUN
@ -2759,7 +2759,7 @@ EXPECT=<<EOF
| ----------- true: 0x0000118a
int main(int argc, char **argv, char **envp);
0x00001184 31c0 xor eax, eax
0x00001186 75f8 jne loc.start2
0x00001186 75f8 jnz loc.start2
| ----------- true: 0x00001180 false: 0x00001188
0x00001188 ebf6 jmp loc.start2
| ----------- true: 0x00001180
@ -2864,7 +2864,7 @@ b 0x80
pIf
EOF
EXPECT=<<EOF
push 0
push 0x00
dec eax
mov ebp, esp
dec eax
@ -2872,22 +2872,22 @@ and esp, 0xfffffff0
dec eax
mov edi, dword [arg_4h]
dec eax
lea esi, [arg_ch]
lea esi, dword [arg_ch]
mov edx, edi
add edx, 1
shl edx, 3
add edx, 0x01
shl edx, 0x03
dec eax
add edx, esi
dec eax
mov ecx, edx
jmp 0x25
dec eax
add ecx, 8
add ecx, 0x08
dec eax
cmp dword [ecx], 0
jne 0x21
cmp dword [ecx], 0x00
jnz 0x21
dec eax
add ecx, 8
add ecx, 0x08
call 0xf8c
mov edi, eax
call 0x3956
@ -2911,7 +2911,7 @@ af
pIf @ 0
EOF
EXPECT=<<EOF
push 0
push 0x00
dec eax
mov ebp, esp
dec eax
@ -2919,22 +2919,22 @@ and esp, 0xfffffff0
dec eax
mov edi, dword [arg_4h]
dec eax
lea esi, [arg_ch]
lea esi, dword [arg_ch]
mov edx, edi
add edx, 1
shl edx, 3
add edx, 0x01
shl edx, 0x03
dec eax
add edx, esi
dec eax
mov ecx, edx
jmp 0x25
dec eax
add ecx, 8
add ecx, 0x08
dec eax
cmp dword [ecx], 0
jne 0x21
cmp dword [ecx], 0x00
jnz 0x21
dec eax
add ecx, 8
add ecx, 0x08
call 0xf8c
mov edi, eax
call 0x3956
@ -3205,7 +3205,7 @@ EXPECT=<<EOF
},
"sign": false,
"prefix": 0,
"id": 1503,
"id": 1771,
"opex": {
"operands": [
{
@ -3683,7 +3683,7 @@ EXPECT=<<EOF
},
"sign": false,
"prefix": 0,
"id": 612,
"id": 668,
"opex": {
"operands": [
{
@ -3697,11 +3697,11 @@ EXPECT=<<EOF
"addr": 0,
"bytes": "669c",
"size": 2,
"type": "upush",
"type": "rpush",
"esilcost": 12,
"scale": 0,
"refptr": 0,
"cycles": 2,
"cycles": 1,
"failcycles": 0,
"delay": 0,
"stack": "inc",
@ -3739,8 +3739,8 @@ EXPECT=<<EOF
│ ┌─< 0x00000004 jb 0x50
│ ┌──< 0x00000006 jmp 0x7a
││ 0x00000008 nop
││ 0x00000009 lea esi, [esi]
│ ┌───> 0x00000010 lea edi, [esi + 1]
││ 0x00000009 lea esi, dword [esi]
│ ┌───> 0x00000010 lea edi, dword [esi+0x01]
│ ╎││ 0x00000013 xor edx, edx
│ ╎││ 0x00000015 mov eax, ebp
│ ╎││ 0x00000017 div ecx
@ -3750,14 +3750,14 @@ EXPECT=<<EOF
│ ╎││ 0x00000021 div ecx
│ ╎││ 0x00000023 cmp dword [arg_1ch], eax
│ ┌────< 0x00000027 jbe 0x90
│ │╎││ 0x00000029 mov edx, dword [ebx + 0x208]
│ │╎││ 0x00000029 mov edx, dword [ebx+0x208]
│ │╎││ 0x0000002f mov eax, dword [edx]
│ │╎││ 0x00000031 mov edx, dword [eax + 0x14]
│ │╎││ 0x00000034 cmp edx, dword [eax + 0x18]
│ ┌─────< 0x00000037 jae 0xa6
│ ││╎││ 0x00000039 mov byte [edx], 9
│ ││╎││ 0x0000003c add edx, 1
│ ││╎││ 0x0000003f mov dword [eax + 0x14], edx
│ │╎││ 0x00000031 mov edx, dword [eax+0x14]
│ │╎││ 0x00000034 cmp edx, dword [eax+0x18]
│ ┌─────< 0x00000037 jnb 0xa6
│ ││╎││ 0x00000039 mov byte [edx], 0x09
│ ││╎││ 0x0000003c add edx, 0x01
│ ││╎││ 0x0000003f mov dword [eax+0x14], edx
│ ││╎││ 0x00000042 mov eax, esi
│ ││╎││ 0x00000044 xor edx, edx
│ ││╎││ 0x00000046 add esi, ecx
@ -3765,13 +3765,13 @@ EXPECT=<<EOF
│ ││╎││ 0x0000004a sub esi, edx
│ ││╎││ 0x0000004c cmp ebp, esi
│ ┌──────< 0x0000004e jbe 0x7a
│ │││╎│└─> 0x00000050 mov ecx, dword [ebx + 0x58c]
│ │││╎│└─> 0x00000050 mov ecx, dword [ebx+0x58c]
│ │││╎│ 0x00000056 test ecx, ecx
│ │││└───< 0x00000058 jne 0x10
│ │││ │ 0x0000005a add esi, 1
│ │││ │ 0x0000005d mov edx, dword [ebx + 0x208]
│ │││└───< 0x00000058 jnz 0x10
│ │││ │ 0x0000005a add esi, 0x01
│ │││ │ 0x0000005d mov edx, dword [ebx+0x208]
│ │││ │ 0x00000063 mov eax, dword [edx]
│ │││ │ 0x00000065 mov edx, dword [eax + 0x14]
│ │││ │ 0x00000065 mov edx, dword [eax+0x14]
EOF
RUN
@ -3802,8 +3802,8 @@ EXPECT=<<EOF
| ,=< 0x00000004 jb 0x50
| ,==< 0x00000006 jmp 0x7a
|| 0x00000008 nop
|| 0x00000009 lea esi, [esi]
| .---> 0x00000010 lea edi, [esi + 1]
|| 0x00000009 lea esi, dword [esi]
| .---> 0x00000010 lea edi, dword [esi+0x01]
| :|| 0x00000013 xor edx, edx
| :|| 0x00000015 mov eax, ebp
| :|| 0x00000017 div ecx
@ -3813,14 +3813,14 @@ EXPECT=<<EOF
| :|| 0x00000021 div ecx
| :|| 0x00000023 cmp dword [arg_1ch], eax
| ,====< 0x00000027 jbe 0x90
| |:|| 0x00000029 mov edx, dword [ebx + 0x208]
| |:|| 0x00000029 mov edx, dword [ebx+0x208]
| |:|| 0x0000002f mov eax, dword [edx]
| |:|| 0x00000031 mov edx, dword [eax + 0x14]
| |:|| 0x00000034 cmp edx, dword [eax + 0x18]
| ,=====< 0x00000037 jae 0xa6
| ||:|| 0x00000039 mov byte [edx], 9
| ||:|| 0x0000003c add edx, 1
| ||:|| 0x0000003f mov dword [eax + 0x14], edx
| |:|| 0x00000031 mov edx, dword [eax+0x14]
| |:|| 0x00000034 cmp edx, dword [eax+0x18]
| ,=====< 0x00000037 jnb 0xa6
| ||:|| 0x00000039 mov byte [edx], 0x09
| ||:|| 0x0000003c add edx, 0x01
| ||:|| 0x0000003f mov dword [eax+0x14], edx
| ||:|| 0x00000042 mov eax, esi
| ||:|| 0x00000044 xor edx, edx
| ||:|| 0x00000046 add esi, ecx
@ -3828,13 +3828,13 @@ EXPECT=<<EOF
| ||:|| 0x0000004a sub esi, edx
| ||:|| 0x0000004c cmp ebp, esi
| ,======< 0x0000004e jbe 0x7a
| |||:|`-> 0x00000050 mov ecx, dword [ebx + 0x58c]
| |||:|`-> 0x00000050 mov ecx, dword [ebx+0x58c]
| |||:| 0x00000056 test ecx, ecx
| |||`===< 0x00000058 jne 0x10
| ||| | 0x0000005a add esi, 1
| ||| | 0x0000005d mov edx, dword [ebx + 0x208]
| |||`===< 0x00000058 jnz 0x10
| ||| | 0x0000005a add esi, 0x01
| ||| | 0x0000005d mov edx, dword [ebx+0x208]
| ||| | 0x00000063 mov eax, dword [edx]
| ||| | 0x00000065 mov edx, dword [eax + 0x14]
| ||| | 0x00000065 mov edx, dword [eax+0x14]
EOF
RUN
@ -3895,7 +3895,7 @@ EXPECT=<<EOF
| 0x00000025 89442408 mov dword [var_8h], eax
| 0x00000029 8b542414 mov edx, dword [arg_4h]
| 0x0000002d 8b44240c mov eax, dword [var_4h]
| 0x00000031 8d0c02 lea ecx, [edx + eax]
| 0x00000031 8d0c02 lea ecx, dword [edx+eax*1]
| 0x00000034 8b44242c mov eax, dword [arg_1ch]
| 0x00000038 99 cdq
| 0x00000039 f7f9 idiv ecx
@ -3932,7 +3932,7 @@ mnemonic: nop
description: no operation
mask: ff
prefix: 0
id: 510
id: 487
bytes: 90
refptr: 0
size: 1
@ -3954,7 +3954,7 @@ s 0x00402130
axt
EOF
EXPECT=<<EOF
(nofunc) 0x4010d1 [DATA] lea edx, [ebx*4 + str.Y_B]
(nofunc) 0x4010d1 [DATA] lea edx, dword [ebx*4+str.Y_B]
EOF
RUN
@ -4111,9 +4111,9 @@ EXPECT=<<EOF
| 0x00000000 push ebp
| 0x00000001 mov esp, ebp
| 0x00000003 sub esp, 0x40
| 0x00000006 mov dword [var_40h], 4
| 0x0000000e mov dword [var_3ch], 8
| 0x00000016 mov dword [var_38h], 0xc ; [0xc:4]=0x44c70000
| 0x00000006 mov dword [var_40h], 0x04
| 0x0000000e mov dword [var_3ch], 0x08
| 0x00000016 mov dword [var_38h], 0x0c ; [0xc:4]=0x44c70000
| 0x0000001e push dword [var_3ch]
\ 0x00000022 ret
EOF
@ -4151,44 +4151,44 @@ pd 10 @ 0x08049410
EOF
EXPECT=<<EOF
/ int main(int argc, char **argv, char **envp);
| 0x080491ca 0 lea ecx, [argc]
| 0x080491ca 0 lea ecx, dword [argc]
| 0x080491ce 0 and esp, 0xfffffff0
| 0x080491d1 0 -= 4 push dword [ecx - 4]
| 0x080491d1 0 -= 4 push dword [ecx-0x04]
| 0x080491d4 -4 -= 4 push ebp
| 0x080491d5 -8 mov ebp, esp
| 0x080491d7 -8 -= 4 push ecx
| 0x080491d8 -12 -= 36 sub esp, 0x24
| 0x080491db -48 mov eax, ecx
| 0x080491dd -48 mov edx, dword [eax + 4]
| 0x080491dd -48 mov edx, dword [eax+0x04]
| 0x080491e0 -48 mov dword [var_24h], edx
| 0x080491e3 -48 mov ecx, dword gs:[0x14]
| 0x080491ea -48 mov dword [var_14h], ecx
| 0x080491ed -48 xor ecx, ecx
| 0x080491ef -48 -= 4 sub esp, 4
| 0x080491ef -48 -= 4 sub esp, 0x04
| 0x080491f2 -52 -= 4 push dword [var_24h]
| 0x080491f5 -56 -= 4 push dword [eax]
| 0x080491f7 -60 lea eax, [var_20h]
| 0x080491f7 -60 lea eax, dword [var_20h]
| 0x080491fa -60 -= 4 push eax
| 0x080491fb -64 call sym.Aeropause
| 0x08049200 -64 += 16 add esp, 0x10
| 0x08049203 -48 mov eax, 0
| 0x08049203 -48 mov eax, 0x00
| 0x08049208 -48 mov edx, dword [var_14h]
| 0x0804920b -48 xor edx, dword gs:[0x14]
| ,=< 0x08049212 -48 je 0x8049219
| ,=< 0x08049212 -48 jz 0x8049219
| | 0x08049214 -48 call sym.imp.__stack_chk_fail ; void __stack_chk_fail(void)
| `-> 0x08049219 -48 mov ecx, dword [var_ch]
| 0x0804921c -48 := 0 leave
| 0x0804921d 0 lea esp, [ecx - 4]
| 0x0804921d 0 lea esp, dword [ecx-0x04]
\ 0x08049220 0 += 4 ret
--- in jumptable
| ;-- case 3: ; from 0x80493cf
| 0x08049410 -12 -= 12 sub esp, 0xc
| 0x08049410 -12 -= 12 sub esp, 0x0c
| 0x08049413 -24 -= 4 push str.echoes ; 0x804a032 ; "echoes"
| 0x08049418 -28 call sym.imp.printf
| 0x0804941d -28 += 16 add esp, 0x10
| ,=< 0x08049420 -12 jmp 0x8049447
| | ;-- case 4: ; from 0x80493cf
| | 0x08049422 -12 -= 12 sub esp, 0xc
| | 0x08049422 -12 -= 12 sub esp, 0x0c
| | 0x08049425 -24 -= 4 push str.wall ; 0x804a039 ; "wall"
| | 0x0804942a -28 call sym.imp.printf
| | 0x0804942f -28 += 16 add esp, 0x10
@ -4212,24 +4212,24 @@ EXPECT=<<EOF
..
| || ; CODE XREF from entry0 @ 0x401000
| |`-> 0x00401012 mov eax, dword [0x411133] ; [0x411133:4]=0
| | 0x00401017 shl eax, 2
| | 0x0040101a mov dword [0x411137], eax ; [0x411137:4]=0
| | 0x00401017 shl eax, 0x02
| | 0x0040101a mov dword [0x411137], eax
| | 0x0040101f push edx
| | 0x00401020 push 0
| | 0x00401020 push 0x00
| | 0x00401022 call sub.KERNEL32.DLL_GetModuleHandleA
| | 0x00401027 mov edx, eax
| | 0x00401029 call fcn.0040710c
| | 0x0040102e pop edx
| | 0x0040102f call fcn.004064a8
| | 0x00401034 call fcn.00407110
| | 0x00401039 push 0
| | 0x00401039 push 0x00
| | 0x0040103b call fcn.00408058
| | 0x00401040 pop ecx
| | 0x00401041 push 0x4110dc
| | 0x00401046 push 0
| | 0x00401046 push 0x00
| | 0x00401048 call sub.KERNEL32.DLL_GetModuleHandleA
| | 0x0040104d mov dword [0x41113b], eax ; [0x41113b:4]=0
| | 0x00401052 push 0
| | 0x0040104d mov dword [0x41113b], eax
| | 0x00401052 push 0x00
\ |,=< 0x00401054 jmp fcn.0040dfd0
EOF
RUN

412
test/db/analysis/x86_64
View file

@ -69,9 +69,9 @@ EXPECT=<<EOF
0x000048f4 0x00004901 00:0000 13 j 0x000045b1 f 0x00004901
0x00004901 0x0000491a 00:0000 25 j 0x000045ba f 0x0000491a
| 0x000039c2 mov dword [data.0021f558], 2 ; [0x21f558:4]=1
| 0x000039c2 mov dword [data.0021f558], 0x02 ; [0x21f558:4]=1
| 0x000039cc call fcn.00015960
| 0x000039d1 mov byte [data.00220618], 1 ; [0x220618:1]=0
| 0x000039d1 mov byte [data.00220618], 0x01 ; [0x220618:1]=0
EOF
RUN
@ -484,7 +484,7 @@ EXPECT=<<EOF
| 0x00003ec4 jmp rax ; switch table (275 cases) at 0x172d8
| ; CODE XREF from main @ 0x3ec4
| ;-- case 110: ; from 0x3ec4
| 0x00003ec6 mov byte [0x00021260], 1 ; [0x21260:1]=0
| 0x00003ec6 mov byte [0x00021260], 0x01 ; [0x21260:1]=0
EOF
RUN
@ -519,30 +519,30 @@ afvd
EOF
EXPECT=<<EOF
/ fcn.00487350();
| 0x00487350 8b8710030000 mov eax, dword [rdi + 0x310]
| 0x00487356 48b900000000. movabs rcx, 0x200000000
| 0x00487360 8d50ff lea edx, [rax - 1]
| 0x00487363 48b8ffffffff. movabs rax, 0x3ffffffff
| 0x0048736d 899710030000 mov dword [rdi + 0x310], edx
| 0x00487373 482387100300. and rax, qword [rdi + 0x310]
| 0x00487350 8b8710030000 mov eax, dword [rdi+0x310]
| 0x00487356 48b900000000. mov rcx, 0x200000000
| 0x00487360 8d50ff lea edx, qword [rax-0x01]
| 0x00487363 48b8ffffffff. mov rax, 0x3ffffffff
| 0x0048736d 899710030000 mov dword [rdi+0x310], edx
| 0x00487373 482387100300. and rax, qword [rdi+0x310]
| 0x0048737a 4839c8 cmp rax, rcx
| 0x0048737d 7411 je 0x487390
| 0x0048737d 7411 jz 0x487390
| ----------- true: 0x00487390 false: 0x0048737f
| 0x0048737f f605d2542300. test byte [0x006bc858], 0x40
| 0x00487386 7525 jne 0x4873ad
| 0x00487386 7525 jnz 0x4873ad
| ----------- true: 0x004873ad false: 0x00487388
| 0x00487388 f3c3 repz ret
| 0x00487388 f3c3 ret
| 0x00487390 8b05ea4d2300 mov eax, dword [0x006bc180]
| 0x00487396 85c0 test eax, eax
| 0x00487398 7426 je 0x4873c0
| 0x00487398 7426 jz 0x4873c0
| ----------- true: 0x004873c0 false: 0x0048739a
| 0x0048739a f605b7542300. test byte [0x006bc858], 0x40
| 0x004873a1 c705d54d2300. mov dword [0x006bc180], 2
| 0x004873ab 74db je 0x487388
| 0x004873a1 c705d54d2300. mov dword [0x006bc180], 0x02
| 0x004873ab 74db jz 0x487388
| ----------- true: 0x00487388 false: 0x004873ad
| 0x004873ad 488b7708 mov rsi, qword [rdi + 8]
| 0x004873b1 488d3dd03502. lea rdi, str.closing_file__s__direct_opencount__u
| 0x004873ad 488b7708 mov rsi, qword [rdi+0x08]
| 0x004873b1 488d3dd03502. lea rdi, qword str.closing_file__s__direct_opencount__u
| 0x004873b8 31c0 xor eax, eax
| 0x004873ba e9b16cffff jmp fcn.0047e070
| ----------- true: 0x0047e070
@ -954,38 +954,38 @@ s 0x000113bd
pd 28
EOF
EXPECT=<<EOF
| ,=< 0x000113bd je 0x1144e
| ,=< 0x000113bd jz 0x1144e
| | 0x000113c3 mov esi, 0x2f ; '/' ; int c
| | 0x000113c8 call sym.imp.strrchr ; char *strrchr(const char *s, int c)
| | 0x000113cd test rax, rax
| ,==< 0x000113d0 je 0x11424
| || 0x000113d2 lea rdx, [rax + 1]
| ,==< 0x000113d0 jz 0x11424
| || 0x000113d2 lea rdx, qword [rax+0x01]
| || 0x000113d6 mov rcx, rdx
| || 0x000113d9 sub rcx, rbx
| || 0x000113dc cmp rcx, 6
| || 0x000113dc cmp rcx, 0x06
| ,===< 0x000113e0 jle 0x11424
| ||| 0x000113e2 lea rsi, [rax - 6]
| ||| 0x000113e6 mov ecx, 7
| ||| 0x000113eb lea rdi, [rip + 0x7ebb] ; str..libs
| ||| 0x000113e2 lea rsi, qword [rax-0x06]
| ||| 0x000113e6 mov ecx, 0x07
| ||| 0x000113eb lea rdi, qword [rip+0x7ebb] ; str..libs
| ||| ; 0x192ad ; "/.libs/"
| ||| 0x000113f2 repe cmpsb byte [rsi], byte ptr [rdi]
| ,====< 0x000113f4 jne 0x11424
| |||| 0x000113f6 mov ecx, 3
| ||| 0x000113f2 repe cmpsb
| ,====< 0x000113f4 jnz 0x11424
| |||| 0x000113f6 mov ecx, 0x03
| |||| 0x000113fb mov rsi, rdx
| |||| 0x000113fe mov rbx, rdx
| |||| 0x00011401 lea rdi, [rip + 0x7ead] ; data.000192b5
| |||| 0x00011401 lea rdi, qword [rip+0x7ead] ; data.000192b5
| |||| ; 0x192b5 ; "lt-"
| |||| 0x00011408 repe cmpsb byte [rsi], byte ptr [rdi]
| |||| 0x0001140a seta sil
| |||| 0x00011408 repe cmpsb
| |||| 0x0001140a setnbe sil
| |||| 0x0001140e setb cl
| |||| 0x00011411 cmp sil, cl
| ,=====< 0x00011414 jne 0x11424
| ||||| 0x00011416 lea rbx, [rax + 4]
| ||||| 0x0001141a mov rax, qword [rip + 0xdeaf] ; reloc.program_invocation_short_name
| ,=====< 0x00011414 jnz 0x11424
| ||||| 0x00011416 lea rbx, qword [rax+0x04]
| ||||| 0x0001141a mov rax, qword [rip+0xdeaf] ; reloc.program_invocation_short_name
| ||||| ; [0x1f2d0:8]=0x21ba0 reloc.target.program_invocation_short_name
| ||||| 0x00011421 mov qword [rax], rbx
| ||||| ; CODE XREFS from fcn.00011390 @ 0x113d0, 0x113e0, 0x113f4, 0x11414
| ````--> 0x00011424 mov rax, qword [rip + 0xde3d] ; data.0001f268
| ````--> 0x00011424 mov rax, qword [rip+0xde3d] ; data.0001f268
| | ; [0x1f268:8]=0x21680
EOF
RUN
@ -1005,33 +1005,33 @@ s 0x00003ca6
pd 19
EOF
EXPECT=<<EOF
| 0x00003ca6 cmp eax, 2
| ,=< 0x00003ca9 je 0x45ec
| | 0x00003caf cmp eax, 3
| ,==< 0x00003cb2 je 0x3ce3
| || 0x00003cb4 sub eax, 1
| ,===< 0x00003cb7 je 0x3cbe
| 0x00003ca6 cmp eax, 0x02
| ,=< 0x00003ca9 jz 0x45ec
| | 0x00003caf cmp eax, 0x03
| ,==< 0x00003cb2 jz 0x3ce3
| || 0x00003cb4 sub eax, 0x01
| ,===< 0x00003cb7 jz 0x3cbe
| ||| ; CODE XREFS from main @ 0x58bc, 0x58d2
| ||| ;-- default: ; from 0x58d2
| ||| 0x00003cb9 call sym.imp.abort ; void abort(void)
| ||| ; CODE XREF from main @ 0x3cb7
| `---> 0x00003cbe mov edi, 1 ; int fd
| `---> 0x00003cbe mov edi, 0x01 ; int fd
| || 0x00003cc3 call sym.imp.isatty ; int isatty(int fd)
| || 0x00003cc8 test eax, eax
| ,===< 0x00003cca je 0x4c2e
| ||| 0x00003cd0 mov dword [rip + 0x1d626], 2 ; data.00021300
| ,===< 0x00003cca jz 0x4c2e
| ||| 0x00003cd0 mov dword [rip+0x1d626], 0x02 ; data.00021300
| ||| ; [0x21300:4]=0
| ||| 0x00003cda mov byte [rip + 0x1d33f], 1 ; data.00021020
| ||| 0x00003cda mov byte [rip+0x1d33f], 0x01 ; data.00021020
| ||| ; [0x21020:1]=0
| ,====< 0x00003ce1 jmp 0x3cf9
| |||| ; CODE XREF from main @ 0x3cb2
| ||`--> 0x00003ce3 mov esi, 5 ; int64_t arg2
| ||`--> 0x00003ce3 mov esi, 0x05 ; int64_t arg2
| || | 0x00003ce8 xor edi, edi ; int64_t arg1
| || | 0x00003cea mov dword [rip + 0x1d60c], 0 ; data.00021300
| || | 0x00003cea mov dword [rip+0x1d60c], 0x00 ; data.00021300
| || | ; [0x21300:4]=0
| || | 0x00003cf4 call fcn.00012740
| || | ; CODE XREFS from main @ 0x3ce1, 0x4602, 0x4c38
| `----> 0x00003cf9 lea rdi, [rip + 0x14fb4] ; str.QUOTING_STYLE
| `----> 0x00003cf9 lea rdi, qword [rip+0x14fb4] ; str.QUOTING_STYLE
| | | ; 0x18cb4 ; "QUOTING_STYLE" ; const char *name
EOF
RUN
@ -1052,33 +1052,33 @@ s 0x00003ca6
pd 19
EOF
EXPECT=<<EOF
| 0x00003ca6 cmp eax, 2
| ,==< 0x00003ca9 je 0x45ec
| | 0x00003caf cmp eax, 3
| ,====< 0x00003cb2 je 0x3ce3
| | | 0x00003cb4 sub eax, 1
| ,======< 0x00003cb7 je 0x3cbe
| 0x00003ca6 cmp eax, 0x02
| ,==< 0x00003ca9 jz 0x45ec
| | 0x00003caf cmp eax, 0x03
| ,====< 0x00003cb2 jz 0x3ce3
| | | 0x00003cb4 sub eax, 0x01
| ,======< 0x00003cb7 jz 0x3cbe
| | | | ; CODE XREFS from main @ 0x58bc, 0x58d2
| | | | ;-- default: ; from 0x58d2
| | | | 0x00003cb9 call sym.imp.abort ; void abort(void)
| | | | ; CODE XREF from main @ 0x3cb7
| `------> 0x00003cbe mov edi, 1 ; int fd
| `------> 0x00003cbe mov edi, 0x01 ; int fd
| | | 0x00003cc3 call sym.imp.isatty ; int isatty(int fd)
| | | 0x00003cc8 test eax, eax
| ,======< 0x00003cca je 0x4c2e
| | | | 0x00003cd0 mov dword [rip + 0x1d626], 2 ; data.00021300
| ,======< 0x00003cca jz 0x4c2e
| | | | 0x00003cd0 mov dword [rip+0x1d626], 0x02 ; data.00021300
| | | | ; [0x21300:4]=0
| | | | 0x00003cda mov byte [rip + 0x1d33f], 1 ; data.00021020
| | | | 0x00003cda mov byte [rip+0x1d33f], 0x01 ; data.00021020
| | | | ; [0x21020:1]=0
| ========< 0x00003ce1 jmp 0x3cf9
| | | | ; CODE XREF from main @ 0x3cb2
| | `----> 0x00003ce3 mov esi, 5 ; int64_t arg2
| | `----> 0x00003ce3 mov esi, 0x05 ; int64_t arg2
| | | 0x00003ce8 xor edi, edi ; int64_t arg1
| | | 0x00003cea mov dword [rip + 0x1d60c], 0 ; data.00021300
| | | 0x00003cea mov dword [rip+0x1d60c], 0x00 ; data.00021300
| | | ; [0x21300:4]=0
| | | 0x00003cf4 call fcn.00012740
| | | ; CODE XREFS from main @ 0x3ce1, 0x4602, 0x4c38
| --------> 0x00003cf9 lea rdi, [rip + 0x14fb4] ; str.QUOTING_STYLE
| --------> 0x00003cf9 lea rdi, qword [rip+0x14fb4] ; str.QUOTING_STYLE
| | | ; 0x18cb4 ; "QUOTING_STYLE" ; const char *name
EOF
RUN
@ -1098,33 +1098,33 @@ s 0x00003ca6
pd 19
EOF
EXPECT=<<EOF
| 0x00003ca6 cmp eax, 2
| ,==< 0x00003ca9 je 0x45ec
| | 0x00003caf cmp eax, 3
| ,====< 0x00003cb2 je 0x3ce3
| | | 0x00003cb4 sub eax, 1
| ,======< 0x00003cb7 je 0x3cbe
| 0x00003ca6 cmp eax, 0x02
| ,==< 0x00003ca9 jz 0x45ec
| | 0x00003caf cmp eax, 0x03
| ,====< 0x00003cb2 jz 0x3ce3
| | | 0x00003cb4 sub eax, 0x01
| ,======< 0x00003cb7 jz 0x3cbe
| | | | ; CODE XREFS from main @ 0x58bc, 0x58d2
| | | | ;-- default: ; from 0x58d2
| | | | 0x00003cb9 call sym.imp.abort ; void abort(void)
| | | | ; CODE XREF from main @ 0x3cb7
| `------> 0x00003cbe mov edi, 1 ; int fd
| `------> 0x00003cbe mov edi, 0x01 ; int fd
| | | 0x00003cc3 call sym.imp.isatty ; int isatty(int fd)
| | | 0x00003cc8 test eax, eax
| ,======< 0x00003cca je 0x4c2e
| | | | 0x00003cd0 mov dword [rip + 0x1d626], 2 ; data.00021300
| ,======< 0x00003cca jz 0x4c2e
| | | | 0x00003cd0 mov dword [rip+0x1d626], 0x02 ; data.00021300
| | | | ; [0x21300:4]=0
| | | | 0x00003cda mov byte [rip + 0x1d33f], 1 ; data.00021020
| | | | 0x00003cda mov byte [rip+0x1d33f], 0x01 ; data.00021020
| | | | ; [0x21020:1]=0
| ========< 0x00003ce1 jmp 0x3cf9
| | | | ; CODE XREF from main @ 0x3cb2
| | `----> 0x00003ce3 mov esi, 5 ; int64_t arg2
| | `----> 0x00003ce3 mov esi, 0x05 ; int64_t arg2
| | | 0x00003ce8 xor edi, edi ; int64_t arg1
| | | 0x00003cea mov dword [rip + 0x1d60c], 0 ; data.00021300
| | | 0x00003cea mov dword [rip+0x1d60c], 0x00 ; data.00021300
| | | ; [0x21300:4]=0
| | | 0x00003cf4 call fcn.00012740
| | | ; CODE XREFS from main @ 0x3ce1, 0x4602, 0x4c38
| --------> 0x00003cf9 lea rdi, [rip + 0x14fb4] ; str.QUOTING_STYLE
| --------> 0x00003cf9 lea rdi, qword [rip+0x14fb4] ; str.QUOTING_STYLE
| | | ; 0x18cb4 ; "QUOTING_STYLE" ; const char *name
EOF
RUN
@ -1151,18 +1151,18 @@ EXPECT=<<EOF
| 0x00012740 push rbp
| 0x00012741 mov rbp, rsp
| 0x00012744 sub rsp, 0x1030
| 0x0001274b or qword [rsp], 0
| 0x0001274b or qword [rsp], 0x00
| 0x00012750 add rsp, 0x1020
| 0x00012757 mov rax, qword fs:[0x28]
| 0x00012760 mov qword [var_10h], rax
| 0x00012764 xor eax, eax
| 0x00012766 lea rax, [rip + 0xf033]
| 0x00012766 lea rax, qword [rip+0xf033]
| 0x0001276d test rdi, rdi
| 0x00012770 cmovne rax, rdi
| 0x00012770 cmovnz rax, rdi
| 0x00012774 mov dword [rax], esi
| 0x00012776 mov rax, qword [var_10h]
| 0x0001277a xor rax, qword fs:[0x28]
| ,==< 0x00012783 jne 0x12787
| ,==< 0x00012783 jnz 0x12787
| | 0x00012785 leave
| | 0x00012786 ret
\ `--> 0x00012787 call sym.imp.__stack_chk_fail
@ -1185,7 +1185,7 @@ EXPECT=<<EOF
╎ ; CALL XREF from main @ 0x400406
┌ int sym.imp.puts(const char *s);
└ ╎ 0x004003f0 jmp qword [reloc.puts] ; [0x601018:8]=0x4003f6
╎ 0x004003f6 push 0
╎ 0x004003f6 push 0x00
└─< 0x004003fb jmp sym..plt
EOF
RUN
@ -1209,8 +1209,8 @@ pdr~0x100003b44
pdr~0x100003b46
EOF
EXPECT=<<EOF
0x100003b27 -104 add rsi, 0xc
0x100003b27 -104 add rsi, 0xc
0x100003b27 -104 add rsi, 0x0c
0x100003b27 -104 add rsi, 0x0c
0x100003b3d -48 += 8 pop rbx
0x100003b3e -40 += 8 pop r12
0x100003b40 -32 += 8 pop r13
@ -1238,7 +1238,7 @@ pd 1
EOF
EXPECT=<<EOF
; [0x1048:8]=0x500 "Hello"
0x00000000 mov rsi, qword [rip + 0x1041]
0x00000000 mov rsi, qword [rip+0x1041]
EOF
RUN
@ -1260,7 +1260,7 @@ pd 1
EOF
EXPECT=<<EOF
; [0x1048:8]=0x500 "Hello"
0x00000000 mov rsi, qword [rip + 0x1041]
0x00000000 mov rsi, qword [rip+0x1041]
EOF
RUN
@ -1299,10 +1299,10 @@ EXPECT=<<EOF
| ; var DWORD dwFlagsAndAttributes @ stack - 0x20
| ; var HANDLE hTemplateFile @ stack - 0x18
| 0x14000b54c 4883ec48 sub rsp, 0x48
| 0x14000b550 488364243000 and qword [hTemplateFile], 0 ; HANDLE hTemplateFile
| 0x14000b556 488d0da37300. lea rcx, str.CONOUT ; 0x140012900 ; u"CONOUT$" ; LPCWSTR lpFileName
| 0x14000b55d 8364242800 and dword [dwFlagsAndAttributes], 0 ; DWORD dwFlagsAndAttributes
| 0x14000b562 41b803000000 mov r8d, 3 ; DWORD dwShareMode
| 0x14000b550 488364243000 and qword [hTemplateFile], 0x00 ; HANDLE hTemplateFile
| 0x14000b556 488d0da37300. lea rcx, qword str.CONOUT ; 0x140012900 ; u"CONOUT$" ; LPCWSTR lpFileName
| 0x14000b55d 8364242800 and dword [dwFlagsAndAttributes], 0x00 ; DWORD dwFlagsAndAttributes
| 0x14000b562 41b803000000 mov r8d, 0x03 ; DWORD dwShareMode
| 0x14000b568 4533c9 xor r9d, r9d ; LPSECURITY_ATTRIBUTES lpSecurityAttributes
| 0x14000b56b 4489442420 mov dword [dwCreationDisposition], r8d ; DWORD dwCreationDisposition
| 0x14000b570 ba00000040 mov edx, 0x40000000 ; DWORD dwDesiredAccess
@ -1564,7 +1564,7 @@ fastcall
| 0x0804844e 83c410 add esp, 0x10
| 0x08048451 90 nop
| 0x08048452 c9 leave
\ 0x08048453 c20800 ret 8
\ 0x08048453 c20800 ret 0x08
EOF
RUN
@ -1919,7 +1919,7 @@ e asm.sub.rel=true
axt @ sym.imp.msvcrt.dll_printf
EOF
EXPECT=<<EOF
entry0 0xffffffffffff100a [CALL] call qword [rip + 0xd8]
entry0 0xffffffffffff100a [CALL] call qword [rip+0xd8]
entry0 0xffffffffffff100a [CALL] call qword [sym.imp.msvcrt.dll_printf]
EOF
RUN
@ -2454,25 +2454,25 @@ EXPECT=<<EOF
},
"sign": false,
"prefix": 0,
"id": 612,
"id": 668,
"opex": {
"operands": [
{
"size": 8,
"rw": 1,
"type": "reg",
"value": "rflags"
"value": "eflags"
}
]
},
"addr": 0,
"bytes": "669c",
"size": 2,
"type": "upush",
"type": "rpush",
"esilcost": 24,
"scale": 0,
"refptr": 0,
"cycles": 2,
"cycles": 1,
"failcycles": 0,
"delay": 0,
"stack": "inc",
@ -2498,13 +2498,13 @@ axt @ 0x00001df4
axt @ 0x00001e09
EOF
EXPECT=<<EOF
main 0x1457 [STRING] lea eax, str.Take_the_Red_Pill
main 0x148e [STRING] lea eax, str.use:_._exploit1_PILL
main 0x14eb [STRING] lea eax, str.Red_Pill__0x50444552
main 0x1502 [STRING] lea eax, str.Your_Pill_0x_08x
main 0x1523 [STRING] lea eax, str.Red_Pill
main 0x1557 [STRING] lea eax, str.fwhibbit
main 0x161d [STRING] lea eax, str.Blue_Pill
main 0x1457 [STRING] lea eax, dword str.Take_the_Red_Pill
main 0x148e [STRING] lea eax, dword str.use:_._exploit1_PILL
main 0x14eb [STRING] lea eax, dword str.Red_Pill__0x50444552
main 0x1502 [STRING] lea eax, dword str.Your_Pill_0x_08x
main 0x1523 [STRING] lea eax, dword str.Red_Pill
main 0x1557 [STRING] lea eax, dword str.fwhibbit
main 0x161d [STRING] lea eax, dword str.Blue_Pill
EOF
RUN
@ -2548,7 +2548,7 @@ aae
axt @ 0x80484e0
EOF
EXPECT=<<EOF
main 0x8048432 [STRING] lea eax, str.Hello_PIC
main 0x8048432 [STRING] lea eax, dword str.Hello_PIC
EOF
RUN
@ -2568,13 +2568,13 @@ axt @ 0x00001df4
axt @ 0x00001e09
EOF
EXPECT=<<EOF
main 0x1457 [STRING] lea eax, [esi - 0x2277]
main 0x148e [STRING] lea eax, [esi - 0x2260]
main 0x14eb [STRING] lea eax, [esi - 0x2249]
main 0x1502 [STRING] lea eax, [esi - 0x222f]
main 0x1523 [STRING] lea eax, [esi - 0x2218]
main 0x1557 [STRING] lea eax, [esi - 0x220c]
main 0x161d [STRING] lea eax, [esi - 0x21f7]
main 0x1457 [STRING] lea eax, dword [esi-0x2277]
main 0x148e [STRING] lea eax, dword [esi-0x2260]
main 0x14eb [STRING] lea eax, dword [esi-0x2249]
main 0x1502 [STRING] lea eax, dword [esi-0x222f]
main 0x1523 [STRING] lea eax, dword [esi-0x2218]
main 0x1557 [STRING] lea eax, dword [esi-0x220c]
main 0x161d [STRING] lea eax, dword [esi-0x21f7]
EOF
RUN
@ -2588,7 +2588,7 @@ aae
axt @ 0x80484e0
EOF
EXPECT=<<EOF
main 0x8048432 [STRING] lea eax, [ebx - 0x1b20]
main 0x8048432 [STRING] lea eax, dword [ebx-0x1b20]
EOF
RUN
@ -2602,7 +2602,7 @@ aae
pd 1 @ 0x08048432
EOF
EXPECT=<<EOF
| 0x08048432 8d83e0e4ffff lea eax, str.Hello_PIC ; 0x80484e0 ; "Hello PIC!"
| 0x08048432 8d83e0e4ffff lea eax, dword str.Hello_PIC ; 0x80484e0 ; "Hello PIC!"
EOF
RUN
@ -2618,7 +2618,7 @@ aae
pd 1 @ 0x08048432
EOF
EXPECT=<<EOF
| 0x08048432 lea eax, str.Hello_PIC
| 0x08048432 lea eax, dword str.Hello_PIC
EOF
RUN
@ -2648,9 +2648,9 @@ EOF
EXPECT=<<EOF
; DATA XREF from entry0 @ +0xf
;-- __libc_csu_fini:
0x00400730 f3c3 repz ret
0x00400730 f3c3 ret
; CODE XREF from sym.__do_global_ctors_aux @ +0x2d
0x004007f0 4883eb08 sub rbx, 8
0x004007f0 4883eb08 sub rbx, 0x08
; CALL XREF from section..fini @ +0x4
;-- __do_global_dtors_aux:
0x00400610 55 push rbp
@ -2673,9 +2673,9 @@ EOF
EXPECT=<<EOF
; DATA XREF from entry0 @ 0x4005cf
sym.__libc_csu_fini();
0x00400730 f3c3 repz ret
0x00400730 f3c3 ret
; CODE XREF from sym.__do_global_ctors_aux @ 0x4007fd
0x004007f0 4883eb08 sub rbx, 8
0x004007f0 4883eb08 sub rbx, 0x08
; CALL XREF from sym._fini @ 0x40080c
sym.__do_global_dtors_aux();
0x00400610 55 push rbp
@ -2789,7 +2789,7 @@ is-pure: true
realsz: 7
stackframe: 0
call-convention: amd64
cyclomatic-cost: 4
cyclomatic-cost: 2
cyclomatic-complexity: 0
loops: 0
bits: 64
@ -2817,7 +2817,7 @@ args: 0
/ fcn.00000000();
| 0x00000000 b8210000c1 mov eax, 0xc1000021 ; '!'
\ `=< 0x00000005 ebfd jmp 4
\ `=< 0x00000005 ebfd jmp 0x4
EOF
RUN
@ -2870,7 +2870,7 @@ args: 0
/ fcn.00000000();
| 0x00000000 b8210000c1 mov eax, 0xc1000021 ; '!'
| 0x00000005 ebfd jmp 4
| 0x00000005 ebfd jmp 0x4
| ----------- true: 0x00000004
| ; CODE XREF from fcn.00000000 @ 0x5
| 0x00000004 c1ebfd shr ebx, 0xfd
@ -2883,7 +2883,7 @@ args: 0
| fcn.00000000(); |
| ; '!' |
| mov eax, 0xc1000021 |
| jmp 4 |
| jmp 0x4 |
`---------------------'
v
|
@ -2907,7 +2907,7 @@ args: 0
/ fcn.00000000();
| 0x00000000 b8210000c1 mov eax, 0xc1000021 ; '!'
| `=< 0x00000005 ebfd jmp 4
| `=< 0x00000005 ebfd jmp 0x4
| 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ 0x0000000c cc int3
@ -2941,12 +2941,12 @@ args: 0
/ fcn.00000000();
| 0x00000000 b8210000c1 mov eax, 0xc1000021 ; '!'
| 0x00000005 ebfd jmp 4
| 0x00000005 ebfd jmp 0x4
| ----------- true: 0x00000004
| ; CODE XREFS from fcn.00000000 @ 0x5, 0xc
| 0x00000004 c1ebfd shr ebx, 0xfd
| 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ 0x0000000c ebf6 jmp 4
\ 0x0000000c ebf6 jmp 0x4
| ----------- true: 0x00000004
.---------------------.
@ -2954,7 +2954,7 @@ args: 0
| fcn.00000000(); |
| ; '!' |
| mov eax, 0xc1000021 |
| jmp 4 |
| jmp 0x4 |
`---------------------'
v
|
@ -2971,7 +2971,7 @@ args: 0
|| shr ebx, 0xfd |
|| ; ',' |
|| mov ebx, 0x2c |
|| jmp 4 |
|| jmp 0x4 |
|`-------------------------------------------'
| v
| |
@ -2982,13 +2982,13 @@ args: 0
| ; CODE XREFS from fcn.00000000 @ 0x5, 0xc
| ..-> 0x00000004 c1ebfd shr ebx, 0xfd
| : 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ `=< 0x0000000c ebf6 jmp 4
\ `=< 0x0000000c ebf6 jmp 0x4
/ fcn.00000000();
| 0x00000000 b8210000c1 mov eax, 0xc1000021 ; '!'
| `==< 0x00000005 ebfd jmp 4
| `==< 0x00000005 ebfd jmp 0x4
| : 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ `=< 0x0000000c ebf6 jmp 4
\ `=< 0x0000000c ebf6 jmp 0x4
offset: 0x00000000
name: fcn.00000000
@ -3025,10 +3025,10 @@ args: 0
| ; CODE XREF from fcn.00000000 @ 0x5
| 0x00000004 c1ebfd shr ebx, 0xfd
| 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ 0x0000000c ebf7 jmp 5
\ 0x0000000c ebf7 jmp 0x5
| ----------- true: 0x00000005
| ; CODE XREF from fcn.00000000 @ 0xc
| 0x00000005 ebfd jmp 4
| 0x00000005 ebfd jmp 0x4
| ----------- true: 0x00000004
.---------------------.
@ -3045,7 +3045,7 @@ args: 0
|.-------------------------------------.
|| 0x5 |
|| ; CODE XREF from fcn.00000000 @ 0xc |
|| jmp 4 |
|| jmp 0x4 |
|`-------------------------------------'
| v
| |
@ -3056,7 +3056,7 @@ args: 0
|| shr ebx, 0xfd |
|| ; ',' |
|| mov ebx, 0x2c |
|| jmp 5 |
|| jmp 0x5 |
|`-------------------------------------'
| v
| |
@ -3067,16 +3067,16 @@ args: 0
| ; CODE XREF from fcn.00000000 @ 0x5
| .-> 0x00000004 ~ c1ebfd shr ebx, 0xfd
| | ; CODE XREF from fcn.00000000 @ 0xc
| .`=< 0x00000005 ebfd jmp 4
| .`=< 0x00000005 ebfd jmp 0x4
| : 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ `==< 0x0000000c ebf7 jmp 5
\ `==< 0x0000000c ebf7 jmp 0x5
/ fcn.00000000();
| 0x00000000 b8210000c1 mov eax, 0xc1000021 ; '!'
| | ; CODE XREF from fcn.00000000 @ 0xc
| .`=< 0x00000005 ebfd jmp 4
| .`=< 0x00000005 ebfd jmp 0x4
| : 0x00000007 bb2c000000 mov ebx, 0x2c ; ','
\ `==< 0x0000000c ebf7 jmp 5
\ `==< 0x0000000c ebf7 jmp 0x5
offset: 0x00000000
name: fcn.00000000
@ -3109,35 +3109,35 @@ args: 0
0x00000009 0x00000013 00:0000 10 j 0x00000003
/ fcn.00000000();
| 0x00000000 0f1f440000 nop dword [rax + rax]
| 0x00000000 0f1f440000 nop dword [rax+rax*1], eax
| ----------- true: 0x00000005
| ; CODE XREF from fcn.00000000 @ 0x11
| 0x00000003 0000 add byte [rax], al
| ----------- true: 0x00000005
| 0x00000005 b8210000c1 mov eax, 0xc1000021 ; '!'
| 0x0000000a ebfd jmp 9
| 0x0000000a ebfd jmp 0x9
| ----------- true: 0x00000009
| ; CODE XREF from fcn.00000000 @ 0xa
| 0x00000009 c1ebfd shr ebx, 0xfd
| 0x0000000c bb2c000000 mov ebx, 0x2c ; ','
\ 0x00000011 ebf0 jmp 3
\ 0x00000011 ebf0 jmp 0x3
| ----------- true: 0x00000003
.-----------------------.
| 0x0 |
| fcn.00000000(); |
| nop dword [rax + rax] |
`-----------------------'
v
|
'--.
.----------------------------.
| 0x0 |
| fcn.00000000(); |
| nop dword [rax+rax*1], eax |
`----------------------------'
v
|
'-----.
.-----------------.
| | |
| .---------------------.
| | 0x5 |
| | ; '!' |
| | mov eax, 0xc1000021 |
| | jmp 9 |
| | jmp 0x9 |
| `---------------------'
| v
| |
@ -3149,7 +3149,7 @@ args: 0
| | shr ebx, 0xfd |
| | ; ',' |
| | mov ebx, 0x2c |
| | jmp 3 |
| | jmp 0x3 |
| `-------------------------------------'
| v
| |
@ -3165,21 +3165,21 @@ args: 0
`----'
/ fcn.00000000();
| 0x00000000 ~ 0f1f440000 nop dword [rax + rax]
| 0x00000000 ~ 0f1f440000 nop dword [rax+rax*1], eax
| ; CODE XREF from fcn.00000000 @ 0x11
| .-> 0x00000003 0000 add byte [rax], al
| : 0x00000005 ~ b8210000c1 mov eax, 0xc1000021 ; '!'
| : ; CODE XREF from fcn.00000000 @ 0xa
| .--> 0x00000009 c1ebfd shr ebx, 0xfd
| : 0x0000000c bb2c000000 mov ebx, 0x2c ; ','
\ `=< 0x00000011 ebf0 jmp 3
\ `=< 0x00000011 ebf0 jmp 0x3
/ fcn.00000000();
| 0x00000000 0f1f440000 nop dword [rax + rax]
| 0x00000000 0f1f440000 nop dword [rax+rax*1], eax
| : 0x00000005 b8210000c1 mov eax, 0xc1000021 ; '!'
| `==< 0x0000000a ebfd jmp 9
| `==< 0x0000000a ebfd jmp 0x9
| : 0x0000000c bb2c000000 mov ebx, 0x2c ; ','
\ `=< 0x00000011 ebf0 jmp 3
\ `=< 0x00000011 ebf0 jmp 0x3
EOF
RUN
@ -3236,7 +3236,7 @@ args: 0
/ fcn.00000003();
| 0x00000003 0010 add byte [rax], dl
| ----------- true: 0x00000005
| 0x00000005 ebf9 jmp 0
| 0x00000005 ebf9 jmp 0x0
| ----------- true: 0x00000000
.----.
@ -3254,7 +3254,7 @@ args: 0
| | |
| .-----------.
| | 0x5 |
| | jmp 0 |
| | jmp 0x0 |
| `-----------'
| v
| |
@ -3262,18 +3262,18 @@ args: 0
/ fcn.00000003();
| 0x00000003 0010 add byte [rax], dl
| 0x00000005 ebf9 jmp 0
| 0x00000005 ebf9 jmp 0x0
| ; CODE XREF from fcn.00000003 @ 0x5
| ;-- (0x00000003) fcn.00000003:
| 0x00000000 ~ b821c10010 mov eax, 0x1000c121
| 0x00000005 ebf9 jmp 0
| 0x00000005 ebf9 jmp 0x0
| ; CODE XREF from fcn.00000003 @ 0x5
| 0x00000000 ~ b821c10010 mov eax, 0x1000c121
/ fcn.00000003();
| 0x00000003 0010 add byte [rax], dl
| 0x00000005 ebf9 jmp 0
| 0x00000005 ebf9 jmp 0x0
EOF
RUN
@ -3302,7 +3302,7 @@ EXPECT=<<EOF
/ fcn.00000003();
| 0x00000003 0010 add byte [rax], dl
| ----------- true: 0x00000005
| 0x00000005 ebf9 jmp 0
| 0x00000005 ebf9 jmp 0x0
| ----------- true: 0x00000000
.----.
@ -3320,7 +3320,7 @@ EXPECT=<<EOF
| | |
| .-----------.
| | 0x5 |
| | jmp 0 |
| | jmp 0x0 |
| `-----------'
| v
| |
@ -3372,7 +3372,7 @@ mnemonic: push
description: push word, doubleword or quadword onto the stack
mask: ff
prefix: 0
id: 609
id: 665
bytes: 55
refptr: 0
size: 1
@ -3516,19 +3516,19 @@ af
pif
EOF
EXPECT=<<EOF
lea rdi, loc._edata
lea rax, [0x0021d28f]
lea rdi, qword loc._edata
lea rax, qword [0x0021d28f]
push rbp
sub rax, rdi
mov rbp, rsp
cmp rax, 0xe
cmp rax, 0x0e
jbe 0x5c80
mov rax, qword [reloc._ITM_deregisterTMCloneTable]
test rax, rax
je 0x5c80
jz 0x5c80
pop rbp
jmp rax
nop word [rax + rax]
nop word [rax+rax*1], ax
pop rbp
ret
EOF
@ -3800,32 +3800,32 @@ e asm.lines=false
pdf~case
EOF
EXPECT=<<EOF
0x140001012 0f871a010000 ja case.0x140001034.3
0x140001012 0f871a010000 jnbe case.0x140001034.3
0x140001034 ffe1 jmp rcx ; switch table (99 cases) at 0x140001148
;-- case 1: ; from 0x140001034
0x140001036 488d0dd31100. lea rcx, str.case_1 ; 0x140002210 ; "case 1"
0x140001036 488d0dd31100. lea rcx, qword str.case_1 ; 0x140002210 ; "case 1"
;-- case 2: ; from 0x140001034
0x14000104b 488d0dc61100. lea rcx, str.case_2 ; 0x140002218 ; "case 2"
0x14000104b 488d0dc61100. lea rcx, qword str.case_2 ; 0x140002218 ; "case 2"
;-- case 11: ; from 0x140001034
0x140001060 488d0db91100. lea rcx, str.case_11 ; 0x140002220 ; "case 11"
0x140001060 488d0db91100. lea rcx, qword str.case_11 ; 0x140002220 ; "case 11"
;-- case 13: ; from 0x140001034
0x140001075 488d0dac1100. lea rcx, str.case_13 ; 0x140002228 ; "case 13"
0x140001075 488d0dac1100. lea rcx, qword str.case_13 ; 0x140002228 ; "case 13"
;-- case 15...16: ; from 0x140001034
0x14000108a 488d0d9f1100. lea rcx, str.case_15_and_16 ; 0x140002230 ; "case 15 and 16"
0x14000108a 488d0d9f1100. lea rcx, qword str.case_15_and_16 ; 0x140002230 ; "case 15 and 16"
;-- case 19: ; from 0x140001034
0x14000109f 488d0d9a1100. lea rcx, str.case_19 ; 0x140002240 ; "case 19"
0x14000109f 488d0d9a1100. lea rcx, qword str.case_19 ; 0x140002240 ; "case 19"
;-- case 50: ; from 0x140001034
0x1400010b4 488d0d8d1100. lea rcx, str.case_50 ; 0x140002248 ; "case 50"
0x1400010b4 488d0d8d1100. lea rcx, qword str.case_50 ; 0x140002248 ; "case 50"
;-- case 30: ; from 0x140001034
0x1400010c9 488d0d801100. lea rcx, str.case_30 ; 0x140002250 ; "case 30"
0x1400010c9 488d0d801100. lea rcx, qword str.case_30 ; 0x140002250 ; "case 30"
;-- case 20: ; from 0x140001034
0x1400010de 488d0d731100. lea rcx, str.case_20 ; 0x140002258 ; "case 20"
0x1400010de 488d0d731100. lea rcx, qword str.case_20 ; 0x140002258 ; "case 20"
;-- case 10: ; from 0x140001034
0x1400010f3 488d0d661100. lea rcx, str.case_10 ; 0x140002260 ; "case 10"
0x1400010f3 488d0d661100. lea rcx, qword str.case_10 ; 0x140002260 ; "case 10"
;-- case 99: ; from 0x140001034
0x140001108 488d0d591100. lea rcx, str.case_99 ; 0x140002268 ; "case 99"
0x140001108 488d0d591100. lea rcx, qword str.case_99 ; 0x140002268 ; "case 99"
;-- case 97: ; from 0x140001034
0x14000111d 488d0d4c1100. lea rcx, str.case_97 ; 0x140002270 ; "case 97"
0x14000111d 488d0d4c1100. lea rcx, qword str.case_97 ; 0x140002270 ; "case 97"
;-- case 3...9: ; from 0x140001034
;-- case 12: ; from 0x140001034
;-- case 14: ; from 0x140001034
@ -4013,7 +4013,7 @@ EXPECT=<<EOF
| 0x140001096 57 push rdi
| 0x140001097 4883ec30 sub rsp, 0x30
| 0x14000109b 488bf9 mov rdi, rcx
| 0x14000109e 488d742458 lea rsi, [var_10h]
| 0x14000109e 488d742458 lea rsi, qword [var_10h]
| 0x1400010a3 33c9 xor ecx, ecx
| 0x1400010a5 ff15cd100000 call qword [sym.imp.api_ms_win_crt_stdio_l1_1_0.dll___acrt_iob_func]
| 0x1400010ab 488bd8 mov rbx, rax
@ -4096,23 +4096,23 @@ EXPECT=<<EOF
| ; arg int64_t arg_4h @ stack + 0x4
| 0x00000000 54 push rsp
| 0x00000001 4889e5 mov rbp, rsp
| 0x00000004 b402 mov ah, 2
| 0x00000004 b402 mov ah, 0x02
| 0x00000006 66b83333 mov ax, 0x3333
| 0x0000000a b855554444 mov eax, 0x44445555
| 0x0000000f 48b8bebafeca. movabs rax, 0xdeadbeefcafebabe
| 0x0000000f 48b8bebafeca. mov rax, 0xdeadbeefcafebabe
| 0x00000019 4889d8 mov rax, rbx
| 0x0000001c 488d03 lea rax, [rbx]
| 0x0000001f 488b4308 mov rax, qword [rbx + 8]
| 0x00000023 488d4308 lea rax, [rbx + 8]
| 0x00000027 488d041b lea rax, [rbx + rbx]
| 0x0000002b 488d441b0a lea rax, [rbx + rbx + 0xa]
| 0x00000030 488d430a lea rax, [rbx + 0xa]
| 0x00000034 488d44240c lea rax, [arg_4h]
| 0x00000039 488d450b lea rax, [arg_3h]
| 0x0000003d 488d45f5 lea rax, [var_13h]
| 0x00000041 488d442404 lea rax, [var_4h]
| 0x00000046 488d4508 lea rax, [var_4h + 0x4]
| 0x0000004a 488d45f8 lea rax, [var_10h]
| 0x0000001c 488d03 lea rax, qword [rbx]
| 0x0000001f 488b4308 mov rax, qword [rbx+0x08]
| 0x00000023 488d4308 lea rax, qword [rbx+0x08]
| 0x00000027 488d041b lea rax, qword [rbx+rbx*1]
| 0x0000002b 488d441b0a lea rax, qword [rbx+rbx*1+0x0a]
| 0x00000030 488d430a lea rax, qword [rbx+0x0a]
| 0x00000034 488d44240c lea rax, qword [arg_4h]
| 0x00000039 488d450b lea rax, qword [arg_3h]
| 0x0000003d 488d45f5 lea rax, qword [var_13h]
| 0x00000041 488d442404 lea rax, qword [var_4h]
| 0x00000046 488d4508 lea rax, qword [var_4h + 0x4]
| 0x0000004a 488d45f8 lea rax, qword [var_10h]
EOF
RUN
@ -4137,23 +4137,23 @@ EXPECT=<<EOF
| ; arg int64_t arg_4h @ stack + 0x4
| 0x00000000 54 push rsp
| 0x00000001 4889e5 rbp = rsp
| 0x00000004 b402 ah = 2
| 0x00000004 b402 ah = 0x02
| 0x00000006 66b83333 ax = 0x3333
| 0x0000000a b855554444 eax = 0x44445555
| 0x0000000f 48b8bebafeca. rax = 0xdeadbeefcafebabe
| 0x00000019 4889d8 rax = rbx
| 0x0000001c 488d03 rax = rbx
| 0x0000001f 488b4308 rax = qword [rbx + 8]
| 0x00000023 488d4308 rax = rbx + 8
| 0x00000027 488d041b rax = rbx + rbx
| 0x0000002b 488d441b0a rax = rbx + rbx + 0xa
| 0x00000030 488d430a rax = rbx + 0xa
| 0x00000034 488d44240c rax = arg_4h
| 0x00000039 488d450b rax = arg_3h
| 0x0000003d 488d45f5 rax = var_13h
| 0x00000041 488d442404 rax = var_4h
| 0x00000046 488d4508 rax = var_4h + 0x4
| 0x0000004a 488d45f8 rax = var_10h
| 0x0000001c 488d03 rax = qword rbx
| 0x0000001f 488b4308 rax = qword [rbx+0x08]
| 0x00000023 488d4308 rax = qword rbx+0x08
| 0x00000027 488d041b rax = qword rbx+rbx*1
| 0x0000002b 488d441b0a rax = qword rbx+rbx*1+0x0a
| 0x00000030 488d430a rax = qword rbx+0x0a
| 0x00000034 488d44240c rax = qword arg_4h
| 0x00000039 488d450b rax = qword arg_3h
| 0x0000003d 488d45f5 rax = qword var_13h
| 0x00000041 488d442404 rax = qword var_4h
| 0x00000046 488d4508 rax = qword var_4h + 0x4
| 0x0000004a 488d45f8 rax = qword var_10h
EOF
RUN

4
test/db/archos/darwin-x64/dbg
View file

@ -28,9 +28,9 @@ mov rbp, rsp
sub rsp, 0x10
mov rax, qword [section.13.__DATA.__objc_classrefs]
mov rdi, rax
lea rax, reloc.objc_msgSend_fixup
lea rax, qword reloc.objc_msgSend_fixup
mov rax, qword [rax]
lea rsi, reloc.objc_msgSend_fixup
lea rsi, qword reloc.objc_msgSend_fixup
EOF
EXPECT_ERR=<<EOF
hit breakpoint at: 0x100000bf8

10
test/db/archos/linux-x64/dbg_bps
View file

@ -275,12 +275,12 @@ EXPECT=<<EOF
push rbp
mov rbp, rsp
sub rsp, 0x20
mov dword [rbp - 0x14], edi
mov qword [rbp - 0x20], rsi
mov dword [rbp-0x14], edi
mov qword [rbp-0x20], rsi
b sub rsp, 0x20
mov dword [rbp - 0x14], edi
mov qword [rbp - 0x20], rsi
mov dword [rbp - 4], 0
mov dword [rbp-0x14], edi
mov qword [rbp-0x20], rsi
mov dword [rbp-0x04], 0x00
jmp 0x400523
EOF
RUN

4
test/db/archos/linux-x64/dbg_de
View file

@ -27,7 +27,7 @@ s rip-7
pi 2
EOF
EXPECT=<<EOF
lea rax, str.Hello
mov qword [rbp - 0x18], rax
lea rax, qword str.Hello
mov qword [rbp-0x18], rax
EOF
RUN

14
test/db/archos/linux-x64/dbg_step
View file

@ -190,20 +190,20 @@ dr rip
EOF
EXPECT=<<EOF
0x00400575 7 call qword [0x600958]
0x0040052f 10 movabs rax, 0x40053c
0x0040052f 10 mov rax, 0x40053c
0x00400539 2 call rax
0x0040053c 10 movabs rax, 0x600968
0x0040053c 10 mov rax, 0x600968
0x00400546 2 call qword [rax]
0x00400549 5 call 0x40054f
0x0040054f 10 movabs rax, 0x40055b
0x0040054f 10 mov rax, 0x40055b
0x00400559 2 jmp rax
0x0040055b 10 movabs rax, 0x600980
0x0040055b 10 mov rax, 0x600980
0x00400565 2 jmp qword [rax]
0x00400567 7 jmp qword [0x600988]
0x0040056e 5 call 0x400510
0x00400510 10 movabs rdi, 0x600954
0x0040051a 10 movabs rsi, 0x600948
0x00400524 5 mov eax, 0
0x00400510 10 mov rdi, 0x600954
0x0040051a 10 mov rsi, 0x600948
0x00400524 5 mov eax, 0x00
rip = 0x0000000000400524
EOF
RUN

4
test/db/archos/linux-x64/dbg_step_back
View file

@ -16,7 +16,7 @@ EOF
EXPECT=<<EOF
rip = 0x00000000004028b6
rip = 0x00000000004028af
0x398
0x3c8
EOF
RUN
@ -43,7 +43,7 @@ rax = 0x0000000000600980
rip = 0x0000000000400510
rax = 0x0000000000600980
rip = 0x000000000040056e
0x8
0x30
EOF
RUN

22
test/db/archos/linux-x64/debuginfod
View file

@ -84,11 +84,11 @@ EXPECT=<<EOF
| 0x0000118f movsd qword [q], xmm0 ; arg7
| 0x00001194 mov qword [gg], rdx ; arg3
| 0x00001198 mov qword [out], rcx ; arg4
| 0x0000119c cmp qword [gg], 0 ; float_ex1.c:16
| ,=< 0x000011a1 je 0x11b2
| | 0x000011a7 cmp qword [out], 0
| ,==< 0x000011ac jne 0x11bb
| |`-> 0x000011b2 mov byte [a + 0x7], 0 ; float_ex1.c:17
| 0x0000119c cmp qword [gg], 0x00 ; float_ex1.c:16
| ,=< 0x000011a1 jz 0x11b2
| | 0x000011a7 cmp qword [out], 0x00
| ,==< 0x000011ac jnz 0x11bb
| |`-> 0x000011b2 mov byte [a + 0x7], 0x00 ; float_ex1.c:17
| |,=< 0x000011b6 jmp 0x121c
| `--> 0x000011bb mov edi, 0x18 ; float_ex1.c:19 ; size_t size
| | 0x000011c0 call sym.imp.malloc ; void *malloc(size_t size)
@ -101,23 +101,23 @@ EXPECT=<<EOF
| | 0x000011d9 mov dword [rax], ecx
| | 0x000011db mov rax, qword [out] ; float_ex1.c:21
| | 0x000011df mov rdi, qword [rax]
| | 0x000011e2 add rdi, 4 ; char *dest
| | 0x000011e2 add rdi, 0x04 ; char *dest
| | 0x000011e6 mov rsi, qword [g] ; const char *src
| | 0x000011ea mov edx, 5 ; size_t n
| | 0x000011ea mov edx, 0x05 ; size_t n
| | 0x000011ef call sym.imp.strncpy ; char *strncpy(char *dest, const char *src, size_t n)
| | 0x000011f4 movsd xmm0, qword [q] ; float_ex1.c:22
| | 0x000011f9 cvtsd2ss xmm0, xmm0
| | 0x000011fd mov rax, qword [out]
| | 0x00001201 mov rax, qword [rax]
| | 0x00001204 movss dword [rax + 0xc], xmm0
| | 0x00001204 movss dword [rax+0x0c], xmm0
| | 0x00001209 mov rcx, qword [gg] ; float_ex1.c:23
| | 0x0000120d mov rax, qword [out]
| | 0x00001211 mov rax, qword [rax]
| | 0x00001214 mov qword [rax + 0x10], rcx
| | 0x00001218 mov byte [a + 0x7], 1 ; float_ex1.c:24
| | 0x00001214 mov qword [rax+0x10], rcx
| | 0x00001218 mov byte [a + 0x7], 0x01 ; float_ex1.c:24
| | ; CODE XREF from dbg.fn1 @ 0x11b6
| `-> 0x0000121c mov al, byte [a + 0x7] ; float_ex1.c:25
| 0x0000121f and al, 1
| 0x0000121f and al, 0x01
| 0x00001221 movzx eax, al
| 0x00001224 add rsp, 0x30
| 0x00001228 pop rbp

13
test/db/asm/x86_16
View file

@ -1,12 +1,12 @@
ad "aaa" 37 0x0 (seq (branch (|| (! (ule (& (cast 8 false (var ax)) (bv 8 0xf)) (bv 8 0x9))) (var af)) (seq (set ax (+ (var ax) (bv 16 0x106))) (set af true) (set cf true)) (seq (set af false) (set cf false))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (& (cast 8 false (var ax)) (bv 8 0xf))))))
ad "aad 0xa" d50a 0x0 (seq (set temp_al (cast 8 false (var ax))) (set temp_ah (cast 8 false (>> (var ax) (bv 8 0x8) false))) (set adjusted (& (+ (var temp_al) (* (var temp_ah) (bv 8 0xa))) (bv 8 0xff))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (var adjusted)))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (bv 8 0x0)) (bv 8 0x8) false))) (set _result (var adjusted)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
ad "aad 0x0a" d50a 0x0 (seq (set temp_al (cast 8 false (var ax))) (set temp_ah (cast 8 false (>> (var ax) (bv 8 0x8) false))) (set adjusted (& (+ (var temp_al) (* (var temp_ah) (bv 8 0xa))) (bv 8 0xff))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (var adjusted)))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (bv 8 0x0)) (bv 8 0x8) false))) (set _result (var adjusted)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
ad "aad 0x42" d542 0x0 (seq (set temp_al (cast 8 false (var ax))) (set temp_ah (cast 8 false (>> (var ax) (bv 8 0x8) false))) (set adjusted (& (+ (var temp_al) (* (var temp_ah) (bv 8 0x42))) (bv 8 0xff))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (var adjusted)))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (bv 8 0x0)) (bv 8 0x8) false))) (set _result (var adjusted)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
ad "aam 0xa" d40a 0x0 (seq (set temp_al (cast 8 false (var ax))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (div (var temp_al) (bv 8 0xa))) (bv 8 0x8) false))) (set adjusted (mod (var temp_al) (bv 8 0xa))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (var adjusted)))) (set _result (var adjusted)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
ad "aam 0x0a" d40a 0x0 (seq (set temp_al (cast 8 false (var ax))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (div (var temp_al) (bv 8 0xa))) (bv 8 0x8) false))) (set adjusted (mod (var temp_al) (bv 8 0xa))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (var adjusted)))) (set _result (var adjusted)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
ad "aam 0x42" d442 0x0 (seq (set temp_al (cast 8 false (var ax))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (div (var temp_al) (bv 8 0x42))) (bv 8 0x8) false))) (set adjusted (mod (var temp_al) (bv 8 0x42))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (var adjusted)))) (set _result (var adjusted)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
ad "aas" 3f 0x0 (seq (branch (|| (! (ule (& (cast 8 false (var ax)) (bv 8 0xf)) (bv 8 0x9))) (var af)) (seq (set ax (- (var ax) (bv 16 0x6))) (set ax (| (& (var ax) (~ (bv 16 0xff00))) (<< (cast 16 false (- (cast 8 false (>> (var ax) (bv 8 0x8) false)) (bv 8 0x1))) (bv 8 0x8) false))) (set af true) (set cf true)) (seq (set af false) (set cf false))) (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (& (cast 8 false (var ax)) (bv 8 0xf))))))
adB "cbw" 98
d "call 0" e8fdff 0x0 (seq (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (bv 16 0x3))) (set sp (var final)) (jmp (bv 16 0x0)))
d "enter 8, 0" c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 16 0x8))) (set _nest_lvl (mod (cast 8 false (bv 16 0x0)) (bv 8 0x20))) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var bp))) (set sp (var final)) (set _frame_tmp (var sp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set bp (- (var bp) (bv 16 0x2))) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (loadw 0 16 (var bp)))) (set sp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var _frame_tmp))) (set sp (var final)))) (set sp (- (var sp) (cast 16 false (var _alloc_sz)))) (set bp (cast 16 false (cast 15 false (var _frame_tmp)))))
d "call 0x0" e8fdff 0x0 (seq (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (bv 16 0x3))) (set sp (var final)) (jmp (bv 16 0x0)))
d "enter 0x08, 0x00" c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 16 0x8))) (set _nest_lvl (mod (cast 8 false (bv 8 0x0)) (bv 8 0x20))) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var bp))) (set sp (var final)) (set _frame_tmp (var sp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set bp (- (var bp) (bv 16 0x2))) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (loadw 0 16 (var bp)))) (set sp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var _frame_tmp))) (set sp (var final)))) (set sp (- (var sp) (cast 16 false (var _alloc_sz)))) (set bp (cast 16 false (cast 15 false (var _frame_tmp)))))
a "jmp 0x0" ebfe 0x0 (jmp (cast 16 false (bv 16 0x0)))
a "jmp 0x10" eb0e 0x0 (jmp (cast 16 false (bv 16 0x10)))
a "jmp 0x34" eb32 0x0 (jmp (cast 16 false (bv 16 0x34)))
@ -18,15 +18,14 @@ dB "jmp 0xfec50" e95bec
dB "jmp 0xec50" e95bec 0x1ffff2 (jmp (cast 16 false (bv 16 0xec50)))
d "jmp 0xec50" e95bec 0xfff2 (jmp (cast 16 false (bv 16 0xec50)))
ad "leave" c9 0x0 (seq (set sp (var bp)) (set sp (+ (var sp) (bv 16 0x2))) (set bp (loadw 0 16 (+ (+ (cast 16 false (var sp)) (bv 16 0x0)) (<< (cast 16 false (var ss)) (bv 8 0x4) false)))))
ad "loop 0xffffff92" e290 0x0 (seq (set cx (- (var cx) (bv 16 0x1))) (branch (! (is_zero (var cx))) (jmp (bv 16 0xff94)) nop))
ad "loop 0xff92" e290 0x0 (seq (set cx (- (var cx) (bv 16 0x1))) (branch (! (is_zero (var cx))) (jmp (bv 16 0xff94)) nop))
a "mov al, [0xbeef]" a0efbe 0x0 (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (loadw 0 8 (bv 16 0xbeef)))))
a "mov ax, [0xbeef]" a1efbe 0x0 (set ax (loadw 0 16 (bv 16 0xbeef)))
d "popf" 9d 0x0 (seq (set _flags (loadw 0 16 (+ (+ (cast 16 false (var sp)) (bv 16 0x0)) (<< (cast 16 false (var ss)) (bv 8 0x4) false)))) (set cf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x2) false)) (set pf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x2) false)) (set af (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x2) false)) (set zf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set sf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set tf (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set if (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set df (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x1) false)) (set of (lsb (var _flags))) (set _flags (>> (var _flags) (bv 8 0x3) false)) (set nt (lsb (var _flags))) (set sp (+ (var sp) (bv 16 0x2))))
ad "push ax" 50 0x0 (seq (set final (- (var sp) (bv 16 0x4))) (storew 0 (var final) (cast 16 false (var ax))) (set sp (var final)))
d "pushf" 9c 0x0 (seq (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (| (<< (ite false (bv 16 0x1) (bv 16 0x0)) (bv 16 0x1) false) (ite (var nt) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x2) false) (bv 16 0x3)) (bv 16 0x1) false) (ite (var of) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x1) false) (ite (var df) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x1) false) (ite (var if) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x1) false) (ite (var tf) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x1) false) (ite (var zf) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x1) false) (ite (var zf) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x2) false) (ite (var af) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x2) false) (ite (var pf) (bv 16 0x1) (bv 16 0x0))) (bv 16 0x1) false) (bv 16 0x1)) (bv 16 0x1) false) (ite (var cf) (bv 16 0x1) (bv 16 0x0))))) (set sp (var final)))
d "pushaw" 60 0x0 (seq (set _sp (var sp)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var ax))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var cx))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var dx))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var bx))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var _sp))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var bp))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var si))) (set sp (var final)) (set final (- (var sp) (bv 16 0x2))) (storew 0 (var final) (cast 16 false (var di))) (set sp (var final)))
a "test bl, 0x12" f6c312 0x0 (seq (set _result (& (cast 8 false (var bx)) (bv 8 0x12))) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (set cf false) (set of false))
a "test bx, 0x1234" f7c33412 0x0 (seq (set _result (& (var bx) (bv 16 0x1234))) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (set cf false) (set of false))
aB "test byte [bx], 0x12" f60712
aB "test word [bx], 0x1234" f7073412
a "xlatb" d7 0x0 (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (loadw 0 8 (+ (+ (+ (var bx) (bv 16 0x0)) (<< (cast 16 false (var ds)) (bv 8 0x4) false)) (cast 16 false (cast 8 false (var ax))))))))
a "xlatb" d7 0x0 (set ax (| (& (var ax) (~ (bv 16 0xff))) (cast 16 false (loadw 0 8 (+ (+ (var bx) (bv 16 0x0)) (cast 16 false (cast 8 false (var ax))))))))

1176
test/db/asm/x86_32
View file

File diff suppressed because it is too large Load diff

77
test/db/asm/x86_64
View file

@ -1,7 +1,7 @@
a "lea rax, [0x1000]" 488d05f90f0000 0x0 (set rax (cast 64 false (+ (bv 64 0x7) (bv 64 0xff9))))
d "lea rax, [rip + 0xff9]" 488d05f90f0000 0x0 (set rax (cast 64 false (+ (bv 64 0x7) (bv 64 0xff9))))
d "lea rax, qword [rip+0xff9]" 488d05f90f0000 0x0 (set rax (cast 64 false (+ (bv 64 0x7) (bv 64 0xff9))))
ad "leave" c9 0x0 (seq (set rsp (var rbp)) (set rsp (+ (var rsp) (bv 64 0x8))) (set rbp (loadw 0 64 (+ (var rsp) (bv 64 0x0)))))
d "leave" 66c9 0x0 (seq (set rsp (var rbp)) (set rsp (+ (var rsp) (bv 64 0x4))) (set rbp (cast 64 false (loadw 0 32 (+ (var rsp) (bv 64 0x0))))))
d "leave" 66c9 0x0 (seq (set rsp (var rbp)) (set rsp (+ (var rsp) (bv 64 0x8))) (set rbp (loadw 0 64 (+ (var rsp) (bv 64 0x0)))))
ad "nop" 90 0x0 nop
ad "ret" c3 0x0 (seq (set tgt (loadw 0 64 (+ (var rsp) (bv 64 0x0)))) (set rsp (+ (var rsp) (bv 64 0x8))) (jmp (var tgt)))
a "add r13, r15" 4d01fd 0x0 (seq (set op1 (var r13)) (set op2 (var r15)) (set sum (+ (var op1) (var op2))) (set r13 (cast 64 false (var sum))) (set _result (var sum)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (set _result (var sum)) (set _x (var op1)) (set _y (var op2)) (set cf (|| (|| (&& (msb (var _x)) (msb (var _y))) (&& (! (msb (var _result))) (msb (var _y)))) (&& (msb (var _x)) (! (msb (var _result)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))))
@ -10,8 +10,8 @@ a "add rax, 44" 4883c02c 0x0 (seq (set op1 (var rax)) (set op2 (bv 64 0x2c)) (se
a "add rax, r8" 4c01c0 0x0 (seq (set op1 (var rax)) (set op2 (var r8)) (set sum (+ (var op1) (var op2))) (set rax (var sum)) (set _result (var sum)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (set _result (var sum)) (set _x (var op1)) (set _y (var op2)) (set cf (|| (|| (&& (msb (var _x)) (msb (var _y))) (&& (! (msb (var _result))) (msb (var _y)))) (&& (msb (var _x)) (! (msb (var _result)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))))
a "add r10, r9" 4d01ca 0x0 (seq (set op1 (var r10)) (set op2 (var r9)) (set sum (+ (var op1) (var op2))) (set r10 (cast 64 false (var sum))) (set _result (var sum)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (set _result (var sum)) (set _x (var op1)) (set _y (var op2)) (set cf (|| (|| (&& (msb (var _x)) (msb (var _y))) (&& (! (msb (var _result))) (msb (var _y)))) (&& (msb (var _x)) (! (msb (var _result)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))))
a "add rax, rcx" 4801c8 0x0 (seq (set op1 (var rax)) (set op2 (var rcx)) (set sum (+ (var op1) (var op2))) (set rax (var sum)) (set _result (var sum)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (set _result (var sum)) (set _x (var op1)) (set _y (var op2)) (set cf (|| (|| (&& (msb (var _x)) (msb (var _y))) (&& (! (msb (var _result))) (msb (var _y)))) (&& (msb (var _x)) (! (msb (var _result)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))))
ad "add r8, 3" 4983c003
ad "add r10, 4" 4983c204
ad "add r8, 0x03" 4983c003
ad "add r10, 0x04" 4983c204
aB "and dword [ebp + 128], eax" 48218580000000
a "call rbx" ffd3 0x0 (seq (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (bv 64 0x2))) (set rsp (var final)) (jmp (var rbx)))
a "cdqe" 4898 0x0 empty
@ -23,29 +23,19 @@ a "cmp rdx, rsi" 4839f2 0x0 (seq (set op1 (var rdx)) (set op2 (var rsi)) (set su
a "cmpsb" a6 0x0 (seq (set _src1 (loadw 0 8 (var rsi))) (set _src2 (loadw 0 8 (var rdi))) (set _temp (- (var _src1) (var _src2))) (set _result (var _temp)) (set _x (var _src1)) (set _y (var _src2)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x1))) (set rdi (- (var rdi) (bv 64 0x1)))) (seq (set rsi (+ (var rsi) (bv 64 0x1))) (set rdi (+ (var rdi) (bv 64 0x1))))))
a "cmpsd" a7 0x0 (seq (set _src1 (loadw 0 32 (var rsi))) (set _src2 (loadw 0 32 (var rdi))) (set _temp (- (var _src1) (var _src2))) (set _result (var _temp)) (set _x (var _src1)) (set _y (var _src2)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x4))) (set rdi (- (var rdi) (bv 64 0x4)))) (seq (set rsi (+ (var rsi) (bv 64 0x4))) (set rdi (+ (var rdi) (bv 64 0x4))))))
a "cmpsw" 66a7 0x0 (seq (set _src1 (loadw 0 16 (var rsi))) (set _src2 (loadw 0 16 (var rdi))) (set _temp (- (var _src1) (var _src2))) (set _result (var _temp)) (set _x (var _src1)) (set _y (var _src2)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x2))) (set rdi (- (var rdi) (bv 64 0x2)))) (seq (set rsi (+ (var rsi) (bv 64 0x2))) (set rdi (+ (var rdi) (bv 64 0x2))))))
d "cmpsd dword [esi], dword ptr [edi]" 67a7 0x0 (seq (set _src1 (loadw 0 32 (cast 64 false (cast 32 false (var rsi))))) (set _src2 (loadw 0 32 (cast 64 false (cast 32 false (var rdi))))) (set _temp (- (var _src1) (var _src2))) (set _result (var _temp)) (set _x (var _src1)) (set _y (var _src2)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (seq (set rsi (cast 64 false (- (cast 32 false (var rsi)) (bv 32 0x4)))) (set rdi (cast 64 false (- (cast 32 false (var rdi)) (bv 32 0x4))))) (seq (set rsi (cast 64 false (+ (cast 32 false (var rsi)) (bv 32 0x4)))) (set rdi (cast 64 false (+ (cast 32 false (var rdi)) (bv 32 0x4)))))))
d "cmpsq qword [rsi], qword ptr [rdi]" 48a7 0x0 (seq (set _src1 (loadw 0 64 (var rsi))) (set _src2 (loadw 0 64 (var rdi))) (set _temp (- (var _src1) (var _src2))) (set _result (var _temp)) (set _x (var _src1)) (set _y (var _src2)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x8))) (set rdi (- (var rdi) (bv 64 0x8)))) (seq (set rsi (+ (var rsi) (bv 64 0x8))) (set rdi (+ (var rdi) (bv 64 0x8))))))
a "lodsb" ac 0x0 (seq (set rax (| (& (var rax) (~ (bv 64 0xff))) (cast 64 false (loadw 0 8 (var rsi))))) (branch (var df) (set rsi (- (var rsi) (bv 64 0x1))) (set rsi (+ (var rsi) (bv 64 0x1)))))
a "lodsd" ad 0x0 (seq (set rax (cast 64 false (loadw 0 32 (var rsi)))) (branch (var df) (set rsi (- (var rsi) (bv 64 0x4))) (set rsi (+ (var rsi) (bv 64 0x4)))))
a "lodsw" 66ad 0x0 (seq (set rax (| (& (var rax) (~ (bv 64 0xffff))) (cast 64 false (loadw 0 16 (var rsi))))) (branch (var df) (set rsi (- (var rsi) (bv 64 0x2))) (set rsi (+ (var rsi) (bv 64 0x2)))))
d "lodsd eax, dword [esi]" 67ad 0x0 (seq (set rax (cast 64 false (loadw 0 32 (cast 64 false (cast 32 false (var rsi)))))) (branch (var df) (set rsi (cast 64 false (- (cast 32 false (var rsi)) (bv 32 0x4)))) (set rsi (cast 64 false (+ (cast 32 false (var rsi)) (bv 32 0x4))))))
d "lodsq rax, qword [rsi]" 48ad 0x0 (seq (set rax (loadw 0 64 (var rsi))) (branch (var df) (set rsi (- (var rsi) (bv 64 0x8))) (set rsi (+ (var rsi) (bv 64 0x8)))))
d "loop 0" 67e2fd 0x0 (seq (set rcx (cast 64 false (- (cast 32 false (var rcx)) (bv 32 0x1)))) (branch (! (is_zero (cast 32 false (var rcx)))) (jmp (bv 64 0x3)) nop))
d "loop 0x0" 67e2fd 0x0 (seq (set rcx (- (var rcx) (bv 64 0x1))) (branch (! (is_zero (var rcx))) (jmp (bv 64 0x3)) nop))
a "movsb" a4 0x0 (seq (storew 0 (var rdi) (loadw 0 8 (var rsi))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x1))) (set rdi (- (var rdi) (bv 64 0x1)))) (seq (set rsi (+ (var rsi) (bv 64 0x1))) (set rdi (+ (var rdi) (bv 64 0x1))))))
a "movsd" a5 0x0 (seq (storew 0 (var rdi) (loadw 0 32 (var rsi))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x4))) (set rdi (- (var rdi) (bv 64 0x4)))) (seq (set rsi (+ (var rsi) (bv 64 0x4))) (set rdi (+ (var rdi) (bv 64 0x4))))))
a "movsw" 66a5 0x0 (seq (storew 0 (var rdi) (loadw 0 16 (var rsi))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x2))) (set rdi (- (var rdi) (bv 64 0x2)))) (seq (set rsi (+ (var rsi) (bv 64 0x2))) (set rdi (+ (var rdi) (bv 64 0x2))))))
d "movsd dword [edi], dword ptr [esi]" 67a5 0x0 (seq (storew 0 (cast 64 false (cast 32 false (var rdi))) (loadw 0 32 (cast 64 false (cast 32 false (var rsi))))) (branch (var df) (seq (set rsi (cast 64 false (- (cast 32 false (var rsi)) (bv 32 0x4)))) (set rdi (cast 64 false (- (cast 32 false (var rdi)) (bv 32 0x4))))) (seq (set rsi (cast 64 false (+ (cast 32 false (var rsi)) (bv 32 0x4)))) (set rdi (cast 64 false (+ (cast 32 false (var rdi)) (bv 32 0x4)))))))
d "movsq qword [rdi], qword ptr [rsi]" 48a5 0x0 (seq (storew 0 (var rdi) (loadw 0 64 (var rsi))) (branch (var df) (seq (set rsi (- (var rsi) (bv 64 0x8))) (set rdi (- (var rdi) (bv 64 0x8)))) (seq (set rsi (+ (var rsi) (bv 64 0x8))) (set rdi (+ (var rdi) (bv 64 0x8))))))
a "stosb" aa 0x0 (seq (storew 0 (var rdi) (cast 8 false (var rax))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x1))) (set rdi (+ (var rdi) (bv 64 0x1)))))
a "stosd" ab 0x0 (seq (storew 0 (var rdi) (cast 32 false (var rax))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x4))) (set rdi (+ (var rdi) (bv 64 0x4)))))
a "stosw" 66ab 0x0 (seq (storew 0 (var rdi) (cast 16 false (var rax))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x2))) (set rdi (+ (var rdi) (bv 64 0x2)))))
d "stosd dword [edi], eax" 67ab 0x0 (seq (storew 0 (cast 64 false (cast 32 false (var rdi))) (cast 32 false (var rax))) (branch (var df) (set rdi (cast 64 false (- (cast 32 false (var rdi)) (bv 32 0x4)))) (set rdi (cast 64 false (+ (cast 32 false (var rdi)) (bv 32 0x4))))))
d "stosq qword [rdi], rax" 48ab 0x0 (seq (storew 0 (var rdi) (var rax)) (branch (var df) (set rdi (- (var rdi) (bv 64 0x8))) (set rdi (+ (var rdi) (bv 64 0x8)))))
a "scasb" ae 0x0 (seq (set _reg (cast 8 false (var rax))) (set _src (loadw 0 8 (var rdi))) (set _temp (- (var _reg) (var _src))) (set _result (var _temp)) (set _x (var _reg)) (set _y (var _src)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x1))) (set rdi (+ (var rdi) (bv 64 0x1)))))
a "scasd" af 0x0 (seq (set _reg (cast 32 false (var rax))) (set _src (loadw 0 32 (var rdi))) (set _temp (- (var _reg) (var _src))) (set _result (var _temp)) (set _x (var _reg)) (set _y (var _src)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x4))) (set rdi (+ (var rdi) (bv 64 0x4)))))
a "scasw" 66af 0x0 (seq (set _reg (cast 16 false (var rax))) (set _src (loadw 0 16 (var rdi))) (set _temp (- (var _reg) (var _src))) (set _result (var _temp)) (set _x (var _reg)) (set _y (var _src)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x2))) (set rdi (+ (var rdi) (bv 64 0x2)))))
d "scasd eax, dword [edi]" 67af 0x0 (seq (set _reg (cast 32 false (var rax))) (set _src (loadw 0 32 (cast 64 false (cast 32 false (var rdi))))) (set _temp (- (var _reg) (var _src))) (set _result (var _temp)) (set _x (var _reg)) (set _y (var _src)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (set rdi (cast 64 false (- (cast 32 false (var rdi)) (bv 32 0x4)))) (set rdi (cast 64 false (+ (cast 32 false (var rdi)) (bv 32 0x4))))))
d "scasq rax, qword [rdi]" 48af 0x0 (seq (set _reg (var rax)) (set _src (loadw 0 64 (var rdi))) (set _temp (- (var _reg) (var _src))) (set _result (var _temp)) (set _x (var _reg)) (set _y (var _src)) (set cf (|| (|| (&& (! (msb (var _x))) (msb (var _y))) (&& (msb (var _y)) (msb (var _result)))) (&& (msb (var _result)) (! (msb (var _x)))))) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (! (msb (var _y)))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (msb (var _y))))) (set af (|| (|| (&& (! (msb (cast 4 false (var _x)))) (msb (cast 4 false (var _y)))) (&& (msb (cast 4 false (var _y))) (msb (cast 4 false (var _result))))) (&& (msb (cast 4 false (var _result))) (! (msb (cast 4 false (var _x))))))) (set _result (var _temp)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))) (branch (var df) (set rdi (- (var rdi) (bv 64 0x8))) (set rdi (+ (var rdi) (bv 64 0x8)))))
ad "mul rax" 48f7e0 0x0 (seq (set _mul (* (cast 128 false (var rax)) (cast 128 false (var rax)))) (set rdx (cast 64 false (>> (var _mul) (bv 8 0x40) false))) (set rax (cast 64 false (var _mul))) (branch (is_zero (>> (var _mul) (bv 8 0x40) false)) (seq (set of false) (set cf false)) (seq (set of true) (set cf true))))
ad "div rax" 48f7f0 0x0 (seq (set _src (cast 128 false (var rax))) (branch (is_zero (var _src)) nop (seq (set _rdxrax (| (<< (cast 128 false (var rdx)) (bv 8 0x40) false) (cast 128 false (var rax)))) (set _temp (cast 64 false (div (var _rdxrax) (var _src)))) (branch (! (ule (var _temp) (bv 64 0xffffffffffffffff))) nop (seq (set rax (| (& (var rax) (~ (bv 64 0xffff))) (cast 64 false (var _temp)))) (set rdx (| (& (var rdx) (~ (bv 64 0xffff))) (cast 64 false (mod (var _rdxrax) (var _src))))))))))
ad "idiv rax" 48f7f8 0x0 (seq (set _src (cast 128 false (var rax))) (branch (is_zero (var _src)) nop (seq (set _rdxrax (| (<< (cast 128 false (cast 32 false (var rdx))) (bv 8 0x40) false) (cast 128 false (cast 32 false (var rax))))) (set _temp (cast 64 false (sdiv (var _rdxrax) (var _src)))) (branch (|| (! (sle (var _temp) (bv 64 0x7fffffffffffffff))) (&& (sle (var _temp) (bv 64 0x8000000000000000)) (! (== (var _temp) (bv 64 0x8000000000000000))))) nop (seq (set rax (| (& (var rax) (~ (bv 64 0xffff))) (cast 64 false (var _temp)))) (set rdx (| (& (var rdx) (~ (bv 64 0xffff))) (cast 64 false (smod (var _rdxrax) (var _src))))))))))
@ -59,8 +49,7 @@ a "lea rax, [rax+1]" 488d4001 0x0 (set rax (cast 64 false (+ (var rax) (bv 64 0x
a "lea rax, [rax-0]" 488d00 0x0 (set rax (cast 64 false (+ (var rax) (bv 64 0x0))))
a "lea rax, [rax-1]" 488d40ff 0x0 (set rax (cast 64 false (+ (var rax) (bv 64 0xffffffffffffffff))))
a "lea rax, [rax]" 488d00 0x0 (set rax (cast 64 false (+ (var rax) (bv 64 0x0))))
d "lea eax, [rax]" 8d00 0x0 (set rax (cast 64 false (cast 32 false (+ (var rax) (bv 64 0x0)))))
d "lea rax, [eax]" 67488d00 0x0 (set rax (cast 64 false (+ (cast 64 false (cast 32 false (var rax))) (bv 64 0x0))))
d "lea eax, qword [rax]" 8d00 0x0 (set rax (cast 64 false (cast 64 false (+ (var rax) (bv 64 0x0)))))
aB "lea rax,[rel -10]" 488d06f6ffffff
aB "lea rax,[rel 0]" 488d0500000000
aB "lea rax,[rel 10]" 488d050a000000
@ -73,7 +62,7 @@ a "lea rdi,[rip+0x1011]" 488d3d11100000 0x0 (set rdi (cast 64 false (+ (bv 64 0x
aB "lea rax, [0x803]" 488d042503080000
aB "lea rax, 0x803" 488d042503080000
a "mov [rsi], rbx" 48891e 0x0 (storew 0 (+ (var rsi) (bv 64 0x0)) (var rbx))
ad "mov eax, 0" b800000000 0x0 (set rax (cast 64 false (bv 32 0x0)))
ad "mov eax, 0x00" b800000000 0x0 (set rax (cast 64 false (bv 32 0x0)))
ad "mov ecx, 0x7fffffff" b9ffffff7f 0x0 (set rcx (cast 64 false (bv 32 0x7fffffff)))
a "mov esi, -0x80000000" be00000080 0x0 (set rsi (cast 64 false (bv 32 0x80000000)))
ad "mov esi, 0x80000000" be00000080 0x0 (set rsi (cast 64 false (bv 32 0x80000000)))
@ -84,14 +73,14 @@ a "mov rax, 3" 48c7c003000000 0x0 (set rax (bv 64 0x3))
a "mov rax, 33" 48c7c021000000 0x0 (set rax (bv 64 0x21))
ad "mov rax, 0x7fffffff" 48c7c0ffffff7f 0x0 (set rax (bv 64 0x7fffffff))
a "mov rax, 0x80000000" 48b80000008000000000 0x0 (set rax (bv 64 0x80000000))
ad "movabs rax, 0x80000000" 48b80000008000000000 0x0 (set rax (bv 64 0x80000000))
ad "mov rax, 0x80000000" 48b80000008000000000 0x0 (set rax (bv 64 0x80000000))
a "mov rax, 0xdeadbeef" 48b8efbeadde00000000 0x0 (set rax (bv 64 0xdeadbeef))
ad "movabs rax, 0xdeadbeef" 48b8efbeadde00000000 0x0 (set rax (bv 64 0xdeadbeef))
ad "mov rax, 0xdeadbeef" 48b8efbeadde00000000 0x0 (set rax (bv 64 0xdeadbeef))
a "mov rax, 0xffffffff" 48b8ffffffff00000000 0x0 (set rax (bv 64 0xffffffff))
ad "movabs rax, 0xffffffff" 48b8ffffffff00000000 0x0 (set rax (bv 64 0xffffffff))
ad "mov rax, 0xffffffff" 48b8ffffffff00000000 0x0 (set rax (bv 64 0xffffffff))
a "mov rax, 0x100000000" 48b80000000001000000 0x0 (set rax (bv 64 0x100000000))
ad "movabs rax, 0x100000000" 48b80000000001000000 0x0 (set rax (bv 64 0x100000000))
ad "mov rax, 0" 48c7c000000000 0x0 (set rax (bv 64 0x0))
ad "mov rax, 0x100000000" 48b80000000001000000 0x0 (set rax (bv 64 0x100000000))
ad "mov rax, 0x00" 48c7c000000000 0x0 (set rax (bv 64 0x0))
a "mov rax, -1" 48c7c0ffffffff 0x0 (set rax (bv 64 0xffffffffffffffff))
a "mov rax, -0x1" 48c7c0ffffffff 0x0 (set rax (bv 64 0xffffffffffffffff))
ad "mov rax, 0xffffffffffffffff" 48c7c0ffffffff 0x0 (set rax (bv 64 0xffffffffffffffff))
@ -103,16 +92,16 @@ ad "mov rax, 0xfffffffffffffffe" 48c7c0feffffff 0x0 (set rax (bv 64 0xffffffffff
a "mov rax, -0x80000000" 48c7c000000080 0x0 (set rax (bv 64 0xffffffff80000000))
ad "mov rax, 0xffffffff80000000" 48c7c000000080 0x0 (set rax (bv 64 0xffffffff80000000))
a "mov rax, -0x80000001" 48b8ffffff7fffffffff 0x0 (set rax (bv 64 0xffffffff7fffffff))
ad "movabs rax, 0xffffffff7fffffff" 48b8ffffff7fffffffff 0x0 (set rax (bv 64 0xffffffff7fffffff))
ad "mov rax, 0xffffffff7fffffff" 48b8ffffff7fffffffff 0x0 (set rax (bv 64 0xffffffff7fffffff))
ad "mov r9, 0x7fffffff" 49c7c1ffffff7f 0x0 (set r9 (cast 64 false (bv 64 0x7fffffff)))
a "mov r10, 0x80000000" 49ba0000008000000000 0x0 (set r10 (cast 64 false (bv 64 0x80000000)))
ad "movabs r10, 0x80000000" 49ba0000008000000000 0x0 (set r10 (cast 64 false (bv 64 0x80000000)))
ad "mov r10, 0x80000000" 49ba0000008000000000 0x0 (set r10 (cast 64 false (bv 64 0x80000000)))
a "mov r11, 0x100000000" 49bb0000000001000000 0x0 (set r11 (cast 64 false (bv 64 0x100000000)))
ad "movabs r11, 0x100000000" 49bb0000000001000000 0x0 (set r11 (cast 64 false (bv 64 0x100000000)))
ad "mov r11, 0x100000000" 49bb0000000001000000 0x0 (set r11 (cast 64 false (bv 64 0x100000000)))
a "mov r14, -0x80000000" 49c7c600000080 0x0 (set r14 (cast 64 false (bv 64 0xffffffff80000000)))
ad "mov r14, 0xffffffff80000000" 49c7c600000080 0x0 (set r14 (cast 64 false (bv 64 0xffffffff80000000)))
a "mov r15, -0x80000001" 49bfffffff7fffffffff 0x0 (set r15 (cast 64 false (bv 64 0xffffffff7fffffff)))
ad "movabs r15, 0xffffffff7fffffff" 49bfffffff7fffffffff 0x0 (set r15 (cast 64 false (bv 64 0xffffffff7fffffff)))
ad "mov r15, 0xffffffff7fffffff" 49bfffffff7fffffffff 0x0 (set r15 (cast 64 false (bv 64 0xffffffff7fffffff)))
a "mov rax, [rax+0]" 488b00 0x0 (set rax (loadw 0 64 (+ (var rax) (bv 64 0x0))))
a "mov rax, [rax+1]" 488b4001 0x0 (set rax (loadw 0 64 (+ (var rax) (bv 64 0x1))))
a "mov rax, [rax-0]" 488b00 0x0 (set rax (loadw 0 64 (+ (var rax) (bv 64 0x0))))
@ -810,7 +799,7 @@ aB "mov qword[r12], rsp" 49892424
aB "mov qword[r8 + 0x20], rax" 49894020
aB "mov r12, qword[r12]" 4d8b2424
a "mov eax,r12d" 4489e0 0x0 (set rax (cast 64 false (cast 32 false (var r12))))
ad "movabs r12, 1" 49bc0100000000000000
ad "mov r12, 0x01" 49c7c401000000
a "inc al" fec0 0x0 (seq (set _op (cast 8 false (var rax))) (set _result (+ (var _op) (bv 8 0x1))) (set rax (| (& (var rax) (~ (bv 64 0xff))) (cast 64 false (var _result)))) (set _result (var _result)) (set _x (var _op)) (set _y (bv 8 0x1)) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))) (set _result (var _result)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
a "inc BYTE PTR [r12]" 41fe0424 0x0 (seq (set _op (loadw 0 8 (+ (cast 64 false (var r12)) (bv 64 0x0)))) (set _result (+ (var _op) (bv 8 0x1))) (storew 0 (+ (cast 64 false (var r12)) (bv 64 0x0)) (var _result)) (set _result (var _result)) (set _x (var _op)) (set _y (bv 8 0x1)) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))) (set _result (var _result)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
a "inc BYTE PTR [rbx+0x18]" fe4318 0x0 (seq (set _op (loadw 0 8 (+ (var rbx) (bv 64 0x18)))) (set _result (+ (var _op) (bv 8 0x1))) (storew 0 (+ (var rbx) (bv 64 0x18)) (var _result)) (set _result (var _result)) (set _x (var _op)) (set _y (bv 8 0x1)) (set of (|| (&& (&& (! (msb (var _result))) (msb (var _x))) (msb (var _y))) (&& (&& (msb (var _result)) (! (msb (var _x)))) (! (msb (var _y)))))) (set af (|| (|| (&& (msb (cast 4 false (var _x))) (msb (cast 4 false (var _y)))) (&& (! (msb (cast 4 false (var _result)))) (msb (cast 4 false (var _y))))) (&& (msb (cast 4 false (var _x))) (! (msb (cast 4 false (var _result))))))) (set _result (var _result)) (set pf (! (lsb (let _val (cast 8 false (var _result)) (let _c4 (^ (var _val) (>> (var _val) (bv 8 0x4) false)) (let _c2 (^ (var _c4) (>> (var _c4) (bv 8 0x2) false)) (^ (var _c2) (>> (var _c2) (bv 8 0x1) false)))))))) (set zf (is_zero (var _result))) (set sf (msb (var _result))))
@ -1004,8 +993,8 @@ a "bswap r15" 490fcf
a "bswap eax" 0fc8
a "bswap r15d" 410fcf
ad "endbr64" f30f1efa
d "enter 8, 0" c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 64 0x8))) (set _nest_lvl (mod (cast 8 false (bv 64 0x0)) (bv 8 0x20))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var rbp))) (set rsp (var final)) (set _frame_tmp (var rsp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set rbp (- (var rbp) (bv 64 0x8))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (loadw 0 64 (var rbp)))) (set rsp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var _frame_tmp))) (set rsp (var final)))) (set rsp (- (var rsp) (cast 64 false (var _alloc_sz)))) (set rbp (var _frame_tmp)))
d "enter 8, 0" 66c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 32 0x8))) (set _nest_lvl (mod (cast 8 false (bv 32 0x0)) (bv 8 0x20))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (cast 32 false (var rbp)))) (set rsp (var final)) (set _frame_tmp (var rsp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set rbp (- (var rbp) (bv 64 0x4))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (loadw 0 32 (var rbp)))) (set rsp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var _frame_tmp))) (set rsp (var final)))) (set rsp (- (var rsp) (cast 64 false (var _alloc_sz)))) (set rbp (cast 64 false (var _frame_tmp))))
d "enter 0x08, 0x00" c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 16 0x8))) (set _nest_lvl (mod (cast 8 false (bv 8 0x0)) (bv 8 0x20))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var rbp))) (set rsp (var final)) (set _frame_tmp (var rsp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set rbp (- (var rbp) (bv 64 0x8))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (loadw 0 64 (var rbp)))) (set rsp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var _frame_tmp))) (set rsp (var final)))) (set rsp (- (var rsp) (cast 64 false (var _alloc_sz)))) (set rbp (var _frame_tmp)))
d "enter 0x08, 0x00" 66c8080000 0x0 (seq (set _alloc_sz (cast 16 false (bv 16 0x8))) (set _nest_lvl (mod (cast 8 false (bv 8 0x0)) (bv 8 0x20))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var rbp))) (set rsp (var final)) (set _frame_tmp (var rsp)) (branch (is_zero (var _nest_lvl)) nop (seq (branch (! (ule (var _nest_lvl) (bv 8 0x1))) (seq (set _itr (bv 8 0x1)) (repeat (&& (ule (var _itr) (var _nest_lvl)) (! (== (var _itr) (var _nest_lvl)))) (seq (set rbp (- (var rbp) (bv 64 0x8))) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (loadw 0 64 (var rbp)))) (set rsp (var final)) (set _itr (+ (var _itr) (bv 8 0x1)))))) nop) (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (var _frame_tmp))) (set rsp (var final)))) (set rsp (- (var rsp) (cast 64 false (var _alloc_sz)))) (set rbp (var _frame_tmp)))
a "xchg eax, r8d" 4190 0x0 (seq (set _temp (cast 32 false (var r8))) (set r8 (cast 64 false (cast 32 false (var rax)))) (set rax (cast 64 false (var _temp))))
ad "xchg r8d, eax" 4190 0x0 (seq (set _temp (cast 32 false (var r8))) (set r8 (cast 64 false (cast 32 false (var rax)))) (set rax (cast 64 false (var _temp))))
a "xchg rax, rdx" 4892 0x0 (seq (set _temp (var rdx)) (set rdx (var rax)) (set rax (var _temp)))
@ -1020,9 +1009,9 @@ ad "xchg r8d, r15d" 4587f8 0x0 (seq (set _temp (cast 32 false (var r8))) (set r8
ad "xchg r15d, r8d" 4587c7 0x0 (seq (set _temp (cast 32 false (var r15))) (set r15 (cast 64 false (cast 32 false (var r8)))) (set r8 (cast 64 false (var _temp))))
ad "xchg rdx, r8" 4c87c2 0x0 (seq (set _temp (var rdx)) (set rdx (var r8)) (set r8 (cast 64 false (var _temp))))
ad "xchg r15, rdx" 4987d7 0x0 (seq (set _temp (var r15)) (set r15 (cast 64 false (var rdx))) (set rdx (var _temp)))
d "call qword [rip + 0x3a8f3e]" 48ff153e8f3a00 0x0 (seq (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (bv 64 0x7))) (set rsp (var final)) (jmp (loadw 0 64 (+ (bv 64 0x7) (bv 64 0x3a8f3e)))))
d "call qword [rip + 0x1d638f]" 48ff158f631d00 0x0 (seq (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (bv 64 0x7))) (set rsp (var final)) (jmp (loadw 0 64 (+ (bv 64 0x7) (bv 64 0x1d638f)))))
a "fmul st2, st0" dcca 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st2) )) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
d "call qword [rip+0x3a8f3e]" 48ff153e8f3a00 0x0 (seq (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (bv 64 0x7))) (set rsp (var final)) (jmp (loadw 0 64 (+ (bv 64 0x7) (bv 64 0x3a8f3e)))))
d "call qword [rip+0x1d638f]" 48ff158f631d00 0x0 (seq (set final (- (var rsp) (bv 64 0x8))) (storew 0 (var final) (cast 64 false (bv 64 0x7))) (set rsp (var final)) (jmp (loadw 0 64 (+ (bv 64 0x7) (bv 64 0x1d638f)))))
a "fmul st2, st0" dcca 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st0) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fdiv st0, st1" d8f1 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st1) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdiv st(0), st(1)" d8f1 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st1) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdiv st0, st7" d8f7 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st7) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
@ -1051,7 +1040,7 @@ a "fucom st(2)" dde2 0x0 (seq (set swd (| (<< (ite (&& (! (|| (is_nan (float 2 (
a "fucomp" dde9 0x0 (seq (set swd (| (<< (ite (&& (! (|| (is_nan (float 2 (var st0) )) (is_nan (float 2 (var st1) )))) (<. (float 2 (var st0) ) (float 2 (var st1) ))) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x8) false) (& (bv 16 0xfeff) (var swd)))) (set swd (| (<< (ite false (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))) (set swd (| (<< (ite false (bv 16 0x1) (bv 16 0x0)) (bv 8 0xa) false) (& (bv 16 0xfbff) (var swd)))) (set swd (| (<< (ite (! (|| (|| (is_nan (float 2 (var st0) )) (is_nan (float 2 (var st1) ))) (|| (<. (float 2 (var st0) ) (float 2 (var st1) )) (<. (float 2 (var st1) ) (float 2 (var st0) ))))) (bv 16 0x1) (bv 16 0x0)) (bv 8 0xe) false) (& (bv 16 0xbfff) (var swd)))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fucomp st(2)" ddea 0x0 (seq (set swd (| (<< (ite (&& (! (|| (is_nan (float 2 (var st0) )) (is_nan (float 2 (var st2) )))) (<. (float 2 (var st0) ) (float 2 (var st2) ))) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x8) false) (& (bv 16 0xfeff) (var swd)))) (set swd (| (<< (ite false (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))) (set swd (| (<< (ite false (bv 16 0x1) (bv 16 0x0)) (bv 8 0xa) false) (& (bv 16 0xfbff) (var swd)))) (set swd (| (<< (ite (! (|| (|| (is_nan (float 2 (var st0) )) (is_nan (float 2 (var st2) ))) (|| (<. (float 2 (var st0) ) (float 2 (var st2) )) (<. (float 2 (var st2) ) (float 2 (var st0) ))))) (bv 16 0x1) (bv 16 0x0)) (bv 8 0xe) false) (& (bv 16 0xbfff) (var swd)))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "faddp" dec1 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (+. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (+. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (+. rtp (var x_rm) (var y_rm)) (+. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "faddp st2, st0" dec2 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (+. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (+. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (+. rtp (var x_rm) (var y_rm)) (+. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "faddp st2, st0" dec2 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (+. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (+. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (+. rtp (var x_rm) (var y_rm)) (+. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fiadd word [rax]" de00 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 16 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (+. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (+. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (+. rtp (var x_rm) (var y_rm)) (+. rtz (var x_rm) (var y_rm))))))))
a "fiadd dword [rax]" da00 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 32 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (+. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (+. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (+. rtp (var x_rm) (var y_rm)) (+. rtz (var x_rm) (var y_rm))))))))
a "fadd dword [rax]" d800 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 0 (loadw 0 32 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (+. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (+. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (+. rtp (var x_rm) (var y_rm)) (+. rtz (var x_rm) (var y_rm))))))))
@ -1082,41 +1071,41 @@ a "fnstenv [rcx]" d931
a "fdiv dword[rax]" d830 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 0 (loadw 0 32 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdiv qword [rax]" dc30 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 1 (loadw 0 64 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdiv st0, st7" d8f7 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st7) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdiv st6, st0" dcfe 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st6) )) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdiv st6, st0" dcfe 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st0) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivp" def9 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fdivp st2, st0" defa 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fdivp st2, st0" defa 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fidiv word [rax]" de30 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 16 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fidiv dword [rax]" da30 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 32 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivr dword[rax]" d838 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 0 (loadw 0 32 (+ (var rax) (bv 64 0x0))) )) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivr qword [rax]" dc38 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 1 (loadw 0 64 (+ (var rax) (bv 64 0x0))) )) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivr st0, st7" d8ff 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st7) )) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivr st6, st0" dcf6 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st6) )) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivr st6, st0" dcf6 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st0) )) (set x_rm (float 2 (var st6) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fdivrp" def1 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fdivrp st2, st0" def2 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fdivrp st2, st0" def2 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fidivr word [rax]" de38 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 16 (+ (var rax) (bv 64 0x0)))) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fidivr dword [rax]" da38 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 32 (+ (var rax) (bv 64 0x0)))) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (/. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (/. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (/. rtp (var x_rm) (var y_rm)) (/. rtz (var x_rm) (var y_rm))))))))
a "fmul dword[rax]" d808 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 0 (loadw 0 32 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fmul qword [rax]" dc08 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 1 (loadw 0 64 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fmul st0, st7" d8cf 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st7) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fmul st6, st0" dcce 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st6) )) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fmul st6, st0" dcce 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st0) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fmulp" dec9 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fmulp st2, st0" deca 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fmulp st2, st0" deca 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fimul word [rax]" de08 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 16 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fimul dword [rax]" da08 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 32 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (*. rne (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x1)) (*. rtn (var x_rm) (var y_rm)) (ite (== (var _rmode) (bv 2 0x2)) (*. rtp (var x_rm) (var y_rm)) (*. rtz (var x_rm) (var y_rm))))))))
a "fsub dword[rax]" d820 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 0 (loadw 0 32 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsub qword [rax]" dc20 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 1 (loadw 0 64 (+ (var rax) (bv 64 0x0))) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsub st0, st7" d8e7 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st7) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsub st6, st0" dcee 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st6) )) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsub st6, st0" dcee 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st0) )) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubp" dee9 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fsubp st2, st0" deea 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st1) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fsubp st2, st0" deea 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st0) )) (set y_rm (float 2 (var st2) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fisub word [rax]" de20 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 16 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fisub dword [rax]" da20 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 32 (+ (var rax) (bv 64 0x0)))) (set x_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set y_rm (float 2 (var st0) )) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubr dword[rax]" d828 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 0 (loadw 0 32 (+ (var rax) (bv 64 0x0))) )) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubr qword [rax]" dc28 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 1 (loadw 0 64 (+ (var rax) (bv 64 0x0))) )) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubr st0, st7" d8ef 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st7) )) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubr st6, st0" dce6 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st6) )) (set y_rm (float 2 (var st6) )) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubr st6, st0" dce6 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set f_val_rm (float 2 (var st0) )) (set x_rm (float 2 (var st6) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fconvert ieee754-bin80 rne (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fconvert ieee754-bin80 rtn (var f_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fconvert ieee754-bin80 rtp (var f_val_rm)) (fconvert ieee754-bin80 rtz (var f_val_rm)))))) (set st6 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fsubrp" dee1 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st1) )) (set y_rm (float 2 (var st0) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fsubrp st2, st0" dee2 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st1) )) (set y_rm (float 2 (var st0) )) (set st1 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fsubrp st2, st0" dee2 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set x_rm (float 2 (var st2) )) (set y_rm (float 2 (var st0) )) (set st2 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))) (set swd (| (<< (cast 16 false (+ (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x1))) (bv 8 0xb) false) (& (bv 16 0xc7ff) (var swd)))) (set st0 (fbits (float 2 (var st1) ))) (set st1 (fbits (float 2 (var st2) ))) (set st2 (fbits (float 2 (var st3) ))) (set st3 (fbits (float 2 (var st4) ))) (set st4 (fbits (float 2 (var st5) ))) (set st5 (fbits (float 2 (var st6) ))) (set st6 (fbits (float 2 (var st7) ))) (set swd (| (<< (ite (== (cast 3 false (>> (var swd) (bv 8 0xb) false)) (bv 3 0x0)) (bv 16 0x1) (bv 16 0x0)) (bv 8 0x9) false) (& (bv 16 0xfdff) (var swd)))))
a "fisubr word [rax]" de28 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 16 (+ (var rax) (bv 64 0x0)))) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
a "fisubr dword [rax]" da28 0x0 (seq (set _rmode (cast 2 false (>> (var cwd) (bv 8 0xa) false))) (set i_val_rm (loadw 0 32 (+ (var rax) (bv 64 0x0)))) (set x_rm (float 2 (var st0) )) (set y_rm (ite (== (var _rmode) (bv 2 0x0)) (fcast_sfloat ieee754-bin80 rne (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x1)) (fcast_sfloat ieee754-bin80 rtn (var i_val_rm)) (ite (== (var _rmode) (bv 2 0x2)) (fcast_sfloat ieee754-bin80 rtp (var i_val_rm)) (fcast_sfloat ieee754-bin80 rtz (var i_val_rm)))))) (set st0 (fbits (ite (== (var _rmode) (bv 2 0x0)) (-. rne (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x1)) (-. rtn (var y_rm) (var x_rm)) (ite (== (var _rmode) (bv 2 0x2)) (-. rtp (var y_rm) (var x_rm)) (-. rtz (var y_rm) (var x_rm))))))))
# Not testing [fstcw] and [fstsw] since they are made up of a [wait] instruction and a [fnstcw] (or [fnstsw]) instruction, and we already test both of these instructions.

2
test/db/cmd/cmd_a8
View file

@ -18,6 +18,6 @@ e asm.bits=64
a8j c745f400000000
EOF
EXPECT=<<EOF
[{"opcode":"mov dword [rbp - 0xc], 0","disasm":"mov dword [rbp - 0xc], 0","pseudo":"dword [rbp - 0xc] = 0","description":"moves data from src to dst","mnemonic":"mov","mask":"ffffffffffffff","esil":"0,0xc,rbp,-,=[4]","rzil":{"opcode":"storew","mem":0,"key":{"opcode":"+","x":{"opcode":"var","value":"rbp"},"y":{"opcode":"bitv","bits":"0xfffffffffffffff4","len":64}},"value":{"opcode":"bitv","bits":"0x0","len":32}},"sign":false,"prefix":0,"id":460,"opex":{"operands":[{"size":4,"rw":2,"type":"mem","base":"rbp","scale":1,"disp":-12},{"size":4,"rw":0,"type":"imm","value":0}],"modrm":true,"disp":-12},"addr":0,"bytes":"c745f400000000","val":0,"disp":18446744073709551604,"size":7,"type":"mov","esilcost":12,"scale":0,"refptr":4,"cycles":1,"failcycles":0,"delay":0,"stack":"set","stackptr":8,"family":"cpu"}]
[{"opcode":"mov dword [rbp-0x0c], 0x00","disasm":"mov dword [rbp-0x0c], 0x00","pseudo":"dword [rbp-0x0c] = 0x00","description":"moves data from src to dst","mnemonic":"mov","mask":"ffffffffffffff","esil":"0,0xc,rbp,-,=[4]","rzil":{"opcode":"storew","mem":0,"key":{"opcode":"+","x":{"opcode":"var","value":"rbp"},"y":{"opcode":"bitv","bits":"0xfffffffffffffff4","len":64}},"value":{"opcode":"bitv","bits":"0x0","len":32}},"sign":false,"prefix":0,"id":436,"opex":{"operands":[{"size":4,"rw":2,"type":"mem","segment":"ss","base":"rbp","scale":0,"disp":-12},{"size":4,"rw":1,"type":"imm","value":0}],"modrm":true,"disp":-12},"addr":0,"bytes":"c745f400000000","val":0,"disp":18446744073709551604,"size":7,"type":"mov","esilcost":12,"scale":0,"refptr":4,"cycles":1,"failcycles":0,"delay":0,"stack":"set","stackptr":8,"family":"cpu"}]
EOF
RUN

2
test/db/cmd/cmd_aL
View file

@ -61,7 +61,7 @@ _dAeI 32 v810 LGPL3 NEC V810 disassembler (by pancake)
_dAeI 32 v850 LGPL3 NEC/Renesas V850 disassembler
_dA__ 8 32 vax GPL3 DEC VAX disassembler
adA__ 32 wasm MIT WebAssembly disassembler (by cgvwzq) v0.1.0
_dAeI 16 32 64 x86 BSD X86/X86_64 Capstone-based disassembler
_dAeI 16 32 64 x86 MIT X86/X86_64 Zydis-based disassembler
a____ 16 32 64 x86.as LGPL3 Intel X86 GNU Assembler (Use RZ_X86_AS env)
a____ 16 32 64 x86.nasm LGPL3 X86 nasm assembler
a____ 16 32 64 x86.nz LGPL3 x86 handmade assembler

26
test/db/cmd/cmd_af
View file

@ -39,7 +39,7 @@ f. foobar @ 0x100001216
pd 20~foo
EOF
EXPECT=<<EOF
| ,=< 0x10000120f 7f05 jg .foobar ; main.foobar
| ,=< 0x10000120f 7f05 jnle .foobar ; main.foobar
| | .foobar:
EOF
RUN
@ -129,15 +129,15 @@ EXPECT=<<EOF
/ sym.register_tm_clones();
| 0x08048410 mov eax, obj.completed.6891
| 0x08048415 sub eax, obj.completed.6891
| 0x0804841a sar eax, 2
| 0x0804841a sar eax, 0x02
| 0x0804841d mov edx, eax
| 0x0804841f shr edx, 0x1f
| 0x08048422 add eax, edx
| 0x08048424 sar eax, 1
| ,=< 0x08048426 je 0x8048448
| | 0x08048428 mov edx, 0
| 0x08048424 sar eax, 0x01
| ,=< 0x08048426 jz 0x8048448
| | 0x08048428 mov edx, 0x00
| | 0x0804842d test edx, edx
| ,==< 0x0804842f je 0x8048448
| ,==< 0x0804842f jz 0x8048448
| || 0x08048431 push ebp
| || 0x08048432 mov ebp, esp
| || 0x08048434 sub esp, 0x10
@ -185,7 +185,7 @@ size: 13
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
| 0x004017c6 3d00100000 cmp eax, 0x1000
\ ,=< 0x004017cb 7210 jb 0x4017dd
@ -195,7 +195,7 @@ size: 6
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
\ 0x004017c3 83c108 add ecx, 8
\ 0x004017c3 83c108 add ecx, 0x08
size: 11
0x004017c0 0x004017cb 00:0000 11 j 0x004017dd f 0x004017cd
@ -203,7 +203,7 @@ size: 11
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
\ 0x004017c6 3d00100000 cmp eax, 0x1000
EOF
EXPECT_ERR=
@ -238,13 +238,13 @@ size: 9
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
..
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
| 0x004017c6 3d invalid
\ 0x004017c7 0010 add byte [eax], dl
| ----------- true: 0x004017dd false: 0x004017cd
@ -255,14 +255,14 @@ size: 12
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
| 0x004017c6 3d00100000 cmp eax, 0x1000
..
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
| 0x004017c6 3d00100000 cmp eax, 0x1000
| 0x004017cb 72 invalid
| ----------- true: 0x004017dd false: 0x004017cd

20
test/db/cmd/cmd_ag
View file

@ -809,17 +809,17 @@ EXPECT=<<EOF
| push rax |
| push rsp |
| ; 0x8c0 |
| lea r8, [sym.__libc_csu_fini] |
| lea r8, qword [sym.__libc_csu_fini] |
| ; 0x850 |
| ; "AWAVA\x89\xffAUATL\x8d%.\U00000005 " |
| lea rcx, [sym.__libc_csu_init] |
| lea rcx, qword [sym.__libc_csu_init] |
| ; 0x7aa |
| lea rdi, [main] |
| lea rdi, qword [main] |
| ; [reloc.__libc_start_main:8]=0x201058 reloc.target.__libc_start_main |
| ; "X\U00000010 " |
| call qword [reloc.__libc_start_main] |
`-----------------------------------------------------------------------'
agn "0x6a0" base64:OyBbMTNdIC1yLXggc2VjdGlvbiBzaXplIDU0NiBuYW1lZCAudGV4dAogIDstLSBzZWN0aW9uLi50ZXh0OgogIDstLSAudGV4dDoKICA7LS0gX3N0YXJ0OgplbnRyeTAoaW50NjRfdCBhcmczKTsKOyBhcmcgaW50NjRfdCBhcmczIEAgcmR4CnhvciBlYnAsIGVicAo7IGFyZzMKbW92IHI5LCByZHgKcG9wIHJzaQptb3YgcmR4LCByc3AKYW5kIHJzcCwgMHhmZmZmZmZmZmZmZmZmZmYwCnB1c2ggcmF4CnB1c2ggcnNwCjsgMHg4YzAKbGVhIHI4LCBbc3ltLl9fbGliY19jc3VfZmluaV0KOyAweDg1MAo7ICJBV0FWQVx4ODlceGZmQVVBVExceDhkJS5cVTAwMDAwMDA1ICIKbGVhIHJjeCwgW3N5bS5fX2xpYmNfY3N1X2luaXRdCjsgMHg3YWEKbGVhIHJkaSwgW21haW5dCjsgW3JlbG9jLl9fbGliY19zdGFydF9tYWluOjhdPTB4MjAxMDU4IHJlbG9jLnRhcmdldC5fX2xpYmNfc3RhcnRfbWFpbgo7ICJYXFUwMDAwMDAxMCAiCmNhbGwgcXdvcmQgW3JlbG9jLl9fbGliY19zdGFydF9tYWluXQ==
agn "0x6a0" base64:OyBbMTNdIC1yLXggc2VjdGlvbiBzaXplIDU0NiBuYW1lZCAudGV4dAogIDstLSBzZWN0aW9uLi50ZXh0OgogIDstLSAudGV4dDoKICA7LS0gX3N0YXJ0OgplbnRyeTAoaW50NjRfdCBhcmczKTsKOyBhcmcgaW50NjRfdCBhcmczIEAgcmR4CnhvciBlYnAsIGVicAo7IGFyZzMKbW92IHI5LCByZHgKcG9wIHJzaQptb3YgcmR4LCByc3AKYW5kIHJzcCwgMHhmZmZmZmZmZmZmZmZmZmYwCnB1c2ggcmF4CnB1c2ggcnNwCjsgMHg4YzAKbGVhIHI4LCBxd29yZCBbc3ltLl9fbGliY19jc3VfZmluaV0KOyAweDg1MAo7ICJBV0FWQVx4ODlceGZmQVVBVExceDhkJS5cVTAwMDAwMDA1ICIKbGVhIHJjeCwgcXdvcmQgW3N5bS5fX2xpYmNfY3N1X2luaXRdCjsgMHg3YWEKbGVhIHJkaSwgcXdvcmQgW21haW5dCjsgW3JlbG9jLl9fbGliY19zdGFydF9tYWluOjhdPTB4MjAxMDU4IHJlbG9jLnRhcmdldC5fX2xpYmNfc3RhcnRfbWFpbgo7ICJYXFUwMDAwMDAxMCAiCmNhbGwgcXdvcmQgW3JlbG9jLl9fbGliY19zdGFydF9tYWluXQ==
digraph code {
rankdir=LR;
outputorder=edgesfirst
@ -841,12 +841,12 @@ and rsp, 0xfffffffffffffff0
push rax
push rsp
; 0x8c0
lea r8, [sym.__libc_csu_fini]
lea r8, qword [sym.__libc_csu_fini]
; 0x850
; 'AWAVA\x89\xffAUATL\x8d%.\U00000005 '
lea rcx, [sym.__libc_csu_init]
lea rcx, qword [sym.__libc_csu_init]
; 0x7aa
lea rdi, [main]
lea rdi, qword [main]
; [reloc.__libc_start_main:8]=0x201058 reloc.target.__libc_start_main
; 'X\U00000010 '
call qword [reloc.__libc_start_main]
@ -862,15 +862,15 @@ directed 1
label "0x6a0"
]
]
{"nodes":[{"id":0,"title":"0x6a0","body":"; [13] -r-x section size 546 named .text\n ;-- section..text:\n ;-- .text:\n ;-- _start:\nentry0(int64_t arg3);\n; arg int64_t arg3 @ rdx\nxor ebp, ebp\n; arg3\nmov r9, rdx\npop rsi\nmov rdx, rsp\nand rsp, 0xfffffffffffffff0\npush rax\npush rsp\n; 0x8c0\nlea r8, [sym.__libc_csu_fini]\n; 0x850\n; \"AWAVA\\x89\\xffAUATL\\x8d%.\\U00000005 \"\nlea rcx, [sym.__libc_csu_init]\n; 0x7aa\nlea rdi, [main]\n; [reloc.__libc_start_main:8]=0x201058 reloc.target.__libc_start_main\n; \"X\\U00000010 \"\ncall qword [reloc.__libc_start_main]\n","offset":1696,"out_nodes":[]}]}
{"nodes":[{"id":0,"title":"0x6a0","body":"; [13] -r-x section size 546 named .text\n ;-- section..text:\n ;-- .text:\n ;-- _start:\nentry0(int64_t arg3);\n; arg int64_t arg3 @ rdx\nxor ebp, ebp\n; arg3\nmov r9, rdx\npop rsi\nmov rdx, rsp\nand rsp, 0xfffffffffffffff0\npush rax\npush rsp\n; 0x8c0\nlea r8, [sym.__libc_csu_fini]\n; 0x850\n; \"AWAVA\\x89\\xffAUATL\\x8d%.\\U00000005 \"\nlea rcx, [sym.__libc_csu_init]\n; 0x7aa\nlea rdi, [main]\n; [reloc.__libc_start_main:8]=0x201058 reloc.target.__libc_start_main\n; \"X\\U00000010 \"\ncall qword [reloc.__libc_start_main]\n","offset":1696,"out_nodes":[]}]}
{"nodes":[{"id":0,"title":"0x6a0","body":"; [13] -r-x section size 546 named .text\n ;-- section..text:\n ;-- .text:\n ;-- _start:\nentry0(int64_t arg3);\n; arg int64_t arg3 @ rdx\nxor ebp, ebp\n; arg3\nmov r9, rdx\npop rsi\nmov rdx, rsp\nand rsp, 0xfffffffffffffff0\npush rax\npush rsp\n; 0x8c0\nlea r8, qword [sym.__libc_csu_fini]\n; 0x850\n; \"AWAVA\\x89\\xffAUATL\\x8d%.\\U00000005 \"\nlea rcx, qword [sym.__libc_csu_init]\n; 0x7aa\nlea rdi, qword [main]\n; [reloc.__libc_start_main:8]=0x201058 reloc.target.__libc_start_main\n; \"X\\U00000010 \"\ncall qword [reloc.__libc_start_main]\n","offset":1696,"out_nodes":[]}]}
{"nodes":[{"id":0,"title":"0x6a0","body":"; [13] -r-x section size 546 named .text\n ;-- section..text:\n ;-- .text:\n ;-- _start:\nentry0(int64_t arg3);\n; arg int64_t arg3 @ rdx\nxor ebp, ebp\n; arg3\nmov r9, rdx\npop rsi\nmov rdx, rsp\nand rsp, 0xfffffffffffffff0\npush rax\npush rsp\n; 0x8c0\nlea r8, qword [sym.__libc_csu_fini]\n; 0x850\n; \"AWAVA\\x89\\xffAUATL\\x8d%.\\U00000005 \"\nlea rcx, qword [sym.__libc_csu_init]\n; 0x7aa\nlea rdi, qword [main]\n; [reloc.__libc_start_main:8]=0x201058 reloc.target.__libc_start_main\n; \"X\\U00000010 \"\ncall qword [reloc.__libc_start_main]\n","offset":1696,"out_nodes":[]}]}
agraph.color_box=G1swbQ==
agraph.delta_x=0xb
agraph.delta_y=0x1
agraph.h=0x1e
agraph.is_callgraph=false
agraph.nodes=0x6a0
agraph.nodes.0x6a0.body=base64:OyBbMTNdIC1yLXggc2VjdGlvbiBzaXplIDU0NiBuYW1lZCAudGV4dAogIDstLSBzZWN0aW9uLi50ZXh0OgogIDstLSAudGV4dDoKICA7LS0gX3N0YXJ0OgplbnRyeTAoaW50NjRfdCBhcmczKTsKOyBhcmcgaW50NjRfdCBhcmczIEAgcmR4CnhvciBlYnAsIGVicAo7IGFyZzMKbW92IHI5LCByZHgKcG9wIHJzaQptb3YgcmR4LCByc3AKYW5kIHJzcCwgMHhmZmZmZmZmZmZmZmZmZmYwCnB1c2ggcmF4CnB1c2ggcnNwCjsgMHg4YzAKbGVhIHI4LCBbc3ltLl9fbGliY19jc3VfZmluaV0KOyAweDg1MAo7ICJBV0FWQVx4ODlceGZmQVVBVExceDhkJS5cVTAwMDAwMDA1ICIKbGVhIHJjeCwgW3N5bS5fX2xpYmNfY3N1X2luaXRdCjsgMHg3YWEKbGVhIHJkaSwgW21haW5dCjsgW3JlbG9jLl9fbGliY19zdGFydF9tYWluOjhdPTB4MjAxMDU4IHJlbG9jLnRhcmdldC5fX2xpYmNfc3RhcnRfbWFpbgo7ICJYXFUwMDAwMDAxMCAiCmNhbGwgcXdvcmQgW3JlbG9jLl9fbGliY19zdGFydF9tYWluXQ==
agraph.nodes.0x6a0.body=base64:OyBbMTNdIC1yLXggc2VjdGlvbiBzaXplIDU0NiBuYW1lZCAudGV4dAogIDstLSBzZWN0aW9uLi50ZXh0OgogIDstLSAudGV4dDoKICA7LS0gX3N0YXJ0OgplbnRyeTAoaW50NjRfdCBhcmczKTsKOyBhcmcgaW50NjRfdCBhcmczIEAgcmR4CnhvciBlYnAsIGVicAo7IGFyZzMKbW92IHI5LCByZHgKcG9wIHJzaQptb3YgcmR4LCByc3AKYW5kIHJzcCwgMHhmZmZmZmZmZmZmZmZmZmYwCnB1c2ggcmF4CnB1c2ggcnNwCjsgMHg4YzAKbGVhIHI4LCBxd29yZCBbc3ltLl9fbGliY19jc3VfZmluaV0KOyAweDg1MAo7ICJBV0FWQVx4ODlceGZmQVVBVExceDhkJS5cVTAwMDAwMDA1ICIKbGVhIHJjeCwgcXdvcmQgW3N5bS5fX2xpYmNfY3N1X2luaXRdCjsgMHg3YWEKbGVhIHJkaSwgcXdvcmQgW21haW5dCjsgW3JlbG9jLl9fbGliY19zdGFydF9tYWluOjhdPTB4MjAxMDU4IHJlbG9jLnRhcmdldC5fX2xpYmNfc3RhcnRfbWFpbgo7ICJYXFUwMDAwMDAxMCAiCmNhbGwgcXdvcmQgW3JlbG9jLl9fbGliY19zdGFydF9tYWluXQ==
agraph.nodes.0x6a0.h=0x1b
agraph.nodes.0x6a0.w=0x49
agraph.nodes.0x6a0.x=0

2
test/db/cmd/cmd_agf
View file

@ -21,6 +21,6 @@ af
agf J
EOF
EXPECT=<<EOF
{"nodes":[{"id":0,"title":"0x42","body":"fcn.00000042();\nadd byte [rax], al\ncmp rax, 0\nje 0x50\n","offset":66,"out_nodes":[1,2]},{"id":1,"title":"0x50","body":"add byte [rax], al\nret\n","offset":80,"out_nodes":[]},{"id":2,"title":"0x4a","body":"add byte [rax], al\nadd byte [rax], al\nadd byte [rax], al\n","offset":74,"out_nodes":[1]}]}
{"nodes":[{"id":0,"title":"0x42","body":"fcn.00000042();\nadd byte [rax], al\ncmp rax, 0x00\njz 0x50\n","offset":66,"out_nodes":[1,2]},{"id":1,"title":"0x50","body":"add byte [rax], al\nret\n","offset":80,"out_nodes":[]},{"id":2,"title":"0x4a","body":"add byte [rax], al\nadd byte [rax], al\nadd byte [rax], al\n","offset":74,"out_nodes":[1]}]}
EOF
RUN

30
test/db/cmd/cmd_ahi
View file

@ -92,7 +92,7 @@ ahi 2
pi 1
EOF
EXPECT=<<EOF
cmp rax, 0xe
cmp rax, 0x0e
cmp rax, 1110b
EOF
RUN
@ -109,7 +109,7 @@ ahi 2
pi 1
EOF
EXPECT=<<EOF
cmp rax, 4
cmp rax, 0x04
cmp rax, 100b
EOF
RUN
@ -288,9 +288,9 @@ ahi 10; pd 1
EOF
EXPECT=<<EOF
true
0x100001000 c7055f440000. mov dword [rip + 0x445f], 0 ; [0x100005469:4]=-1
0x100001000 c7055f440000. mov dword [0x100005469], 0 ; [0x100005469:4]=-1
0x100001000 c7055f440000. mov dword [4294988905], 0 ; [0x100005469:4]=-1
0x100001000 c7055f440000. mov dword [rip+0x445f], 0x00 ; [0x100005469:4]=-1
0x100001000 c7055f440000. mov dword [0x100005469], 0x00 ; [0x100005469:4]=-1
0x100001000 c7055f440000. mov dword [4294988905], 0x00 ; [0x100005469:4]=-1
EOF
RUN
@ -305,8 +305,8 @@ ahi s 1
pi 1
EOF
EXPECT=<<EOF
mov dword [esp + 0x68], 0x72656164
mov dword [esp + 0x68], 'read'
mov dword [esp+0x68], 0x72656164
mov dword [esp+0x68], 'read'
EOF
RUN
@ -339,8 +339,8 @@ e scr.color=1
pd 1
EOF
EXPECT=<<EOF
0x00000000 mov dword [esp + 0x68], 'm0[\x1b'
0x00000000 mov dword [esp + 0x68], 'm0[\x1b'
0x00000000 mov dword [esp+0x68], 'm0[\x1b'
0x00000000 mov dword [esp+0x68], 'm0[\x1b'
EOF
RUN
@ -359,9 +359,9 @@ ahi 10 1
pdq 1
EOF
EXPECT=<<EOF
0x00000000 mov dword [rbp - 0x78], 0xffc643
0x00000000 mov dword [rbp - 120], 0xffc643
0x00000000 mov dword [rbp - 0x78], 16762435
0x00000000 mov dword [rbp-0x78], 0xffc643
0x00000000 mov dword [rbp-120], 0xffc643
0x00000000 mov dword [rbp-0x78], 16762435
EOF
RUN
@ -378,9 +378,9 @@ ahi 10u
pd 1
EOF
EXPECT=<<EOF
0x00000000 cmp eax, 0xffffffff
0x00000000 cmp eax, -1
0x00000000 cmp eax, 4294967295
0x00000000 cmp eax, 0xffffffff ; -1
0x00000000 cmp eax, -1 ; 0xffffffff ; -1
0x00000000 cmp eax, 4294967295 ; 0xffffffff ; -1
EOF
RUN

33
test/db/cmd/cmd_ao
View file

@ -9,15 +9,15 @@ aoj~{}
EOF
EXPECT=<<EOF
address: 0x0
opcode: mov dword [rbp - 0xc], 0
opcode: mov dword [rbp-0x0c], 0x00
esilcost: 12
disasm: mov dword [rbp - 0xc], 0
pseudo: dword [rbp - 0xc] = 0
disasm: mov dword [rbp-0x0c], 0x00
pseudo: dword [rbp-0x0c] = 0x00
mnemonic: mov
description: moves data from src to dst
mask: ffffffffffffff
prefix: 0
id: 460
id: 436
bytes: c745f400000000
val: 0x00000000
disp: 0xfffffffffffffff4
@ -34,9 +34,9 @@ stackop: set
stackptr: 8
[
{
"opcode": "mov dword [rbp - 0xc], 0",
"disasm": "mov dword [rbp - 0xc], 0",
"pseudo": "dword [rbp - 0xc] = 0",
"opcode": "mov dword [rbp-0x0c], 0x00",
"disasm": "mov dword [rbp-0x0c], 0x00",
"pseudo": "dword [rbp-0x0c] = 0x00",
"description": "moves data from src to dst",
"mnemonic": "mov",
"mask": "ffffffffffffff",
@ -64,20 +64,21 @@ stackptr: 8
},
"sign": false,
"prefix": 0,
"id": 460,
"id": 436,
"opex": {
"operands": [
{
"size": 4,
"rw": 2,
"type": "mem",
"segment": "ss",
"base": "rbp",
"scale": 1,
"scale": 0,
"disp": -12
},
{
"size": 4,
"rw": 0,
"rw": 1,
"type": "imm",
"value": 0
}
@ -126,16 +127,18 @@ FILE==
CMDS=<<EOF
e asm.arch=x86
e asm.bits=64
aom 3
aom 4
aom aam
aoma~movnb
aoma~mova
EOF
EXPECT=<<EOF
aam
3
cmova conditional move - above/not below nor equal (cf=0 and zf=0)
cmovae conditional move - above or equal/not below/not carry (cf=0)
movabs absolute data moves
4
cmovnb conditional move - not below/above or equal/not carry (cf=0)
cmovnbe conditional move - not below nor equal/above (cf=0 and zf=0)
fcmovnb fp conditional move - not below (cf=0)
fcmovnbe fp conditional move - not below or equal (cf=0 and zf=0)
movapd move aligned packed double-fp values
movaps move aligned packed single-fp values
vmovapd move aligned packed double-precision floating-point values

88
test/db/cmd/cmd_att
View file

@ -11,26 +11,26 @@ EXPECT=<<EOF
;-- main:
;-- entry0:
;-- func.100001058:
0x100001058 pushq %rbp
0x100001059 movq %rsp, %rbp
0x10000105c pushq %r15
0x10000105e pushq %r14
0x100001060 pushq %r13
0x100001062 pushq %r12
0x100001064 pushq %rbx
0x100001065 subq $0x648, %rsp
0x10000106c movq %rsi, %rbx
0x10000106f movl %edi, %r14d
0x100001072 leaq -0x640(%rbp), %rax
0x100001058 push %rbp
0x100001059 mov %rsp, %rbp
0x10000105c push %r15
0x10000105e push %r14
0x100001060 push %r13
0x100001062 push %r12
0x100001064 push %rbx
0x100001065 sub $0x648, %rsp
0x10000106c mov %rsi, %rbx
0x10000106f mov %edi, %r14d
0x100001072 lea -0x640(%rbp), %rax
0x100001079 movq %rax, -0x648(%rbp)
0x100001080 testl %r14d, %r14d
0x100001083 jg 0x10000108a
0x100001085 callq sym.func.100004401
0x10000108a leaq section.4.__TEXT.__cstring, %rsi
0x100001091 xorl %edi, %edi
0x100001093 callq sym.imp.setlocale
0x100001098 movl $1, %r13d
0x10000109e movl $1, %edi
0x100001080 test %r14d, %r14d
0x100001083 jnle 0x10000108a
0x100001085 call sym.func.100004401
0x10000108a lea section.4.__TEXT.__cstring, %rsi
0x100001091 xor %edi, %edi
0x100001093 call sym.imp.setlocale
0x100001098 mov $0x01, %r13d
0x10000109e mov $0x01, %edi
EOF
RUN
@ -49,26 +49,26 @@ EXPECT=<<EOF
;-- entry0:
;-- func.100001058:
/ int main(int argc, char **argv, char **envp);
| 0x100001058 pushq %rbp
| 0x100001059 movq %rsp, %rbp
| 0x10000105c pushq %r15
| 0x10000105e pushq %r14
| 0x100001060 pushq %r13
| 0x100001062 pushq %r12
| 0x100001064 pushq %rbx
| 0x100001065 subq $0x648, %rsp
| 0x10000106c movq %rsi, %rbx
| 0x10000106f movl %edi, %r14d
| 0x100001072 leaq var_648h, %rax
| 0x100001058 push %rbp
| 0x100001059 mov %rsp, %rbp
| 0x10000105c push %r15
| 0x10000105e push %r14
| 0x100001060 push %r13
| 0x100001062 push %r12
| 0x100001064 push %rbx
| 0x100001065 sub $0x648, %rsp
| 0x10000106c mov %rsi, %rbx
| 0x10000106f mov %edi, %r14d
| 0x100001072 lea var_648h, %rax
| 0x100001079 movq %rax, var_650h
| 0x100001080 testl %r14d, %r14d
| 0x100001083 jg 0x10000108a
| 0x100001085 callq sym.func.100004401
| 0x10000108a leaq section.4.__TEXT.__cstring, %rsi
| 0x100001091 xorl %edi, %edi
| 0x100001093 callq sym.imp.setlocale
| 0x100001098 movl $1, %r13d
| 0x10000109e movl $1, %edi
| 0x100001080 test %r14d, %r14d
| 0x100001083 jnle 0x10000108a
| 0x100001085 call sym.func.100004401
| 0x10000108a lea section.4.__TEXT.__cstring, %rsi
| 0x100001091 xor %edi, %edi
| 0x100001093 call sym.imp.setlocale
| 0x100001098 mov $0x01, %r13d
| 0x10000109e mov $0x01, %edi
EOF
RUN
@ -85,8 +85,8 @@ pdf
EOF
EXPECT=<<EOF
/ int main(int argc, char **argv, char **envp);
| 0x004004a6 pushq %rbp
| 0x004004a7 movq %rsp, %rbp
| 0x004004a6 push %rbp
| 0x004004a7 mov %rsp, %rbp
| 0x004004aa movq var_10h + 0x10, %rax
| 0x004004af movq var_10h, %rax
| 0x004004b4 movq var_10h + 0x10, %rax
@ -96,7 +96,7 @@ EXPECT=<<EOF
| 0x004004c6 movq arg_10h, %rax
| 0x004004ca movq var_20h, %rax
| 0x004004ce leave
\ 0x004004cf retq
\ 0x004004cf ret
EOF
RUN
@ -114,8 +114,8 @@ pdf
EOF
EXPECT=<<EOF
/ int main(int argc, char **argv, char **envp);
| 0x004004a6 pushq %rbp
| 0x004004a7 movq %rsp, %rbp
| 0x004004a6 push %rbp
| 0x004004a7 mov %rsp, %rbp
| 0x004004aa movq var_10h + 0x10(%rsp), %rax
| 0x004004af movq var_10h(%rsp), %rax
| 0x004004b4 movq var_10h + 0x10(%rbp), %rax
@ -125,6 +125,6 @@ EXPECT=<<EOF
| 0x004004c6 movq arg_10h(%rbp), %rax
| 0x004004ca movq var_20h(%rbp), %rax
| 0x004004ce leave
\ 0x004004cf retq
\ 0x004004cf ret
EOF
RUN

212
test/db/cmd/cmd_c
View file

@ -192,63 +192,63 @@ ccd 0x5a8d
EOF
EXPECT=<<EOF
0x00005ae0 endbr64 ! 0x00005a8d add dword [rax], eax
0x00005ae4 xor ebp, ebp ! 0x00005a8f call qword [rip + 0x1c343]
0x00005ae6 mov r9, rdx ! 0x00005a95 lea rcx, [rip + 0x11cbe]
0x00005ae4 xor ebp, ebp ! 0x00005a8f call qword [rip+0x1c343]
0x00005ae6 mov r9, rdx ! 0x00005a95 lea rcx, qword [rip+0x11cbe]
0x00005ae9 pop rsi ! 0x00005a9c mov edx, 0x670
0x00005aea mov rdx, rsp ! 0x00005aa1 lea rsi, [rip + 0x12dcf]
0x00005aed and rsp, 0xfffffffffffffff0 ! 0x00005aa8 lea rdi, [rip + 0x153b9]
0x00005af1 push rax ! 0x00005aaf call qword [rip + 0x1c323]
0x00005af2 push rsp ! 0x00005ab5 lea rcx, [rip + 0x11bfc]
0x00005af3 lea r8, [rip + 0x10c66] ! 0x00005abc mov edx, 0x403
0x00005afa lea rcx, [rip + 0x10bef] ! 0x00005ac1 lea rsi, [rip + 0x12daf]
0x00005b01 lea rdi, [rip - 0x1a98] ! 0x00005ac8 lea rdi, [rip + 0x15339]
0x00005b08 call qword [rip + 0x1c30a] ! 0x00005acf call qword [rip + 0x1c303]
0x00005b0e hlt ! 0x00005ad5 nop word cs:[rax + rax]
0x00005aea mov rdx, rsp ! 0x00005aa1 lea rsi, qword [rip+0x12dcf]
0x00005aed and rsp, 0xfffffffffffffff0 ! 0x00005aa8 lea rdi, qword [rip+0x153b9]
0x00005af1 push rax ! 0x00005aaf call qword [rip+0x1c323]
0x00005af2 push rsp ! 0x00005ab5 lea rcx, qword [rip+0x11bfc]
0x00005af3 lea r8, qword [rip+0x10c66] ! 0x00005abc mov edx, 0x403
0x00005afa lea rcx, qword [rip+0x10bef] ! 0x00005ac1 lea rsi, qword [rip+0x12daf]
0x00005b01 lea rdi, qword [rip-0x1a98] ! 0x00005ac8 lea rdi, qword [rip+0x15339]
0x00005b08 call qword [rip+0x1c30a] ! 0x00005acf call qword [rip+0x1c303]
0x00005b0e hlt ! 0x00005ad5 nop word [rax+rax*1], ax
0x00005b0f nop = 0x00005adf nop
0x00005b10 lea rdi, [rip + 0x1c751] ! 0x00005ae0 endbr64
0x00005b17 lea rax, [rip + 0x1c74a] ! 0x00005ae4 xor ebp, ebp
0x00005b10 lea rdi, qword [rip+0x1c751] ! 0x00005ae0 endbr64
0x00005b17 lea rax, qword [rip+0x1c74a] ! 0x00005ae4 xor ebp, ebp
0x00005b1e cmp rax, rdi ! 0x00005ae6 mov r9, rdx
0x00005b21 je 0x5b38 ! 0x00005ae9 pop rsi
0x00005b23 mov rax, qword [rip + 0x1c196] ! 0x00005aea mov rdx, rsp
0x00005b21 jz 0x5b38 ! 0x00005ae9 pop rsi
0x00005b23 mov rax, qword [rip+0x1c196] ! 0x00005aea mov rdx, rsp
0x00005b2a test rax, rax ! 0x00005aed and rsp, 0xfffffffffffffff0
0x00005b2d je 0x5b38 ! 0x00005af1 push rax
0x00005b2d jz 0x5b38 ! 0x00005af1 push rax
0x00005b2f jmp rax ! 0x00005af2 push rsp
0x00005b31 nop dword [rax] ! 0x00005af3 lea r8, [rip + 0x10c66]
0x00005b38 ret ! 0x00005afa lea rcx, [rip + 0x10bef]
0x00005b39 nop dword [rax] ! 0x00005b01 lea rdi, [rip - 0x1a98]
0x00005b40 lea rdi, [rip + 0x1c721] ! 0x00005b08 call qword [rip + 0x1c30a]
0x00005b47 lea rsi, [rip + 0x1c71a] ! 0x00005b0e hlt
0x00005b31 nop dword [rax], eax ! 0x00005af3 lea r8, qword [rip+0x10c66]
0x00005b38 ret ! 0x00005afa lea rcx, qword [rip+0x10bef]
0x00005b39 nop dword [rax], eax ! 0x00005b01 lea rdi, qword [rip-0x1a98]
0x00005b40 lea rdi, qword [rip+0x1c721] ! 0x00005b08 call qword [rip+0x1c30a]
0x00005b47 lea rsi, qword [rip+0x1c71a] ! 0x00005b0e hlt
0x00005b4e sub rsi, rdi ! 0x00005b0f nop
0x00005b51 sar rsi, 3 ! 0x00005b10 lea rdi, [rip + 0x1c751]
0x00005b55 mov rax, rsi ! 0x00005b17 lea rax, [rip + 0x1c74a]
0x00005b51 sar rsi, 0x03 ! 0x00005b10 lea rdi, qword [rip+0x1c751]
0x00005b55 mov rax, rsi ! 0x00005b17 lea rax, qword [rip+0x1c74a]
0x00005b58 shr rax, 0x3f ! 0x00005b1e cmp rax, rdi
0x00005b5c add rsi, rax ! 0x00005b21 je 0x5b20
0x00005b5f sar rsi, 1 ! 0x00005b23 mov rax, qword [rip + 0x1c196]
0x00005b62 je 0x5b78 ! 0x00005b2a test rax, rax
0x00005b64 mov rax, qword [rip + 0x1c43d] ! 0x00005b2d je 0x5b1c
0x00005b5c add rsi, rax ! 0x00005b21 jz 0x5b20
0x00005b5f sar rsi, 0x01 ! 0x00005b23 mov rax, qword [rip+0x1c196]
0x00005b62 jz 0x5b78 ! 0x00005b2a test rax, rax
0x00005b64 mov rax, qword [rip+0x1c43d] ! 0x00005b2d jz 0x5b1c
0x00005b6b test rax, rax ! 0x00005b2f jmp rax
0x00005b6e je 0x5b78 ! 0x00005b31 nop dword [rax]
0x00005b6e jz 0x5b78 ! 0x00005b31 nop dword [rax], eax
0x00005b70 jmp rax ! 0x00005b38 ret
0x00005b72 nop word [rax + rax] ! 0x00005b39 nop dword [rax]
0x00005b78 ret ! 0x00005b40 lea rdi, [rip + 0x1c721]
0x00005b79 nop dword [rax] ! 0x00005b47 lea rsi, [rip + 0x1c71a]
0x00005b72 nop word [rax+rax*1], ax ! 0x00005b39 nop dword [rax], eax
0x00005b78 ret ! 0x00005b40 lea rdi, qword [rip+0x1c721]
0x00005b79 nop dword [rax], eax ! 0x00005b47 lea rsi, qword [rip+0x1c71a]
0x00005b80 endbr64 ! 0x00005b4e sub rsi, rdi
0x00005b84 cmp byte [rip + 0x1c73d], 0 ! 0x00005b51 sar rsi, 3
0x00005b8b jne 0x5bc0 ! 0x00005b55 mov rax, rsi
0x00005b84 cmp byte [rip+0x1c73d], 0x00 ! 0x00005b51 sar rsi, 0x03
0x00005b8b jnz 0x5bc0 ! 0x00005b55 mov rax, rsi
0x00005b8d push rbp ! 0x00005b58 shr rax, 0x3f
0x00005b8e cmp qword [rip + 0x1c432], 0 ! 0x00005b5c add rsi, rax
0x00005b96 mov rbp, rsp ! 0x00005b5f sar rsi, 1
0x00005b99 je 0x5ba8 ! 0x00005b62 je 0x5b5c
0x00005b9b mov rdi, qword [rip + 0x1c466] ! 0x00005b64 mov rax, qword [rip + 0x1c43d]
0x00005ba2 call qword [rip + 0x1c420] ! 0x00005b6b test rax, rax
0x00005ba8 call 0x5b10 ! 0x00005b6e je 0x5b5f
0x00005bad mov byte [rip + 0x1c714], 1 ! 0x00005b70 jmp rax
0x00005bb4 pop rbp ! 0x00005b72 nop word [rax + rax]
0x00005b8e cmp qword [rip+0x1c432], 0x00 ! 0x00005b5c add rsi, rax
0x00005b96 mov rbp, rsp ! 0x00005b5f sar rsi, 0x01
0x00005b99 jz 0x5ba8 ! 0x00005b62 jz 0x5b5c
0x00005b9b mov rdi, qword [rip+0x1c466] ! 0x00005b64 mov rax, qword [rip+0x1c43d]
0x00005ba2 call qword [rip+0x1c420] ! 0x00005b6b test rax, rax
0x00005ba8 call 0x5b10 ! 0x00005b6e jz 0x5b5f
0x00005bad mov byte [rip+0x1c714], 0x01 ! 0x00005b70 jmp rax
0x00005bb4 pop rbp ! 0x00005b72 nop word [rax+rax*1], ax
0x00005bb5 ret = 0x00005b78 ret
0x00005bb6 nop word cs:[rax + rax] ! 0x00005b79 nop dword [rax]
0x00005bb6 nop word [rax+rax*1], ax ! 0x00005b79 nop dword [rax], eax
0x00005bc0 ret ! 0x00005b80 endbr64
0x00005bc1 nop word cs:[rax + rax] ! 0x00005b84 cmp byte [rip + 0x1c73d], 0
0x00005bcc nop dword [rax] ! 0x00005b8b jne 0x5bae
0x00005bc1 nop word [rax+rax*1], ax ! 0x00005b84 cmp byte [rip+0x1c73d], 0x00
0x00005bcc nop dword [rax], eax ! 0x00005b8b jnz 0x5bae
EOF
RUN
@ -1111,117 +1111,117 @@ EXPECT=<<EOF
-0x00005ae0 endbr64
+0x00005a8d add dword [rax], eax
-0x00005ae4 xor ebp, ebp
+0x00005a8f call qword [rip + 0x1c343]
+0x00005a8f call qword [rip+0x1c343]
-0x00005ae6 mov r9, rdx
+0x00005a95 lea rcx, [rip + 0x11cbe]
+0x00005a95 lea rcx, qword [rip+0x11cbe]
-0x00005ae9 pop rsi
+0x00005a9c mov edx, 0x670
-0x00005aea mov rdx, rsp
+0x00005aa1 lea rsi, [rip + 0x12dcf]
+0x00005aa1 lea rsi, qword [rip+0x12dcf]
-0x00005aed and rsp, 0xfffffffffffffff0
+0x00005aa8 lea rdi, [rip + 0x153b9]
+0x00005aa8 lea rdi, qword [rip+0x153b9]
-0x00005af1 push rax
+0x00005aaf call qword [rip + 0x1c323]
+0x00005aaf call qword [rip+0x1c323]
-0x00005af2 push rsp
+0x00005ab5 lea rcx, [rip + 0x11bfc]
-0x00005af3 lea r8, [rip + 0x10c66]
+0x00005ab5 lea rcx, qword [rip+0x11bfc]
-0x00005af3 lea r8, qword [rip+0x10c66]
+0x00005abc mov edx, 0x403
-0x00005afa lea rcx, [rip + 0x10bef]
+0x00005ac1 lea rsi, [rip + 0x12daf]
-0x00005b01 lea rdi, [rip - 0x1a98]
+0x00005ac8 lea rdi, [rip + 0x15339]
-0x00005b08 call qword [rip + 0x1c30a]
+0x00005acf call qword [rip + 0x1c303]
-0x00005afa lea rcx, qword [rip+0x10bef]
+0x00005ac1 lea rsi, qword [rip+0x12daf]
-0x00005b01 lea rdi, qword [rip-0x1a98]
+0x00005ac8 lea rdi, qword [rip+0x15339]
-0x00005b08 call qword [rip+0x1c30a]
+0x00005acf call qword [rip+0x1c303]
-0x00005b0e hlt
+0x00005ad5 nop word cs:[rax + rax]
+0x00005ad5 nop word [rax+rax*1], ax
0x00005b0f nop
-0x00005b10 lea rdi, [rip + 0x1c751]
-0x00005b10 lea rdi, qword [rip+0x1c751]
+0x00005ae0 endbr64
-0x00005b17 lea rax, [rip + 0x1c74a]
-0x00005b17 lea rax, qword [rip+0x1c74a]
+0x00005ae4 xor ebp, ebp
-0x00005b1e cmp rax, rdi
+0x00005ae6 mov r9, rdx
-0x00005b21 je 0x5b38
-0x00005b21 jz 0x5b38
+0x00005ae9 pop rsi
-0x00005b23 mov rax, qword [rip + 0x1c196]
-0x00005b23 mov rax, qword [rip+0x1c196]
+0x00005aea mov rdx, rsp
-0x00005b2a test rax, rax
+0x00005aed and rsp, 0xfffffffffffffff0
-0x00005b2d je 0x5b38
-0x00005b2d jz 0x5b38
+0x00005af1 push rax
-0x00005b2f jmp rax
+0x00005af2 push rsp
-0x00005b31 nop dword [rax]
+0x00005af3 lea r8, [rip + 0x10c66]
-0x00005b31 nop dword [rax], eax
+0x00005af3 lea r8, qword [rip+0x10c66]
-0x00005b38 ret
+0x00005afa lea rcx, [rip + 0x10bef]
-0x00005b39 nop dword [rax]
+0x00005b01 lea rdi, [rip - 0x1a98]
-0x00005b40 lea rdi, [rip + 0x1c721]
+0x00005b08 call qword [rip + 0x1c30a]
-0x00005b47 lea rsi, [rip + 0x1c71a]
+0x00005afa lea rcx, qword [rip+0x10bef]
-0x00005b39 nop dword [rax], eax
+0x00005b01 lea rdi, qword [rip-0x1a98]
-0x00005b40 lea rdi, qword [rip+0x1c721]
+0x00005b08 call qword [rip+0x1c30a]
-0x00005b47 lea rsi, qword [rip+0x1c71a]
+0x00005b0e hlt
-0x00005b4e sub rsi, rdi
+0x00005b0f nop
-0x00005b51 sar rsi, 3
+0x00005b10 lea rdi, [rip + 0x1c751]
-0x00005b51 sar rsi, 0x03
+0x00005b10 lea rdi, qword [rip+0x1c751]
-0x00005b55 mov rax, rsi
+0x00005b17 lea rax, [rip + 0x1c74a]
+0x00005b17 lea rax, qword [rip+0x1c74a]
-0x00005b58 shr rax, 0x3f
+0x00005b1e cmp rax, rdi
-0x00005b5c add rsi, rax
+0x00005b21 je 0x5b20
-0x00005b5f sar rsi, 1
+0x00005b23 mov rax, qword [rip + 0x1c196]
-0x00005b62 je 0x5b78
+0x00005b21 jz 0x5b20
-0x00005b5f sar rsi, 0x01
+0x00005b23 mov rax, qword [rip+0x1c196]
-0x00005b62 jz 0x5b78
+0x00005b2a test rax, rax
-0x00005b64 mov rax, qword [rip + 0x1c43d]
+0x00005b2d je 0x5b1c
-0x00005b64 mov rax, qword [rip+0x1c43d]
+0x00005b2d jz 0x5b1c
-0x00005b6b test rax, rax
+0x00005b2f jmp rax
-0x00005b6e je 0x5b78
+0x00005b31 nop dword [rax]
-0x00005b6e jz 0x5b78
+0x00005b31 nop dword [rax], eax
-0x00005b70 jmp rax
+0x00005b38 ret
-0x00005b72 nop word [rax + rax]
+0x00005b39 nop dword [rax]
-0x00005b72 nop word [rax+rax*1], ax
+0x00005b39 nop dword [rax], eax
-0x00005b78 ret
+0x00005b40 lea rdi, [rip + 0x1c721]
-0x00005b79 nop dword [rax]
+0x00005b47 lea rsi, [rip + 0x1c71a]
+0x00005b40 lea rdi, qword [rip+0x1c721]
-0x00005b79 nop dword [rax], eax
+0x00005b47 lea rsi, qword [rip+0x1c71a]
-0x00005b80 endbr64
+0x00005b4e sub rsi, rdi
-0x00005b84 cmp byte [rip + 0x1c73d], 0
+0x00005b51 sar rsi, 3
-0x00005b8b jne 0x5bc0
-0x00005b84 cmp byte [rip+0x1c73d], 0x00
+0x00005b51 sar rsi, 0x03
-0x00005b8b jnz 0x5bc0
+0x00005b55 mov rax, rsi
-0x00005b8d push rbp
+0x00005b58 shr rax, 0x3f
-0x00005b8e cmp qword [rip + 0x1c432], 0
-0x00005b8e cmp qword [rip+0x1c432], 0x00
+0x00005b5c add rsi, rax
-0x00005b96 mov rbp, rsp
+0x00005b5f sar rsi, 1
-0x00005b99 je 0x5ba8
+0x00005b62 je 0x5b5c
-0x00005b9b mov rdi, qword [rip + 0x1c466]
+0x00005b64 mov rax, qword [rip + 0x1c43d]
-0x00005ba2 call qword [rip + 0x1c420]
+0x00005b5f sar rsi, 0x01
-0x00005b99 jz 0x5ba8
+0x00005b62 jz 0x5b5c
-0x00005b9b mov rdi, qword [rip+0x1c466]
+0x00005b64 mov rax, qword [rip+0x1c43d]
-0x00005ba2 call qword [rip+0x1c420]
+0x00005b6b test rax, rax
-0x00005ba8 call 0x5b10
+0x00005b6e je 0x5b5f
-0x00005bad mov byte [rip + 0x1c714], 1
+0x00005b6e jz 0x5b5f
-0x00005bad mov byte [rip+0x1c714], 0x01
+0x00005b70 jmp rax
-0x00005bb4 pop rbp
+0x00005b72 nop word [rax + rax]
+0x00005b72 nop word [rax+rax*1], ax
0x00005bb5 ret
-0x00005bb6 nop word cs:[rax + rax]
+0x00005b79 nop dword [rax]
-0x00005bb6 nop word [rax+rax*1], ax
+0x00005b79 nop dword [rax], eax
-0x00005bc0 ret
+0x00005b80 endbr64
-0x00005bc1 nop word cs:[rax + rax]
+0x00005b84 cmp byte [rip + 0x1c73d], 0
-0x00005bcc nop dword [rax]
+0x00005b8b jne 0x5bae
-0x00005bc1 nop word [rax+rax*1], ax
+0x00005b84 cmp byte [rip+0x1c73d], 0x00
-0x00005bcc nop dword [rax], eax
+0x00005b8b jnz 0x5bae
EOF
RUN

2
test/db/cmd/cmd_coverage
View file

@ -6,7 +6,7 @@ aai
EOF
EXPECT=<<EOF
functions: 76
xrefs: 179
xrefs: 177
calls: 130
strings: 1
symbols: 102

2
test/db/cmd/cmd_disassembly
View file

@ -151,7 +151,7 @@ EOF
EXPECT=<<EOF
movs r0, r0
movs r0, r0
add byte [bx + si], al
add byte [bx+si*1], al
EOF
RUN

2
test/db/cmd/cmd_eval
View file

@ -131,7 +131,7 @@ e asm.syntax=masm
pi 1
EOF
EXPECT=<<EOF
jmp 10h
jmp $+10h
EOF
RUN

155
test/db/cmd/cmd_list
View file

File diff suppressed because one or more lines are too long

2
test/db/cmd/cmd_pad
View file

@ -37,7 +37,7 @@ push 0x64777373
push 0x61702f2f
push 0x6374652f
mov ecx, esp
mov al, 0xb
mov al, 0x0b
push edx
push ecx
push ebx

269
test/db/cmd/cmd_pd
View file

@ -13,13 +13,13 @@ e asm.sub.rel=0
pd 1
EOF
EXPECT=<<EOF
0x100001232 c70594420000. mov dword [rip + 0x4294], 0x50 ; 'P' ; section.10.__DATA.__data
0x100001232 c70594420000. mov dword [rip+0x4294], 0x50 ; 'P' ; section.10.__DATA.__data
; [0x1000054d0:4]=80 ; U"P."
0x100001232 c70594420000. mov dword [section.10.__DATA.__data], 0x50 ; 'P'
; [0x1000054d0:4]=80 ; U"P."
0x100001232 c70594420000. mov dword [fin.dus], 0x50 ; 'P'
; [0x1000054d0:4]=80 ; U"P."
0x100001232 c70594420000. mov dword [rip + 0x4294], 0x50 ; 'P' ; fin.dus
0x100001232 c70594420000. mov dword [rip+0x4294], 0x50 ; 'P' ; fin.dus
; [0x1000054d0:4]=80 ; U"P."
EOF
RUN
@ -164,7 +164,7 @@ e asm.lines.bb=0
pd 1
EOF
EXPECT=<<EOF
0x00000000 b8ffffffff mov eax, 0xffffffff ; -1
0x00000000 b8ffffffff mov eax, 0xffffffff
EOF
RUN
@ -322,7 +322,7 @@ wx c6852fffffff61
pd 1
EOF
EXPECT=<<EOF
0x00000000 c6852fffffff. mov byte [ebp - 0xd1], 0x61 ; 'a'
0x00000000 c6852fffffff. mov byte [ebp-0xd1], 0x61 ; 'a'
EOF
RUN
@ -437,10 +437,10 @@ EXPECT=<<EOF
and rsp, 0xfffffffffffffff0
push rax
push rsp
lea r8, [0x000011e0]
lea rcx, [0x00001170]
lea r8, qword [0x000011e0]
lea rcx, qword [0x00001170]
; 0xd7c
lea rdi, main
lea rdi, qword main
EOF
RUN
@ -577,17 +577,17 @@ e asm.nbytes=6
pd 3
EOF
EXPECT=<<EOF
0x00000000 488d85c0f9ff. lea rax, [rbp - 0x640]
0x00000007 488985b8f9ff. mov qword [rbp - 0x648], rax
0x00000000 488d85c0f9ff. lea rax, qword [rbp-0x640]
0x00000007 488985b8f9ff. mov qword [rbp-0x648], rax
0x0000000e 4585f6 test r14d, r14d
0x00000000 488d85c0f9ffff lea rax, [rbp - 0x640]
0x00000007 488985b8f9ffff mov qword [rbp - 0x648], rax
0x00000000 488d85c0f9ffff lea rax, qword [rbp-0x640]
0x00000007 488985b8f9ffff mov qword [rbp-0x648], rax
0x0000000e 4585f6 test r14d, r14d
0x00000000 488d85c0f9ffff lea rax, [rbp - 0x640]
0x00000007 488985b8f9ffff mov qword [rbp - 0x648], rax
0x00000000 488d85c0f9ffff lea rax, qword [rbp-0x640]
0x00000007 488985b8f9ffff mov qword [rbp-0x648], rax
0x0000000e 4585f6 test r14d, r14d
0x00000000 488d85c0f9ff. lea rax, [rbp - 0x640]
0x00000007 488985b8f9ff. mov qword [rbp - 0x648], rax
0x00000000 488d85c0f9ff. lea rax, qword [rbp-0x640]
0x00000007 488985b8f9ff. mov qword [rbp-0x648], rax
0x0000000e 4585f6 test r14d, r14d
EOF
RUN
@ -609,8 +609,8 @@ e asm.sub.rel=true
pd 1
EOF
EXPECT=<<EOF
0x00400000 488d05020000. lea rax, [rip + 2]
0x00400000 488d05020000. lea rax, [0x00400009]
0x00400000 488d05020000. lea rax, qword [rip+0x02]
0x00400000 488d05020000. lea rax, qword [0x00400009]
EOF
RUN
@ -724,14 +724,14 @@ EXPECT=<<EOF
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
| 0x004017c6 3d00100000 cmp eax, 0x1000
\ ,=< 0x004017cb 7210 jb 0x4017dd
fcn2.0x004017c0();
0x004017c0 51 push ecx
0x004017c1 89e1 mov ecx, esp
0x004017c3 83c108 add ecx, 8
0x004017c3 83c108 add ecx, 0x08
0x004017c6 3d00100000 cmp eax, 0x1000
,=< 0x004017cb 7210 jb 0x4017dd
EOF
@ -755,14 +755,14 @@ EXPECT=<<EOF
/ fcn2.0x004017c0();
| 0x004017c0 51 push ecx
| 0x004017c1 89e1 mov ecx, esp
| 0x004017c3 83c108 add ecx, 8
| 0x004017c3 83c108 add ecx, 0x08
| 0x004017c6 3d00100000 cmp eax, 0x1000
\ ,=< 0x004017cb 7210 jb 0x4017dd
13: fcn2.0x004017c0();
0x004017c0 51 push ecx
0x004017c1 89e1 mov ecx, esp
0x004017c3 83c108 add ecx, 8
0x004017c3 83c108 add ecx, 0x08
0x004017c6 3d00100000 cmp eax, 0x1000
,=< 0x004017cb 7210 jb 0x4017dd
EOF
@ -787,8 +787,8 @@ pd 1 @ 0x140001034
pd 1 @ 0x140001070
EOF
EXPECT=<<EOF
0x140001034 488d05495001. lea rax, [0x140016084] ; "\r"
0x140001070 488d053d5001. lea rax, [0x1400160b4] ; "a"
0x140001034 488d05495001. lea rax, qword [0x140016084] ; "\r"
0x140001070 488d053d5001. lea rax, qword [0x1400160b4] ; "a"
EOF
RUN
@ -813,10 +813,10 @@ e asm.cmt.right=false
pd 1 @ 0x0001145f
EOF
EXPECT=<<EOF
0x0001145f 488d3d72a100. lea rdi, str.A_NULL_argv_0__was_passed_through_an_exec_system_call. ; 0x1b5d8 ; "A NULL argv[0] was passed through an exec system call.\n"
0x0001145f 488d3d72a100. lea rdi, qword str.A_NULL_argv_0__was_passed_through_an_exec_system_call. ; 0x1b5d8 ; "A NULL argv[0] was passed through an exec system call.\n"
; 0x1b5d8
; "A NULL argv[0] was passed through an exec system call.\n"
0x0001145f 488d3d72a100. lea rdi, str.A_NULL_argv_0__was_passed_through_an_exec_system_call.
0x0001145f 488d3d72a100. lea rdi, qword str.A_NULL_argv_0__was_passed_through_an_exec_system_call.
EOF
RUN
@ -832,10 +832,10 @@ e asm.cmt.right=false
pd 1 @ 0x0001145f
EOF
EXPECT=<<EOF
0x0001145f 488d3d72a100. lea rdi, [NULL_error] ; 0x1b5d8 ; "A NULL argv[0] was passed through an exec system call.\n"
0x0001145f 488d3d72a100. lea rdi, qword [NULL_error] ; 0x1b5d8 ; "A NULL argv[0] was passed through an exec system call.\n"
; 0x1b5d8
; "A NULL argv[0] was passed through an exec system call.\n"
0x0001145f 488d3d72a100. lea rdi, [NULL_error]
0x0001145f 488d3d72a100. lea rdi, qword [NULL_error]
EOF
RUN
@ -921,8 +921,8 @@ e asm.sub.names=false
pd 1 @ 0x0001145f
EOF
EXPECT=<<EOF
0x0001145f lea rdi, str.A_NULL_argv_0__was_passed_through_an_exec_system_call.
0x0001145f lea rdi, [0x0001b5d8]
0x0001145f lea rdi, qword str.A_NULL_argv_0__was_passed_through_an_exec_system_call.
0x0001145f lea rdi, qword [0x0001b5d8]
EOF
RUN
@ -941,20 +941,20 @@ pd 1 @ 0x140001010
pd 1 @ 0x14000101c
EOF
EXPECT=<<EOF
0x140001004 488d05f54f01. lea rax, str.ANSI_esc:___33m ; section..data
0x140001004 488d05f54f01. lea rax, qword str.ANSI_esc:___33m ; section..data
; 0x140016000 ; "\tANSI\esc: \e[33m\r\n"
0x140001010 488d05015001. lea rax, str.wide_esc:___0m ; 0x140016018 ; u"\twide\esc: \e[0m¡\r\n"
0x14000101c 488d051d5001. lea rax, str.wide__in_Arabic: ; 0x140016040 ; u"\"wide\" in Arabic: واسع"
0x140001010 488d05015001. lea rax, qword str.wide_esc:___0m ; 0x140016018 ; u"\twide\esc: \e[0m¡\r\n"
0x14000101c 488d051d5001. lea rax, qword str.wide__in_Arabic: ; 0x140016040 ; u"\"wide\" in Arabic: واسع"
; section..data
; 0x140016000
; "\tANSI\esc: \e[33m\r\n"
0x140001004 488d05f54f01. lea rax, str.ANSI_esc:___33m
0x140001004 488d05f54f01. lea rax, qword str.ANSI_esc:___33m
; 0x140016018
; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, str.wide_esc:___0m
0x140001010 488d05015001. lea rax, qword str.wide_esc:___0m
; 0x140016040
; u"\"wide\" in Arabic: واسع"
0x14000101c 488d051d5001. lea rax, str.wide__in_Arabic:
0x14000101c 488d051d5001. lea rax, qword str.wide__in_Arabic:
EOF
RUN
@ -965,7 +965,7 @@ e asm.bytes=true
pd 1 @ 0x140001040
EOF
EXPECT=<<EOF
0x140001040 488d05415001. lea rax, str.r2 ; 0x140016088 ; u"r2 ገ⏴⏴"
0x140001040 488d05415001. lea rax, qword str.r2 ; 0x140016088 ; u"r2 ገ⏴⏴"
EOF
RUN
@ -1035,8 +1035,8 @@ e str.encoding=utf8
pd 1 @ 0x140001058
EOF
EXPECT=<<EOF
0x140001058 488d05415001. lea rax, [0x1400160a0] ; "latin1 gate: \xce\xbb\xab\xce"
0x140001058 488d05415001. lea rax, [0x1400160a0] ; "latin1 gate: λ\xab\xce"
0x140001058 488d05415001. lea rax, qword [0x1400160a0] ; "latin1 gate: \xce\xbb\xab\xce"
0x140001058 488d05415001. lea rax, qword [0x1400160a0] ; "latin1 gate: λ\xab\xce"
EOF
RUN
@ -1114,8 +1114,8 @@ e str.encoding=utf16le
pd 1 @ 0x14000104c
EOF
EXPECT=<<EOF
0x14000104c 488d05455001. lea rax, [0x140016098] ; "@"
0x14000104c 488d05455001. lea rax, [0x140016098] ; u"@<40>\x01\xd8"
0x14000104c 488d05455001. lea rax, qword [0x140016098] ; "@"
0x14000104c 488d05455001. lea rax, qword [0x140016098] ; u"@<40>\x01\xd8"
EOF
RUN
@ -1206,16 +1206,16 @@ e asm.cmt.right=false
pd 1 @ 0x140001010
EOF
EXPECT=<<EOF
0x140001010 488d05015001. lea rax, [0x140016018] ; u"\twide\esc: \e[0m¡\r\n"
0x140001028 488d05415001. lea rax, [0x140016070] ; str.Formfeed_at_start
0x140001010 488d05015001. lea rax, qword [0x140016018] ; u"\twide\esc: \e[0m¡\r\n"
0x140001028 488d05415001. lea rax, qword [0x140016070] ; str.Formfeed_at_start
; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, [0x140016018]
0x140001010 488d05015001. lea rax, qword [0x140016018]
; str.Formfeed_at_start
0x140001028 488d05415001. lea rax, [0x140016070]
0x140001010 488d05015001. lea rax, [0x140016018] ; str.wide ; u"\twide\esc: \e[0m¡\r\n"
0x140001028 488d05415001. lea rax, qword [0x140016070]
0x140001010 488d05015001. lea rax, qword [0x140016018] ; str.wide ; u"\twide\esc: \e[0m¡\r\n"
; str.wide
; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, [0x140016018]
0x140001010 488d05015001. lea rax, qword [0x140016018]
EOF
RUN
@ -1232,10 +1232,10 @@ e asm.cmt.right=false
pd 1 @ 0x140001010
EOF
EXPECT=<<EOF
0x140001010 488d05015001. lea rax, [0x140016018] ; str.wide_esc:___0m ; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, qword [0x140016018] ; str.wide_esc:___0m ; u"\twide\esc: \e[0m¡\r\n"
; str.wide_esc:___0m
; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, [0x140016018]
0x140001010 488d05015001. lea rax, qword [0x140016018]
EOF
RUN
@ -1287,9 +1287,9 @@ e asm.cmt.off=nodup
pd 1 @ 0x140001010
EOF
EXPECT=<<EOF
0x140001010 488d05015001. lea rax, str.wide_esc:___0m ; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, [0x140016018] ; 0x140016018 ; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, [0x140016018] ; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, qword str.wide_esc:___0m ; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, qword [0x140016018] ; 0x140016018 ; u"\twide\esc: \e[0m¡\r\n"
0x140001010 488d05015001. lea rax, qword [0x140016018] ; u"\twide\esc: \e[0m¡\r\n"
EOF
RUN
@ -1324,12 +1324,12 @@ pdf
EOF
EXPECT=<<EOF
/ int main(int argc, char **argv, char **envp);
| 0x0000061a pushq %rbp
| 0x0000061b movq %rsp, %rbp
| 0x0000061e movl $1, obj.sa
| 0x00000628 movl $0, %eax
| 0x0000062d popq %rbp
\ 0x0000062e retq
| 0x0000061a push %rbp
| 0x0000061b mov %rsp, %rbp
| 0x0000061e movl $0x01, obj.sa
| 0x00000628 mov $0x00, %eax
| 0x0000062d pop %rbp
\ 0x0000062e ret
EOF
RUN
@ -1351,7 +1351,7 @@ e asm.bytes=false
pd 1 @ 0x004004df
EOF
EXPECT=<<EOF
0x004004df mov qword [rbp - 8], str.Hello_World ; 0x4005a0 ; u"\U0000feffHello World\U0000feff\n"
0x004004df mov qword [rbp-0x08], str.Hello_World ; 0x4005a0 ; u"\U0000feffHello World\U0000feff\n"
EOF
RUN
@ -1689,10 +1689,10 @@ pd 1 @B:-1
pd 1 @B:-2
EOF
EXPECT=<<EOF
0x00000000 83f803 cmp eax, 3
0x00000003 740e je 0x13
0x00000003 740e je 0x13
0x00000000 83f803 cmp eax, 3
0x00000000 83f803 cmp eax, 0x03
0x00000003 740e jz 0x13
0x00000003 740e jz 0x13
0x00000000 83f803 cmp eax, 0x03
EOF
RUN
@ -1710,19 +1710,19 @@ s 0x0040294b
pd 10
EOF
EXPECT=<<EOF
| 0x0040294b c6059ea72100. mov byte [0x0061d0f0], 0
| 0x00402952 83f802 cmp eax, 2
| ,=< 0x00402955 0f8483080000 je 0x4031de
| 0x0040294b c6059ea72100. mov byte [0x0061d0f0], 0x00
| 0x00402952 83f802 cmp eax, 0x02
| ,=< 0x00402955 0f8483080000 jz 0x4031de
| | |
| | 0x0040295b 83f803 cmp eax, 3
| ,==< 0x0040295e 742f je 0x40298f
| | 0x0040295b 83f803 cmp eax, 0x03
| ,==< 0x0040295e 742f jz 0x40298f
| || |
| || 0x00402960 83e801 sub eax, 1
| ,===< 0x00402963 7405 je 0x40296a
| || 0x00402960 83e801 sub eax, 0x01
| ,===< 0x00402963 7405 jz 0x40296a
| ||| |
| ||| 0x00402965 e8b6f8ffff call sym.imp.abort
| ||| |
| `---> 0x0040296a bf01000000 mov edi, 1
| `---> 0x0040296a bf01000000 mov edi, 0x01
| || 0x0040296f e80cf9ffff call sym.imp.isatty
EOF
RUN
@ -1824,17 +1824,17 @@ e emu.str.inv=false
pd 1 @ 0x161d
EOF
EXPECT=<<EOF
0x0000161d lea eax, [esi - abcdefghi] ; 0x21f7 ; "abcdefghi" ; "\n Blue Pill" str.Blue_Pill
0x0000161d lea eax, [esi - abcdefghi] ; 0x21f7 ; "abcdefghi" ; "\n Blue Pill" str.Blue_Pill
0x0000161d lea eax, dword [esi-abcdefghi] ; 0x21f7 ; "abcdefghi" ; "\n Blue Pill" str.Blue_Pill
0x0000161d lea eax, dword [esi-abcdefghi] ; 0x21f7 ; "abcdefghi" ; "\n Blue Pill" str.Blue_Pill
; 0x21f7
; "abcdefghi"
 ; "\n Blue Pill" str.Blue_Pill
 0x0000161d lea eax, [esi - abcdefghi]
 0x0000161d lea eax, dword [esi-abcdefghi]
; 0x21f7
; "abcdefghi"
 ; "\n Blue Pill" str.Blue_Pill
 0x0000161d lea eax, [esi - abcdefghi]
 0x0000161d lea eax, dword [esi-abcdefghi]
EOF
RUN
@ -1851,8 +1851,8 @@ pd 1 @ 0x161d
pd 1 @ 0x1447
EOF
EXPECT=<<EOF
0x0000161d lea eax, [esi - 0x21f7] ; "\n Blue Pill" str.Blue_Pill
0x0000161d lea eax, [esi - 0x21f7] ; "\n Blue Pill"
0x0000161d lea eax, dword [esi-0x21f7] ; "\n Blue Pill" str.Blue_Pill
0x0000161d lea eax, dword [esi-0x21f7] ; "\n Blue Pill"
0x00001447 add esi, 0x2bb9 ; section..got.plt
EOF
RUN
@ -1955,18 +1955,19 @@ s 0
pd 1 @ 0x1457
EOF
EXPECT=<<EOF
0x00001457 8d8689ddffff lea eax, [esi - 0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, dword [esi-0x2277] ; " Take the Red Pill!! \n"
0x0000145d 50 push eax
0x0000145e 8b86f0ffffff mov eax, dword [esi - 0x10]
0x00001457 8d8689ddffff lea eax, [esi - 0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, [esi - 0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, [esi - 0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, [esi - 0x2277] ; " Take the Red Pill!! \n"
0x0000145e 8b86f0ffffff mov eax, dword [esi-0x10]
0x00001457 8d8689ddffff lea eax, dword [esi-0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, dword [esi-0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, dword [esi-0x2277] ; " Take the Red Pill!! \n"
0x00001457 8d8689ddffff lea eax, dword [esi-0x2277] ; " Take the Red Pill!! \n"
EOF
RUN
NAME=pdJ with backslashes, quotation marks, str.escbslash and str.encoding
FILE==
NAME=pdJ with backslashes, quotation marks, str.escbslash and str.search.encoding
FILE=malloc://1024k
CMDS=<<EOF
e io.cache=true
e asm.arch=x86
@ -2082,13 +2083,13 @@ EXPECT=<<EOF
"opcode": "push rbx",
"opcode": "push rax",
"opcode": "mov ebx, edi",
"opcode": "cmp ebx, 2",
"opcode": "cmp ebx, 0x02",
"opcode": "mov eax, 0x5758554a",
"opcode": "mov ebp, 0x10c2377a",
"opcode": "cmovl ebp, eax",
"opcode": "mov eax, 0xbaad0c8f",
"opcode": "cmp eax, 0xccdab13a",
"opcode": "jg 0x40058a",
"opcode": "jnle 0x40058a",
"opcode": "jmp 0x4005ae",
"opcode": "mov edi, 0x400664",
"opcode": "xor eax, eax",
@ -2098,22 +2099,22 @@ EXPECT=<<EOF
"opcode": "cmp eax, 0xccdab13a",
"opcode": "jle 0x4005ae",
"opcode": "cmp eax, 0x10c2377a",
"opcode": "je 0x400570",
"opcode": "jz 0x400570",
"opcode": "cmp eax, 0x5758554a",
"opcode": "jne 0x4005b9",
"opcode": "jnz 0x4005b9",
"opcode": "mov edi, 0x40066d",
"opcode": "call 0x400430",
"opcode": "mov eax, 0xccdab13b",
"opcode": "cmp eax, 0xccdab13a",
"opcode": "jg 0x40058a",
"opcode": "jnle 0x40058a",
"opcode": "cmp eax, 0xbaad0c8f",
"opcode": "mov eax, ebp",
"opcode": "je 0x400583",
"opcode": "jz 0x400583",
"opcode": "jmp 0x4005d0",
"opcode": "cmp eax, 0xccdab13b",
"opcode": "jne 0x4005d0",
"opcode": "jnz 0x4005d0",
"opcode": "xor eax, eax",
"opcode": "add rsp, 8",
"opcode": "add rsp, 0x08",
"opcode": "pop rbx",
"opcode": "pop rbp",
"opcode": "ret",
@ -2131,9 +2132,9 @@ pd 1 @ 0x9a9
pd 1 @ 0x9b3
EOF
EXPECT=<<EOF
0x000009a2 mov dword [rbp - 0x30], 0x3c3c2b3e ; '>+<<'
0x000009a9 mov word [rbp - 0x2c], 0x3e5d ; ']>'
0x000009b3 movabs rax, 0x3c2b3c3c5b3e3e3e ; '>>>[<<+<'
0x000009a2 mov dword [rbp-0x30], 0x3c3c2b3e ; '>+<<'
0x000009a9 mov word [rbp-0x2c], 0x3e5d ; ']>'
0x000009b3 mov rax, 0x3c2b3c3c5b3e3e3e ; '>>>[<<+<'
EOF
RUN
@ -2149,9 +2150,9 @@ pdJ 1 @ 0x9b3
EOF
EXPECT=<<EOF
; '>>>[<<+<'
0x000009b3 48b83e3e3e5b. movabs rax, 0x3c2b3c3c5b3e3e3e
0x000009b3 48b83e3e3e5b. mov rax, 0x3c2b3c3c5b3e3e3e
[{"offset":2483,"text":" ; '>>>[<<+<'"},{"offset":2483,"text":" 0x000009b3 48b83e3e3e5b. movabs rax, 0x3c2b3c3c5b3e3e3e"}]
[{"offset":2483,"text":" ; '>>>[<<+<'"},{"offset":2483,"text":" 0x000009b3 48b83e3e3e5b. mov rax, 0x3c2b3c3c5b3e3e3e"}]
EOF
RUN
@ -2194,7 +2195,7 @@ pd 1 @ 0xe78
EOF
EXPECT=<<EOF
; 'f'
0x00000e78 mov byte [rbp - 0x274e], 0x66
0x00000e78 mov byte [rbp-0x274e], 0x66
EOF
RUN
@ -2216,9 +2217,9 @@ EXPECT=<<EOF
| 0x00005aed 4883e4f0 and rsp, 0xfffffffffffffff0
| 0x00005af1 50 push rax
| 0x00005af2 54 push rsp
| 0x00005af3 4c8d05660c01. lea r8, [0x00016760]
| 0x00005afa 488d0def0b01. lea rcx, [0x000166f0]
| 0x00005b01 488d3d68e5ff. lea rdi, [main] ; 0x4070 ; "AWAVAUATU\x89\xfdSH\x89\xf3H\x83\xecXH\x8b>dH\x8b\U00000004%("
| 0x00005af3 4c8d05660c01. lea r8, qword [0x00016760]
| 0x00005afa 488d0def0b01. lea rcx, qword [0x000166f0]
| 0x00005b01 488d3d68e5ff. lea rdi, qword [main] ; 0x4070 ; "AWAVAUATU\x89\xfdSH\x89\xf3H\x83\xecXH\x8b>dH\x8b\U00000004%("
\ 0x00005b08 ff150ac30100 call qword [reloc.__libc_start_main] ; [reloc.__libc_start_main:8]=0x23708 reloc.target.__libc_start_main
EOF
RUN
@ -2254,9 +2255,9 @@ call 0x401836
jmp 0x401322
push ebp
mov ebp, esp
push 0
push 0x00
call dword [SetUnhandledExceptionFilter]
push dword [ebp + 8]
push dword [ebp+0x08]
call dword [UnhandledExceptionFilter]
push 0xc0000409
call dword [GetCurrentProcess]
@ -2396,8 +2397,8 @@ e asm.ucase=true
pd 1
EOF
EXPECT=<<EOF
0x00401533 and esp, 0fffffff0h
0x00401533 AND ESP, 0FFFFFFF0H
0x00401533 and esp, -10h
0x00401533 AND ESP, -10H
EOF
RUN
@ -2435,8 +2436,8 @@ e asm.ucase=true
pd 1
EOF
EXPECT=<<EOF
0x000007cf call sym.imp.strlen
0x000007cf CALL sym.imp.strlen
0x000007cf call $-16fh ; sym.imp.strlen
0x000007cf CALL $-16FH ; sym.imp.strlen
EOF
RUN
@ -2455,8 +2456,8 @@ e asm.ucase=true
pd 1
EOF
EXPECT=<<EOF
0x10000108a lea rsi, section.4.__TEXT.__cstring
0x10000108a LEA RSI, section.4.__TEXT.__cstring
0x10000108a lea rsi, qword section.4.__TEXT.__cstring
0x10000108a LEA RSI, QWORD section.4.__TEXT.__cstring
EOF
RUN
@ -2750,24 +2751,24 @@ EXPECT=<<EOF
| 0x08048541 mov ebp, esp
| 0x08048543 sub esp, 0x88
| 0x08048549 and esp, 0xfffffff0
| 0x0804854c mov eax, 0
| 0x08048551 add eax, 0xf ; 15
| 0x08048554 add eax, 0xf ; 15
| 0x08048557 shr eax, 4
| 0x0804855a shl eax, 4
| 0x0804854c mov eax, 0x00
| 0x08048551 add eax, 0x0f ; 0xf ; 15
| 0x08048554 add eax, 0x0f ; 0xf ; 15
| 0x08048557 shr eax, 0x04
| 0x0804855a shl eax, 0x04
| 0x0804855d sub esp, eax
| 0x0804855f mov dword [esp], str.IOLI_Crackme_Level_0x05 ; [0x804868e:4]=0x494c4f49 ; "IOLI Crackme Level 0x05\n" ; const char *format
| 0x08048566 call sym.imp.printf ; int printf(const char *format)
| 0x0804856b mov dword [esp], str.Password: ; [0x80486a7:4]=0x73736150 ; "Password: " ; const char *format
| 0x08048572 call sym.imp.printf ; int printf(const char *format)
| 0x08048577 lea eax, [var_7ch]
| 0x08048577 lea eax, dword [var_7ch]
| 0x0804857a mov dword [var_88h], eax
| 0x0804857e mov dword [esp], data.080486b2 ; [0x80486b2:4]=0x7325 ; "%s" ; const char *format
| 0x08048585 call sym.imp.scanf ; int scanf(const char *format)
| 0x0804858a lea eax, [var_7ch]
| 0x0804858a lea eax, dword [var_7ch]
| 0x0804858d mov dword [esp], eax ; int32_t arg_4h
| 0x08048590 call sym.check
| 0x08048595 mov eax, 0
| 0x08048595 mov eax, 0x00
| 0x0804859a leave
\ 0x0804859b ret
@ -2856,8 +2857,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514071,
"size": 5,
"opcode": "mov eax, 0",
"disasm": "mov eax, 0",
"opcode": "mov eax, 0x00",
"disasm": "mov eax, 0x00",
"bytes": "b800000000",
"family": "cpu",
"type": "mov",
@ -2874,8 +2875,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514073,
"size": 3,
"opcode": "add eax, 0xf",
"disasm": "add eax, 0xf",
"opcode": "add eax, 0x0f",
"disasm": "add eax, 0x0f",
"bytes": "83c00f",
"family": "cpu",
"type": "add",
@ -2892,8 +2893,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514073,
"size": 3,
"opcode": "add eax, 0xf",
"disasm": "add eax, 0xf",
"opcode": "add eax, 0x0f",
"disasm": "add eax, 0x0f",
"bytes": "83c00f",
"family": "cpu",
"type": "add",
@ -2909,8 +2910,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514073,
"size": 3,
"opcode": "shr eax, 4",
"disasm": "shr eax, 4",
"opcode": "shr eax, 0x04",
"disasm": "shr eax, 0x04",
"bytes": "c1e804",
"family": "cpu",
"type": "shr",
@ -2925,8 +2926,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514073,
"size": 3,
"opcode": "shl eax, 4",
"disasm": "shl eax, 4",
"opcode": "shl eax, 0x04",
"disasm": "shl eax, 0x04",
"bytes": "c1e004",
"family": "cpu",
"type": "shl",
@ -3053,8 +3054,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514073,
"size": 3,
"opcode": "lea eax, [ebp - 0x78]",
"disasm": "lea eax, [var_7ch]",
"opcode": "lea eax, dword [ebp-0x78]",
"disasm": "lea eax, dword [var_7ch]",
"bytes": "8d4588",
"family": "cpu",
"type": "lea",
@ -3069,7 +3070,7 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514072,
"size": 4,
"opcode": "mov dword [esp + 4], eax",
"opcode": "mov dword [esp+0x04], eax",
"disasm": "mov dword [var_88h], eax",
"bytes": "89442404",
"family": "cpu",
@ -3133,8 +3134,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514073,
"size": 3,
"opcode": "lea eax, [ebp - 0x78]",
"disasm": "lea eax, [var_7ch]",
"opcode": "lea eax, dword [ebp-0x78]",
"disasm": "lea eax, dword [var_7ch]",
"bytes": "8d4588",
"family": "cpu",
"type": "lea",
@ -3190,8 +3191,8 @@ EXPECT=<<EOF
"fcn_addr": 134513984,
"fcn_last": 134514071,
"size": 5,
"opcode": "mov eax, 0",
"disasm": "mov eax, 0",
"opcode": "mov eax, 0x00",
"disasm": "mov eax, 0x00",
"bytes": "b800000000",
"family": "cpu",
"type": "mov",

198
test/db/cmd/cmd_pd2
View file

@ -127,12 +127,12 @@ EXPECT=<<EOF
| ||: 0x00560eb9 mov dword [esp], 0x4b7dbaf4
| ||: 0x00560ec0 mov dword [esp], ebx
| ||: 0x00560ec3 mov ebx, 0x60
| ||: 0x00560ec8 mov dword [esp + 4], ebx
| ||: 0x00560ec8 mov dword [esp+0x04], ebx
| ||: 0x00560ecc pop ebx
| ||: 0x00560ecd push ecx
| ||: 0x00560ece mov dword [esp], 0x7fdd7312
| ||: 0x00560ed5 or dword [esp], 0x76fe6216
| |: 0x00560edc shl dword [esp], 1
| |: 0x00560edc shl dword [esp], 0x01
| |: 0x00560ee0 or dword [esp], 0x5677e157
| |: 0x00560ee7 sub dword [esp], 0x66a97007
| |: 0x00560eee add dword [esp], 0xd4a8fad4
@ -143,8 +143,8 @@ EXPECT=<<EOF
| |: 0x00560f00 sub dword [esp], 0x91ea8610
| |: 0x00560f07 push ebp
| |: 0x00560f08 mov ebp, esp
| |: 0x00560f0a add ebp, 4
| |: 0x00560f10 sub ebp, 4
| |: 0x00560f0a add ebp, 0x04
| |: 0x00560f10 sub ebp, 0x04
| |: 0x00560f16 xchg dword [esp], ebp
| |: 0x00560f19 pop esp
| |: 0x00560f1a mov dword [esp], ecx
@ -153,16 +153,16 @@ EXPECT=<<EOF
| |: 0x00560f25 mov dword [esp], ecx
| |: 0x00560f28 mov ecx, esp
| : 0x00560f2a push ebx
| : 0x00560f2b mov ebx, 4
| : 0x00560f2b mov ebx, 0x04
| : 0x00560f30 add ecx, ebx
| : 0x00560f32 pop ebx
| : 0x00560f33 sub ecx, 4
| : 0x00560f33 sub ecx, 0x04
| : 0x00560f36 xor ecx, dword [esp]
| : 0x00560f39 xor dword [esp], ecx
| : 0x00560f3c xor ecx, dword [esp]
| : 0x00560f3f pop esp
| : 0x00560f40 mov dword [esp], ebx
| : 0x00560f43 push dword [esp + 0x10]
| : 0x00560f43 push dword [esp+0x10]
| : 0x00560f47 mov eax, dword [esp]
| : 0x00560f4a push esi
| : 0x00560f4b mov esi, esp
@ -172,30 +172,30 @@ EXPECT=<<EOF
| : 0x00560f59 xor edx, 0x745d0117
| : 0x00560f5f add esi, edx
| : 0x00560f61 mov edx, dword [esp]
| : 0x00560f64 add esp, 4
| : 0x00560f67 add esi, 4
| : 0x00560f64 add esp, 0x04
| : 0x00560f67 add esi, 0x04
| : 0x00560f6d xchg dword [esp], esi
| : 0x00560f70 pop esp
| : 0x00560f71 push dword [esp + 8]
| : 0x00560f71 push dword [esp+0x08]
| : 0x00560f75 push dword [esp]
| : 0x00560f78 mov ebx, dword [esp]
| : 0x00560f7b push ebx
| : 0x00560f7c mov ebx, esp
| : 0x00560f7e add ebx, 4
| : 0x00560f84 add ebx, 4
| : 0x00560f7e add ebx, 0x04
| : 0x00560f84 add ebx, 0x04
| : 0x00560f8a xchg dword [esp], ebx
| : 0x00560f8d pop esp
| : 0x00560f8e add esp, 4
| : 0x00560f91 mov dword [esp + 8], eax
| : 0x00560f95 mov dword [esp + 0x10], ebx
| : 0x00560f8e add esp, 0x04
| : 0x00560f91 mov dword [esp+0x08], eax
| : 0x00560f95 mov dword [esp+0x10], ebx
| : 0x00560f99 push dword [esp]
| : 0x00560f9c pop ebx
| : 0x00560f9d push ebx
| : 0x00560f9e mov ebx, esp
| : 0x00560fa0 add ebx, 4
| : 0x00560fa6 add ebx, 4
| : 0x00560fa0 add ebx, 0x04
| : 0x00560fa6 add ebx, 0x04
| : 0x00560fa9 push ebx
| : 0x00560faa push dword [esp + 4]
| : 0x00560faa push dword [esp+0x04]
| : 0x00560fae pop ebx
| : 0x00560faf pop dword [esp]
| : 0x00560fb2 mov esp, dword [esp]
@ -204,8 +204,8 @@ EXPECT=<<EOF
| : 0x00560fb9 mov dword [esp], 0x1e8e43e4
| : 0x00560fc0 mov dword [esp], eax
| : 0x00560fc3 mov eax, esp
| : 0x00560fc5 add eax, 4
| : 0x00560fca add eax, 4
| : 0x00560fc5 add eax, 0x04
| : 0x00560fca add eax, 0x04
| : 0x00560fcf xchg dword [esp], eax
| : 0x00560fd2 mov esp, dword [esp]
\ `=< 0x00560fd5 jmp 0x43d3f7
@ -338,8 +338,8 @@ wx 7d0a7f08eb00 @ 0x5b02
pd 4 @ 0x5b02
EOF
EXPECT=<<EOF
,=< 0x00005b02 7d0a jge 0x5b0e ; rip=0x5b0e -> 0x8d4890f4 ; likely
,==< 0x00005b04 7f08 jg 0x5b0e ; rip=0x5b0e -> 0x8d4890f4 ; likely
,=< 0x00005b02 7d0a jnl 0x5b0e ; rip=0x5b0e -> 0x8d4890f4 ; likely
,==< 0x00005b04 7f08 jnle 0x5b0e ; rip=0x5b0e -> 0x8d4890f4 ; likely
,===< 0x00005b06 eb00 jmp 0x5b08 ; rip=0x5b08 -> 0xc30a15ff
`---> 0x00005b08 ff150ac30100 call qword [reloc.__libc_start_main] ; [reloc.__libc_start_main:8]=0x23708 reloc.target.__libc_start_main ; rsp=0xfffffffffffffff8 ; rip=0x23708 -> 0x464c457f reloc.target.__libc_start_main
EOF
@ -360,8 +360,8 @@ e asm.cmt.right=false
pd 1
EOF
EXPECT=<<EOF
0x00000000 488b4608 mov rax, qword [rsi + ms.member1]
0x00000000 488b4608 mov rax, qword [rsi + ms.member1]
0x00000000 488b4608 mov rax, qword [rsi+ms.member1]
0x00000000 488b4608 mov rax, qword [rsi+ms.member1]
EOF
RUN
@ -395,13 +395,13 @@ EXPECT=<<EOF
| 0x080483f6 ret
|
0x080483f7 mov esi, esi
0x080483f9 lea edi, [edi]
0x080483f9 lea edi, dword [edi]
|
\ 0x08048400 ret
| 0x08048470 ret
|
0x08048471 lea esi, [esi]
0x08048471 lea esi, dword [esi]
|
\ 0x08048478 ret
EOF
@ -423,16 +423,16 @@ s 0x08048598
pd 11
EOF
EXPECT=<<EOF
,=< 0x08048598 jg 0x804859e
| 0x0804859a cmp al, byte [esp + 0x27]
,`-> 0x0804859e je 0x80485b3
,=< 0x08048598 jnle 0x804859e
| 0x0804859a cmp al, byte [esp+0x27]
,`-> 0x0804859e jz 0x80485b3
| 0x080485a0 mov dword [esp], str.Wrong
| 0x080485a7 call sym.imp.puts
| 0x080485ac mov eax, 1
| 0x080485ac mov eax, 0x01
,=.-> 0x080485b1 jmp 0x80485f9
|`--> 0x080485b3 add dword [esp + 0x20], 1
| : 0x080485b8 mov ebx, dword [esp + 0x20]
| `=< 0x080485bc jne 0x80485b1
|`--> 0x080485b3 add dword [esp+0x20], 0x01
| : 0x080485b8 mov ebx, dword [esp+0x20]
| `=< 0x080485bc jnz 0x80485b1
| 0x080485be nop
EOF
RUN
@ -454,17 +454,17 @@ echo
pdJ 9~{}
EOF
EXPECT=<<EOF
| ,=< 0x00004233 jg 0x4238
| ,=< 0x00004233 jnle 0x4238
| | |
| | 0x00004235 test rax, rax
| | |
| ,`-> 0x00004238 je 0x4243
| ,`-> 0x00004238 jz 0x4243
| | |
| | 0x0000423a cmp byte [rax], 0
| | 0x0000423a cmp byte [rax], 0x00
| | |
| ,=.-> 0x0000423d jne 0x4b1c
| ,=.-> 0x0000423d jnz 0x4b1c
| ||: |
| |`--> 0x00004243 lea r12, [var_58h]
| |`--> 0x00004243 lea r12, qword [var_58h]
| | : 0x00004248 xor eax, eax
| | `=< 0x0000424a jb 0x423d
| | |
@ -474,7 +474,7 @@ EXPECT=<<EOF
{
"offset": 16947,
"arrow": 16952,
"text": "| ,=< 0x00004233 jg 0x4238"
"text": "| ,=< 0x00004233 jnle 0x4238"
},
{
"offset": 16949,
@ -492,7 +492,7 @@ EXPECT=<<EOF
{
"offset": 16952,
"arrow": 16963,
"text": "| ,`-> 0x00004238 je 0x4243"
"text": "| ,`-> 0x00004238 jz 0x4243"
},
{
"offset": 16954,
@ -500,7 +500,7 @@ EXPECT=<<EOF
},
{
"offset": 16954,
"text": "| | 0x0000423a cmp byte [rax], 0"
"text": "| | 0x0000423a cmp byte [rax], 0x00"
},
{
"offset": 16957,
@ -510,7 +510,7 @@ EXPECT=<<EOF
{
"offset": 16957,
"arrow": 19228,
"text": "| ,=.-> 0x0000423d jne 0x4b1c"
"text": "| ,=.-> 0x0000423d jnz 0x4b1c"
},
{
"offset": 16963,
@ -518,7 +518,7 @@ EXPECT=<<EOF
},
{
"offset": 16963,
"text": "| |`--> 0x00004243 lea r12, [var_58h]"
"text": "| |`--> 0x00004243 lea r12, qword [var_58h]"
},
{
"offset": 16968,
@ -589,50 +589,50 @@ wx 483b3df6470100 @ 0x00004225 # cmp rdi, [rip + 0x147f6]
.(insn_tests)
EOF
EXPECT=<<EOF
,=< 0x000041e0 je 0x421a
| 0x000041e2 mov ecx, 4
| 0x000041e7 lea rdx, [0x0001b980]
| 0x000041ee lea rsi, [0x00021a40]
,=< 0x000041e0 jz 0x421a
| 0x000041e2 mov ecx, 0x04
| 0x000041e7 lea rdx, qword [0x0001b980]
| 0x000041ee lea rsi, qword [0x00021a40]
| 0x000041f5 mov rdi, rax
| 0x000041f8 call 0xc660
| 0x000041fe test eax, eax
,==< 0x00004200 js 0x4ae5
|| 0x00004206 cdqe
|| 0x00004208 lea rdx, [0x0001b980]
|| 0x00004208 lea rdx, qword [0x0001b980]
|| 0x0000420f xor edi, edi
|| 0x00004211 mov esi, dword [rdx + rax*4]
|| 0x00004211 mov esi, dword [rdx+rax*4]
|| 0x00004214 call 0x13c50
|`-> 0x0000421a mov qword [0x000232b0], 0x50 ; 'P'
| ; [0x232b0:8]=0
| 0x00004225 lea rdi, str.COLUMNS ; 0x18a22 ; "COLUMNS"
| 0x00004225 lea rdi, qword str.COLUMNS ; 0x18a22 ; "COLUMNS"
0x000041ee lea rsi, [rip + 0x1d84b] ; 0x21a40
0x00004225 lea rdi, [rip + 0x147f6] ; str.COLUMNS
0x000041ee lea rsi, qword [rip+0x1d84b] ; 0x21a40
0x00004225 lea rdi, qword [rip+0x147f6] ; str.COLUMNS
; 0x18a22 ; "COLUMNS"
,=< 0x000041e0 je 0x421a
| 0x000041e2 mov ecx, 4
| 0x000041e7 lea rdx, [0x0001b980]
| 0x000041ee lea rsi, [0x00021a40]
,=< 0x000041e0 jz 0x421a
| 0x000041e2 mov ecx, 0x04
| 0x000041e7 lea rdx, qword [0x0001b980]
| 0x000041ee lea rsi, qword [0x00021a40]
| 0x000041f5 mov rdi, rax
| 0x000041f8 call 0xc660
| 0x000041fe test eax, eax
,==< 0x00004200 js 0x4ae5
|| 0x00004206 cdqe
|| 0x00004208 lea rdx, [0x0001b980]
|| 0x00004208 lea rdx, qword [0x0001b980]
|| 0x0000420f xor edi, edi
|| 0x00004211 mov esi, dword [rdx + rax*4]
|| 0x00004211 mov esi, dword [rdx+rax*4]
|| 0x00004214 call 0x13c50
|`-> 0x0000421a mov qword [0x000232b0], 0x50 ; 'P'
|  ; [0x232b0:8]=0
| 0x00004225 lea rdi, str.COLUMNS ; 0x18a22 ; "COLUMNS"
| 0x00004225 lea rdi, qword str.COLUMNS ; 0x18a22 ; "COLUMNS"
0x000041ee lea rsi, [rip + 0x1d84b] ; 0x21a40
0x00004225 lea rdi, [rip + 0x147f6] ; str.COLUMNS
0x000041ee lea rsi, qword [rip+0x1d84b] ; 0x21a40
0x00004225 lea rdi, qword [rip+0x147f6] ; str.COLUMNS
 ; 0x18a22 ; "COLUMNS"
,=< 0x000041e0 je 0x421a
| 0x000041e2 mov ecx, 4
,=< 0x000041e0 jz 0x421a
| 0x000041e2 mov ecx, 0x04
| 0x000041e7 mov rax, qword [0x0001b980] ; [0x1b980:8]=0x100000000
| 0x000041ee mov rax, qword [0x00021a40] ; [0x21a40:8]=0x18d31 str.literal
| 0x000041f5 mov rdi, rax
@ -640,20 +640,20 @@ EXPECT=<<EOF
| 0x000041fe test eax, eax
,==< 0x00004200 js 0x4ae5
|| 0x00004206 cdqe
|| 0x00004208 lea rdx, [0x0001b980]
|| 0x00004208 lea rdx, qword [0x0001b980]
|| 0x0000420f xor edi, edi
|| 0x00004211 mov esi, dword [rdx + rax*4]
|| 0x00004211 mov esi, dword [rdx+rax*4]
|| 0x00004214 call 0x13c50
|`-> 0x0000421a mov qword [0x000232b0], 0x50 ; 'P'
| ; [0x232b0:8]=0
| 0x00004225 mov rax, qword [str.COLUMNS] ; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
0x000041ee mov rax, qword [rip + 0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 mov rax, qword [rip + 0x147f6] ; str.COLUMNS
0x000041ee mov rax, qword [rip+0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 mov rax, qword [rip+0x147f6] ; str.COLUMNS
; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
,=< 0x000041e0 je 0x421a
| 0x000041e2 mov ecx, 4
,=< 0x000041e0 jz 0x421a
| 0x000041e2 mov ecx, 0x04
| 0x000041e7 mov rax, qword [0x0001b980] ; [0x1b980:8]=0x100000000
| 0x000041ee mov rax, qword [0x00021a40] ; [0x21a40:8]=0x18d31 str.literal
| 0x000041f5 mov rdi, rax
@ -661,20 +661,20 @@ EXPECT=<<EOF
| 0x000041fe test eax, eax
,==< 0x00004200 js 0x4ae5
|| 0x00004206 cdqe
|| 0x00004208 lea rdx, [0x0001b980]
|| 0x00004208 lea rdx, qword [0x0001b980]
|| 0x0000420f xor edi, edi
|| 0x00004211 mov esi, dword [rdx + rax*4]
|| 0x00004211 mov esi, dword [rdx+rax*4]
|| 0x00004214 call 0x13c50
|`-> 0x0000421a mov qword [0x000232b0], 0x50 ; 'P'
|  ; [0x232b0:8]=0
| 0x00004225 mov rax, qword [str.COLUMNS] ; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
0x000041ee mov rax, qword [rip + 0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 mov rax, qword [rip + 0x147f6] ; str.COLUMNS
0x000041ee mov rax, qword [rip+0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 mov rax, qword [rip+0x147f6] ; str.COLUMNS
 ; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
,=< 0x000041e0 je 0x421a
| 0x000041e2 mov ecx, 4
,=< 0x000041e0 jz 0x421a
| 0x000041e2 mov ecx, 0x04
| 0x000041e7 cmp rdx, qword [0x0001b980] ; [0x1b980:8]=0x100000000
| 0x000041ee cmp rsi, qword [0x00021a40] ; [0x21a40:8]=0x18d31 str.literal
| 0x000041f5 mov rdi, rax
@ -682,20 +682,20 @@ EXPECT=<<EOF
| 0x000041fe test eax, eax
,==< 0x00004200 js 0x4ae5
|| 0x00004206 cdqe
|| 0x00004208 lea rdx, [0x0001b980]
|| 0x00004208 lea rdx, qword [0x0001b980]
|| 0x0000420f xor edi, edi
|| 0x00004211 mov esi, dword [rdx + rax*4]
|| 0x00004211 mov esi, dword [rdx+rax*4]
|| 0x00004214 call 0x13c50
|`-> 0x0000421a mov qword [0x000232b0], 0x50 ; 'P'
| ; [0x232b0:8]=0
| 0x00004225 cmp rdi, qword [str.COLUMNS] ; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
0x000041ee cmp rsi, qword [rip + 0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 cmp rdi, qword [rip + 0x147f6] ; str.COLUMNS
0x000041ee cmp rsi, qword [rip+0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 cmp rdi, qword [rip+0x147f6] ; str.COLUMNS
; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
,=< 0x000041e0 je 0x421a
| 0x000041e2 mov ecx, 4
,=< 0x000041e0 jz 0x421a
| 0x000041e2 mov ecx, 0x04
| 0x000041e7 cmp rdx, qword [0x0001b980] ; [0x1b980:8]=0x100000000
| 0x000041ee cmp rsi, qword [0x00021a40] ; [0x21a40:8]=0x18d31 str.literal
| 0x000041f5 mov rdi, rax
@ -703,16 +703,16 @@ EXPECT=<<EOF
| 0x000041fe test eax, eax
,==< 0x00004200 js 0x4ae5
|| 0x00004206 cdqe
|| 0x00004208 lea rdx, [0x0001b980]
|| 0x00004208 lea rdx, qword [0x0001b980]
|| 0x0000420f xor edi, edi
|| 0x00004211 mov esi, dword [rdx + rax*4]
|| 0x00004211 mov esi, dword [rdx+rax*4]
|| 0x00004214 call 0x13c50
|`-> 0x0000421a mov qword [0x000232b0], 0x50 ; 'P'
|  ; [0x232b0:8]=0
| 0x00004225 cmp rdi, qword [str.COLUMNS] ; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
0x000041ee cmp rsi, qword [rip + 0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 cmp rdi, qword [rip + 0x147f6] ; str.COLUMNS
0x000041ee cmp rsi, qword [rip+0x1d84b] ; [0x21a40:8]=0x18d31 str.literal
0x00004225 cmp rdi, qword [rip+0x147f6] ; str.COLUMNS
 ; [0x18a22:8]=0x534e4d554c4f43 ; "COLUMNS"
EOF
RUN
@ -728,8 +728,8 @@ e scr.color=1
pd 1
EOF
EXPECT=<<EOF
0x00005e6e 488d3d339b01. lea rdi, section..fini_array ; 0x1f9a8
0x00005e6e 488d3d339b01. lea rdi, section..fini_array ; 0x1f9a8
0x00005e6e 488d3d339b01. lea rdi, qword section..fini_array ; 0x1f9a8
0x00005e6e 488d3d339b01. lea rdi, qword section..fini_array ; 0x1f9a8
EOF
RUN
@ -741,21 +741,21 @@ s 0x000041e0
pi 15
EOF
EXPECT=<<EOF
je 0x421a
mov ecx, 4
lea rdx, [0x0001b980]
lea rsi, [0x00021a40]
jz 0x421a
mov ecx, 0x04
lea rdx, qword [0x0001b980]
lea rsi, qword [0x00021a40]
mov rdi, rax
call 0xc660
test eax, eax
js 0x4ae5
cdqe
lea rdx, [0x0001b980]
lea rdx, qword [0x0001b980]
xor edi, edi
mov esi, dword [rdx + rax*4]
mov esi, dword [rdx+rax*4]
call 0x13c50
mov qword [0x000232b0], 0x50
lea rdi, str.COLUMNS
lea rdi, qword str.COLUMNS
EOF
RUN
@ -848,7 +848,7 @@ EXPECT=<<EOF
entry0 + 2 xor eax, eax
entry0 + 4 inc eax
segment.LOAD0 + 83 ~ add byte [ebx + 0x40c0312a], dh
segment.LOAD0 + 83 ~ add byte [ebx+0x40c0312a], dh
entry0 + 0 ;-- entry0:
entry0 + 0 mov bl, 0x2a
entry0 + 2 xor eax, eax
@ -899,8 +899,8 @@ EXPECT=<<EOF
;-- .text:
/ int main(int argc, char **argv, char **envp);
| 0x00001040 f30f1efa endbr64 ; [13] -r-x section size 389 named .text
| 0x00001044 8005f52f0000. add byte [obj.array], 1 ; [0x4040:1]=0
| ,=< 0x0000104b 7403 je 0x1050
| 0x00001044 8005f52f0000. add byte [obj.array], 0x01 ; [0x4040:1]=0
| ,=< 0x0000104b 7403 jz 0x1050
| @=-> 0x0000104d ebfe jmp 0x104d
..
| `-> 0x00001050 31c0 xor eax, eax
@ -921,12 +921,12 @@ e scr.utf8.curvy=1
pd 4 @ 0x104b
EOF
EXPECT=<<EOF
│ ┌─< 0x0000104b je 0x1050
│ ┌─< 0x0000104b jz 0x1050
│ @──> 0x0000104d jmp 0x104d
│ 0x0000104f nop
│ └─> 0x00001050 xor eax, eax
│ ╭─< 0x0000104b je 0x1050
│ ╭─< 0x0000104b jz 0x1050
│ @──> 0x0000104d jmp 0x104d
│ 0x0000104f nop
│ ╰─> 0x00001050 xor eax, eax

2
test/db/cmd/cmd_pd_bugs
View file

@ -123,7 +123,7 @@ e asm.comments=false
pD 6@x:8d15d0830408
EOF
EXPECT=<<EOF
0x00000000 8d15d0830408 lea edx, [0x80483d0]
0x00000000 8d15d0830408 lea edx, dword [0x80483d0]
EOF
RUN

12
test/db/cmd/cmd_pd_bytes
View file

@ -9,9 +9,9 @@ wx b8010000004839ca7f00
pD -10 @ 0xa
EOF
EXPECT=<<EOF
0x00000000 b801000000 mov eax, 1
0x00000000 b801000000 mov eax, 0x01
0x00000005 4839ca cmp rdx, rcx
,=< 0x00000008 7f00 jg 0xa
,=< 0x00000008 7f00 jnle 0xa
EOF
RUN
@ -26,9 +26,9 @@ wx b8010000004839ca7f00
pD -10 @ 10
EOF
EXPECT=<<EOF
0x00000000 b801000000 mov eax, 1
0x00000000 b801000000 mov eax, 0x01
0x00000005 4839ca cmp rdx, rcx
,=< 0x00000008 7f00 jg 0xa
,=< 0x00000008 7f00 jnle 0xa
EOF
RUN
@ -43,7 +43,7 @@ wx b8010000004839ca7f00
pD 5
EOF
EXPECT=<<EOF
0x00000000 b801000000 mov eax, 1
0x00000000 b801000000 mov eax, 0x01
EOF
RUN
@ -57,7 +57,7 @@ wx b8010000004839ca7f00
pDj 5 @ 0
EOF
EXPECT=<<EOF
[{"offset":0,"val":1,"esil":"1,rax,=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":5,"opcode":"mov eax, 1","disasm":"mov eax, 1","bytes":"b801000000","family":"cpu","type":"mov","reloc":false,"type_num":9,"type2_num":0}]
[{"offset":0,"val":1,"esil":"1,rax,=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":5,"opcode":"mov eax, 0x01","disasm":"mov eax, 0x01","bytes":"b801000000","family":"cpu","type":"mov","reloc":false,"type_num":9,"type2_num":0}]
EOF
RUN

26
test/db/cmd/cmd_pde
View file

@ -15,25 +15,25 @@ EXPECT=<<EOF
0x00401311 mov ebp, esp
0x00401313 sub esp, 0x38
0x00401316 and esp, 0xfffffff0
0x00401319 mov eax, 0
0x0040131e add eax, 0xf
0x00401321 add eax, 0xf
0x00401324 shr eax, 4
0x00401327 shl eax, 4
0x0040132a mov dword [ebp - 0x1c], eax
0x0040132d mov eax, dword [ebp - 0x1c]
0x00401319 mov eax, 0x00
0x0040131e add eax, 0x0f
0x00401321 add eax, 0x0f
0x00401324 shr eax, 0x04
0x00401327 shl eax, 0x04
0x0040132a mov dword [ebp-0x1c], eax
0x0040132d mov eax, dword [ebp-0x1c]
0x00401330 call 0x402c70
0x00401335 push ecx
0x00401336 mov ecx, esp
0x00401338 add ecx, 8
0x00401338 add ecx, 0x08
0x0040133b cmp eax, 0x1000
0x00401340 jb 0x401352
0x00402c8d sub ecx, eax
0x00402c8f or dword [ecx], 0
0x00402c8f or dword [ecx], 0x00
0x00402c92 mov eax, esp
0x00402c94 mov esp, ecx
0x00402c96 mov ecx, dword [eax]
0x00402c98 mov eax, dword [eax + 4]
0x00402c98 mov eax, dword [eax+0x04]
0x00402c9b jmp eax
0x00401335 call sym.___main
0x0040133a push ebp
@ -154,10 +154,10 @@ EOF
EXPECT=<<EOF
xor eax, eax
mov byte [eax], 0x20
mov byte [eax + 0x40], 0
mov cl, byte [eax + 0x40]
mov byte [eax+0x40], 0x00
mov cl, byte [eax+0x40]
cmp cl, cl
jne 0x1010
jnz 0x1010
mov al, byte [0x30]
jmp eax
invalid

60
test/db/cmd/cmd_pdr
View file

@ -75,18 +75,18 @@ EOF
EXPECT=<<EOF
/ fcn.00000000();
| 0x00000000 0f1f440000 nop dword [rax + rax]
| 0x00000000 0f1f440000 nop dword [rax+rax*1], eax
| ----------- true: 0x00000005
| ; CODE XREF from fcn.00000000 @ 0x11
| 0x00000003 0000 add byte [rax], al
| ----------- true: 0x00000005
| 0x00000005 b8210000c1 mov eax, 0xc1000021 ; '!'
| 0x0000000a ebfd jmp 9
| 0x0000000a ebfd jmp 0x9
| ----------- true: 0x00000009
| ; CODE XREF from fcn.00000000 @ 0xa
| 0x00000009 c1ebfd shr ebx, 0xfd
| 0x0000000c bb2c000000 mov ebx, 0x2c ; ','
\ 0x00000011 ebf0 jmp 3
\ 0x00000011 ebf0 jmp 0x3
| ----------- true: 0x00000003
[
@ -97,8 +97,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 14,
"size": 5,
"opcode": "nop dword [rax + rax]",
"disasm": "nop dword [rax + rax]",
"opcode": "nop dword [rax+rax*1], eax",
"disasm": "nop dword [rax+rax*1], eax",
"bytes": "0f1f440000",
"family": "cpu",
"type": "nop",
@ -133,9 +133,9 @@ EXPECT=<<EOF
},
{
"offset": 5,
"ptr": 3238002721,
"val": 3238002721,
"esil": "3238002721,rax,=",
"ptr": 18446744072652587041,
"val": 18446744072652587041,
"esil": "18446744072652587041,rax,=",
"refptr": false,
"fcn_addr": 0,
"fcn_last": 14,
@ -156,8 +156,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 9",
"disasm": "jmp 9",
"opcode": "jmp 0x9",
"disasm": "jmp 0x9",
"bytes": "ebfd",
"family": "cpu",
"type": "jmp",
@ -226,8 +226,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 3",
"disasm": "jmp 3",
"opcode": "jmp 0x3",
"disasm": "jmp 0x3",
"bytes": "ebf0",
"family": "cpu",
"type": "jmp",
@ -244,13 +244,13 @@ EXPECT=<<EOF
}
]
nop dword [rax + rax]
nop dword [rax+rax*1], eax
add byte [rax], al
mov eax, 0xc1000021
jmp 9
jmp 0x9
shr ebx, 0xfd
mov ebx, 0x2c
jmp 3
jmp 0x3
[
{
@ -260,8 +260,8 @@ jmp 3
"fcn_addr": 0,
"fcn_last": 14,
"size": 5,
"opcode": "nop dword [rax + rax]",
"disasm": "nop dword [rax + rax]",
"opcode": "nop dword [rax+rax*1], eax",
"disasm": "nop dword [rax+rax*1], eax",
"bytes": "0f1f440000",
"family": "cpu",
"type": "nop",
@ -296,9 +296,9 @@ jmp 3
},
{
"offset": 5,
"ptr": 3238002721,
"val": 3238002721,
"esil": "3238002721,rax,=",
"ptr": 18446744072652587041,
"val": 18446744072652587041,
"esil": "18446744072652587041,rax,=",
"refptr": false,
"fcn_addr": 0,
"fcn_last": 14,
@ -319,8 +319,8 @@ jmp 3
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 9",
"disasm": "jmp 9",
"opcode": "jmp 0x9",
"disasm": "jmp 0x9",
"bytes": "ebfd",
"family": "cpu",
"type": "jmp",
@ -389,8 +389,8 @@ jmp 3
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 3",
"disasm": "jmp 3",
"opcode": "jmp 0x3",
"disasm": "jmp 0x3",
"bytes": "ebf0",
"family": "cpu",
"type": "jmp",
@ -418,21 +418,21 @@ pdr @ entry.init0
EOF
EXPECT=<<EOF
| ; CODE XREF from entry.init0 @ 0x5bd4
| 0x00005b40 488d3d21c701. lea rdi, loc._edata ; loc.__bss_start
| 0x00005b40 488d3d21c701. lea rdi, qword loc._edata ; loc.__bss_start
| ; 0x22268
| 0x00005b47 488d351ac701. lea rsi, loc._edata ; loc.__bss_start
| 0x00005b47 488d351ac701. lea rsi, qword loc._edata ; loc.__bss_start
| ; 0x22268
| 0x00005b4e 4829fe sub rsi, rdi
| 0x00005b51 48c1fe03 sar rsi, 3
| 0x00005b51 48c1fe03 sar rsi, 0x03
| 0x00005b55 4889f0 mov rax, rsi
| 0x00005b58 48c1e83f shr rax, 0x3f
| 0x00005b5c 4801c6 add rsi, rax
| 0x00005b5f 48d1fe sar rsi, 1
| 0x00005b62 7414 je 0x5b78
| 0x00005b5f 48d1fe sar rsi, 0x01
| 0x00005b62 7414 jz 0x5b78
| ----------- true: 0x00005b78 false: 0x00005b64
| 0x00005b64 488b053dc401. mov rax, qword [reloc._ITM_registerTMCloneTable] ; [0x21fa8:8]=0x23898 reloc.target._ITM_registerTMCloneTable
| 0x00005b6b 4885c0 test rax, rax
| 0x00005b6e 7408 je 0x5b78
| 0x00005b6e 7408 jz 0x5b78
| ----------- true: 0x00005b78 false: 0x00005b70
| 0x00005b70 ffe0 jmp rax

12
test/db/cmd/cmd_pipe
View file

@ -25,8 +25,8 @@ Disassembly of entry0:
/ entry0();
| 0x08049020 push ebp ; [09] -r-x section size 16 named .text
| 0x08049021 mov ebp, esp
| 0x08049023 sub esp, 8
| 0x08049026 sub esp, 0xc
| 0x08049023 sub esp, 0x08
| 0x08049026 sub esp, 0x0c
| 0x08049029 push 0x2a ; '*' ; 42
\ 0x0804902b call sym.imp._Exit ; void _Exit(int status)
@ -70,8 +70,8 @@ Shared buffer size 0x360c
/ entry0();
| 0x08049020 push ebp ; [09] -r-x section size 16 named .text
| 0x08049021 mov ebp, esp
| 0x08049023 sub esp, 8
| 0x08049026 sub esp, 0xc
| 0x08049023 sub esp, 0x08
| 0x08049026 sub esp, 0x0c
| 0x08049029 push 0x2a ; '*' ; 42 ; int status
\ 0x0804902b call sym.imp._Exit ; void _Exit(int status)
@ -98,7 +98,7 @@ Shared buffer size 0x400
| 0x00401028 call dword [sym.imp.msvcrt.dll_printf] ; 0x4011bc ; int printf(const char *format)
| 0x0040102e add esp, 0x10
| 0x00401031 nop
| 0x00401032 push 0 ; UINT uExitCode
| 0x00401032 push 0x00 ; UINT uExitCode
\ 0x00401034 call dword [sym.imp.kernel32.dll_ExitProcess] ; 0x4011b0 ; VOID ExitProcess(UINT uExitCode)
Copying bins/mach0/mach0_2-x86_64...
@ -128,7 +128,7 @@ Shared buffer size 0x10e8
| 0x100000f70 push rbp
| 0x100000f71 mov rbp, rsp
| 0x100000f74 sub rsp, 0x10
| 0x100000f78 mov dword [var_ch], 0
| 0x100000f78 mov dword [var_ch], 0x00
| 0x100000f7f mov dword [var_10h], edi ; arg1
| 0x100000f82 mov qword [var_18h], rsi ; arg2
| 0x100000f86 mov edi, dword [var_10h] ; int64_t arg1

2
test/db/cmd/cmd_pix
View file

@ -37,7 +37,7 @@ push 0x64777373
push 0x61702f2f
push 0x6374652f
mov ecx, esp
mov al, 0xb
mov al, 0x0b
push edx
push ecx
push ebx

44
test/db/cmd/cmd_print
View file

@ -280,9 +280,9 @@ wx b8010000004839ca7f
pi 3
EOF
EXPECT=<<EOF
mov eax, 1
mov eax, 0x01
cmp rdx, rcx
jg 0xa
jnle 0xa
EOF
RUN
@ -295,7 +295,7 @@ wx b8010000004839ca7f
pdj 3
EOF
EXPECT=<<EOF
[{"offset":0,"val":1,"esil":"1,rax,=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":5,"opcode":"mov eax, 1","disasm":"mov eax, 1","bytes":"b801000000","family":"cpu","type":"mov","reloc":false,"type_num":9,"type2_num":0},{"offset":5,"esil":"rcx,rdx,==,$z,zf,:=,64,$b,cf,:=,$p,pf,:=,63,$s,sf,:=,rcx,0x8000000000000000,-,!,63,$o,^,of,:=,3,$b,af,:=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":3,"opcode":"cmp rdx, rcx","disasm":"cmp rdx, rcx","bytes":"4839ca","family":"cpu","type":"cmp","reloc":false,"type_num":15,"type2_num":0},{"offset":8,"esil":"sf,of,!,^,zf,!,&,?{,10,rip,=,}","refptr":false,"fcn_addr":0,"fcn_last":0,"size":2,"opcode":"jg 0xa","disasm":"jg 0xa","bytes":"7f00","family":"cpu","type":"cjmp","reloc":false,"type_num":2147483649,"type2_num":0,"jump":10,"fail":10}]
[{"offset":0,"val":1,"esil":"1,rax,=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":5,"opcode":"mov eax, 0x01","disasm":"mov eax, 0x01","bytes":"b801000000","family":"cpu","type":"mov","reloc":false,"type_num":9,"type2_num":0},{"offset":5,"esil":"rcx,rdx,==,$z,zf,:=,64,$b,cf,:=,$p,pf,:=,63,$s,sf,:=,rcx,0x8000000000000000,-,!,63,$o,^,of,:=,3,$b,af,:=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":3,"opcode":"cmp rdx, rcx","disasm":"cmp rdx, rcx","bytes":"4839ca","family":"cpu","type":"cmp","reloc":false,"type_num":15,"type2_num":0},{"offset":8,"esil":"sf,of,!,^,zf,!,&,?{,10,rip,=,}","refptr":false,"fcn_addr":0,"fcn_last":0,"size":2,"opcode":"jnle 0xa","disasm":"jnle 0xa","bytes":"7f00","family":"cpu","type":"cjmp","reloc":false,"type_num":2147483649,"type2_num":0,"jump":10,"fail":10}]
EOF
RUN
@ -308,12 +308,12 @@ wx b8010000004839ca7f00b8010000004839ca7f00
pi 6
EOF
EXPECT=<<EOF
mov eax, 1
mov eax, 0x01
cmp rdx, rcx
jg 0xa
mov eax, 1
jnle 0xa
mov eax, 0x01
cmp rdx, rcx
jg 0x14
jnle 0x14
EOF
RUN
@ -451,9 +451,9 @@ wx b8010000004839ca7f
pi 3
EOF
EXPECT=<<EOF
mov eax, 1
mov eax, 0x01
cmp rdx, rcx
jg 0xa
jnle 0xa
EOF
RUN
@ -466,7 +466,7 @@ wx b8010000004839ca7f
pdj 3
EOF
EXPECT=<<EOF
[{"offset":0,"val":1,"esil":"1,rax,=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":5,"opcode":"mov eax, 1","disasm":"mov eax, 1","bytes":"b801000000","family":"cpu","type":"mov","reloc":false,"type_num":9,"type2_num":0},{"offset":5,"esil":"rcx,rdx,==,$z,zf,:=,64,$b,cf,:=,$p,pf,:=,63,$s,sf,:=,rcx,0x8000000000000000,-,!,63,$o,^,of,:=,3,$b,af,:=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":3,"opcode":"cmp rdx, rcx","disasm":"cmp rdx, rcx","bytes":"4839ca","family":"cpu","type":"cmp","reloc":false,"type_num":15,"type2_num":0},{"offset":8,"esil":"sf,of,!,^,zf,!,&,?{,10,rip,=,}","refptr":false,"fcn_addr":0,"fcn_last":0,"size":2,"opcode":"jg 0xa","disasm":"jg 0xa","bytes":"7f00","family":"cpu","type":"cjmp","reloc":false,"type_num":2147483649,"type2_num":0,"jump":10,"fail":10}]
[{"offset":0,"val":1,"esil":"1,rax,=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":5,"opcode":"mov eax, 0x01","disasm":"mov eax, 0x01","bytes":"b801000000","family":"cpu","type":"mov","reloc":false,"type_num":9,"type2_num":0},{"offset":5,"esil":"rcx,rdx,==,$z,zf,:=,64,$b,cf,:=,$p,pf,:=,63,$s,sf,:=,rcx,0x8000000000000000,-,!,63,$o,^,of,:=,3,$b,af,:=","refptr":false,"fcn_addr":0,"fcn_last":0,"size":3,"opcode":"cmp rdx, rcx","disasm":"cmp rdx, rcx","bytes":"4839ca","family":"cpu","type":"cmp","reloc":false,"type_num":15,"type2_num":0},{"offset":8,"esil":"sf,of,!,^,zf,!,&,?{,10,rip,=,}","refptr":false,"fcn_addr":0,"fcn_last":0,"size":2,"opcode":"jnle 0xa","disasm":"jnle 0xa","bytes":"7f00","family":"cpu","type":"cjmp","reloc":false,"type_num":2147483649,"type2_num":0,"jump":10,"fail":10}]
EOF
RUN
@ -479,12 +479,12 @@ wx b8010000004839ca7f00b8010000004839ca7f00
pi 6
EOF
EXPECT=<<EOF
mov eax, 1
mov eax, 0x01
cmp rdx, rcx
jg 0xa
mov eax, 1
jnle 0xa
mov eax, 0x01
cmp rdx, rcx
jg 0x14
jnle 0x14
EOF
RUN
@ -497,9 +497,9 @@ wx b8010000004839ca7f00
pi -3 @ 10
EOF
EXPECT=<<EOF
mov eax, 1
mov eax, 0x01
cmp rdx, rcx
jg 0xa
jnle 0xa
EOF
RUN
@ -521,8 +521,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 0,
"size": 5,
"opcode": "mov eax, 1",
"disasm": "mov eax, 1",
"opcode": "mov eax, 0x01",
"disasm": "mov eax, 0x01",
"bytes": "b801000000",
"family": "cpu",
"type": "mov",
@ -553,8 +553,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 0,
"size": 2,
"opcode": "jg 0xa",
"disasm": "jg 0xa",
"opcode": "jnle 0xa",
"disasm": "jnle 0xa",
"bytes": "7f00",
"family": "cpu",
"type": "cjmp",
@ -758,7 +758,7 @@ mov rbp, rsp
sub rsp, 0x20
mov dword [var_1ch], edi
mov qword [var_28h], rsi
mov dword [var_ch], 0
mov dword [var_ch], 0x00
jmp 0x400523
EOF
RUN
@ -775,7 +775,7 @@ EXPECT=<<EOF
sub rsp, 0x20
mov dword [var_1ch], edi
mov qword [var_28h], rsi
mov dword [var_ch], 0
mov dword [var_ch], 0x00
jmp 0x400523
EOF
RUN

40
test/db/cmd/cmd_px
View file

@ -222,15 +222,15 @@ echo ===
pxr 24 @ 0x00600ae0+32
EOF
EXPECT=<<EOF
0x00600ae0 0x000000000040055e ^.@..... @ reloc.printf 4195678 .plt R X 'push 0'
0x00600ae8 0x000000000040056e n.@..... @ reloc.puts 4195694 .plt R X 'push 1'
0x00600af0 0x000000000040057e ~.@..... @ reloc.__libc_start_main 4195710 .plt R X 'push 2'
0x00600af8 0x000000000040058e ..@..... @ reloc.fgets 4195726 .plt R X 'push 3'
0x00600b00 0x000000000040059e ..@..... @ reloc.strcmp 4195742 .plt R X 'push 4'
0x00600b08 0x00000000004005ae ..@..... @ reloc.fflush 4195758 .plt R X 'push 5'
0x00600ae0 0x000000000040055e ^.@..... @ reloc.printf 4195678 .plt R X 'push 0x00'
0x00600ae8 0x000000000040056e n.@..... @ reloc.puts 4195694 .plt R X 'push 0x01'
0x00600af0 0x000000000040057e ~.@..... @ reloc.__libc_start_main 4195710 .plt R X 'push 0x02'
0x00600af8 0x000000000040058e ..@..... @ reloc.fgets 4195726 .plt R X 'push 0x03'
0x00600b00 0x000000000040059e ..@..... @ reloc.strcmp 4195742 .plt R X 'push 0x04'
0x00600b08 0x00000000004005ae ..@..... @ reloc.fflush 4195758 .plt R X 'push 0x05'
===
0x00600b00 0x000000000040059e ..@..... @ reloc.strcmp 4195742 .plt R X 'push 4'
0x00600b08 0x00000000004005ae ..@..... @ reloc.fflush 4195758 .plt R X 'push 5'
0x00600b00 0x000000000040059e ..@..... @ reloc.strcmp 4195742 .plt R X 'push 0x04'
0x00600b08 0x00000000004005ae ..@..... @ reloc.fflush 4195758 .plt R X 'push 0x05'
0x00600b10 ..[ null bytes ].. 00000000 loc.__data_start
EOF
RUN
@ -246,18 +246,18 @@ pxr 32@ 0x00600ae0
pxr2j 16@ 0x00600ae0~{}
EOF
EXPECT=<<EOF
0x00600ae0 0x0040055e ^.@. @ reloc.printf 4195678 .plt R X 'push 0'
0x00600ae0 0x0040055e ^.@. @ reloc.printf 4195678 .plt R X 'push 0x00'
0x00600ae4 ..[ null bytes ].. 00000000
0x00600ae8 0x0040056e n.@. @ reloc.puts 4195694 .plt R X 'push 1'
0x00600ae8 0x0040056e n.@. @ reloc.puts 4195694 .plt R X 'push 0x01'
0x00600aec ..[ null bytes ].. 00000000
0x00600af0 0x0040057e ~.@. @ reloc.__libc_start_main 4195710 .plt R X 'push 2'
0x00600af0 0x0040057e ~.@. @ reloc.__libc_start_main 4195710 .plt R X 'push 0x02'
0x00600af4 ..[ null bytes ].. 00000000
0x00600af8 0x0040058e ..@. @ reloc.fgets 4195726 .plt R X 'push 3'
0x00600af8 0x0040058e ..@. @ reloc.fgets 4195726 .plt R X 'push 0x03'
0x00600afc ..[ null bytes ].. 00000000
0x00600ae0 0x000000000040055e ^.@..... @ reloc.printf 4195678 .plt R X 'push 0'
0x00600ae8 0x000000000040056e n.@..... @ reloc.puts 4195694 .plt R X 'push 1'
0x00600af0 0x000000000040057e ~.@..... @ reloc.__libc_start_main 4195710 .plt R X 'push 2'
0x00600af8 0x000000000040058e ..@..... @ reloc.fgets 4195726 .plt R X 'push 3'
0x00600ae0 0x000000000040055e ^.@..... @ reloc.printf 4195678 .plt R X 'push 0x00'
0x00600ae8 0x000000000040056e n.@..... @ reloc.puts 4195694 .plt R X 'push 0x01'
0x00600af0 0x000000000040057e ~.@..... @ reloc.__libc_start_main 4195710 .plt R X 'push 0x02'
0x00600af8 0x000000000040058e ..@..... @ reloc.fgets 4195726 .plt R X 'push 0x03'
0x00600ae0 5e05 ^. @ reloc.printf 1374
0x00600ae2 4000 @. 64 ascii ('@')
0x00600ae4 0000 ..
@ -274,13 +274,13 @@ EXPECT=<<EOF
0x00600afa 4000 @. 64 ascii ('@')
0x00600afc 0000 ..
0x00600afe 0000 ..
0x00600ae0 0x0040055e ^.@. @ reloc.printf .plt R X 'push 0'
0x00600ae0 0x0040055e ^.@. @ reloc.printf .plt R X 'push 0x00'
0x00600ae4 ..[ null bytes ].. 00000000
0x00600ae8 0x0040056e n.@. @ reloc.puts .plt R X 'push 1'
0x00600ae8 0x0040056e n.@. @ reloc.puts .plt R X 'push 0x01'
0x00600aec ..[ null bytes ].. 00000000
0x00600af0 0x0040057e ~.@. @ reloc.__libc_start_main .plt R X 'push 2'
0x00600af0 0x0040057e ~.@. @ reloc.__libc_start_main .plt R X 'push 0x02'
0x00600af4 ..[ null bytes ].. 00000000
0x00600af8 0x0040058e ..@. @ reloc.fgets .plt R X 'push 3'
0x00600af8 0x0040058e ..@. @ reloc.fgets .plt R X 'push 0x03'
0x00600afc ..[ null bytes ].. 00000000
[
{

74
test/db/cmd/cmd_rop
View file

@ -39,28 +39,28 @@ e asm.bits=32
EOF
EXPECT=<<EOF
0x000000b4 cd80 int 0x80
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 15
0x000000b5 80b801000000b9 cmp byte [eax + 1], 0xb9
0x000000b5 80b801000000b9 cmp byte [eax+0x01], 0xb9
0x000000bc 0000 add byte [eax], al
0x000000be 0000 add byte [eax], al
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 14
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 13
0x000000b7 0100 add dword [eax], eax
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 12
@ -72,7 +72,7 @@ Gadget size: 12
Gadget size: 11
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 10
@ -82,7 +82,7 @@ Gadget size: 10
0x000000c2 c3 ret
Gadget size: 9
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 8
@ -118,32 +118,32 @@ e asm.bits=32
EOF
EXPECT=<<EOF
0x000000b4 cd80 int 0x80
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 15
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 13
0x000000b7 0100 add dword [eax], eax
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 12
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 10
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 8
@ -160,14 +160,14 @@ e asm.bits=32
/Rq
EOF
EXPECT=<<EOF
0x000000b4: int 0x80; mov eax, 1; mov ecx, 0; int 0x80; ret;
0x000000b5: cmp byte [eax + 1], 0xb9; add byte [eax], al; add byte [eax], al; int 0x80; ret;
0x000000b6: mov eax, 1; mov ecx, 0; int 0x80; ret;
0x000000b7: add dword [eax], eax; add byte [eax], al; mov ecx, 0; int 0x80; ret;
0x000000b4: int 0x80; mov eax, 0x01; mov ecx, 0x00; int 0x80; ret;
0x000000b5: cmp byte [eax+0x01], 0xb9; add byte [eax], al; add byte [eax], al; int 0x80; ret;
0x000000b6: mov eax, 0x01; mov ecx, 0x00; int 0x80; ret;
0x000000b7: add dword [eax], eax; add byte [eax], al; mov ecx, 0x00; int 0x80; ret;
0x000000b8: add byte [eax], al; add byte [ecx], bh; int 0x80; ret;
0x000000b9: add byte [eax], al; mov ecx, 0; int 0x80; ret;
0x000000b9: add byte [eax], al; mov ecx, 0x00; int 0x80; ret;
0x000000ba: add byte [ecx], bh; int 0x80; ret;
0x000000bb: mov ecx, 0; int 0x80; ret;
0x000000bb: mov ecx, 0x00; int 0x80; ret;
0x000000bc: add byte [eax], al; add byte [eax], al; int 0x80; ret;
0x000000be: add byte [eax], al; int 0x80; ret;
0x000000c0: int 0x80; ret;
@ -185,21 +185,21 @@ e asm.bits=32
EOF
EXPECT=<<EOF
0x000000b4 cd80 int 0x80
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 15
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 13
0x000000b7 0100 add dword [eax], eax
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 12
@ -211,7 +211,7 @@ Gadget size: 12
Gadget size: 11
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 10
@ -221,7 +221,7 @@ Gadget size: 10
0x000000c2 c3 ret
Gadget size: 9
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 8
@ -238,7 +238,7 @@ e asm.bits=32
/Rj ecx
EOF
EXPECT=<<EOF
[{"opcodes":[{"offset":180,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":182,"size":5,"opcode":"mov eax, 1","type":"mov"},{"offset":187,"size":5,"opcode":"mov ecx, 0","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":15},{"opcodes":[{"offset":182,"size":5,"opcode":"mov eax, 1","type":"mov"},{"offset":187,"size":5,"opcode":"mov ecx, 0","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":13},{"opcodes":[{"offset":183,"size":2,"opcode":"add dword [eax], eax","type":"add"},{"offset":185,"size":2,"opcode":"add byte [eax], al","type":"add"},{"offset":187,"size":5,"opcode":"mov ecx, 0","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":12},{"opcodes":[{"offset":184,"size":2,"opcode":"add byte [eax], al","type":"add"},{"offset":186,"size":6,"opcode":"add byte [ecx], bh","type":"add"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":11},{"opcodes":[{"offset":185,"size":2,"opcode":"add byte [eax], al","type":"add"},{"offset":187,"size":5,"opcode":"mov ecx, 0","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":10},{"opcodes":[{"offset":186,"size":6,"opcode":"add byte [ecx], bh","type":"add"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":9},{"opcodes":[{"offset":187,"size":5,"opcode":"mov ecx, 0","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":8}]
[{"opcodes":[{"offset":180,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":182,"size":5,"opcode":"mov eax, 0x01","type":"mov"},{"offset":187,"size":5,"opcode":"mov ecx, 0x00","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":15},{"opcodes":[{"offset":182,"size":5,"opcode":"mov eax, 0x01","type":"mov"},{"offset":187,"size":5,"opcode":"mov ecx, 0x00","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":13},{"opcodes":[{"offset":183,"size":2,"opcode":"add dword [eax], eax","type":"add"},{"offset":185,"size":2,"opcode":"add byte [eax], al","type":"add"},{"offset":187,"size":5,"opcode":"mov ecx, 0x00","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":12},{"opcodes":[{"offset":184,"size":2,"opcode":"add byte [eax], al","type":"add"},{"offset":186,"size":6,"opcode":"add byte [ecx], bh","type":"add"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":11},{"opcodes":[{"offset":185,"size":2,"opcode":"add byte [eax], al","type":"add"},{"offset":187,"size":5,"opcode":"mov ecx, 0x00","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":10},{"opcodes":[{"offset":186,"size":6,"opcode":"add byte [ecx], bh","type":"add"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":9},{"opcodes":[{"offset":187,"size":5,"opcode":"mov ecx, 0x00","type":"mov"},{"offset":192,"size":2,"opcode":"int 0x80","type":"swi"},{"offset":194,"size":1,"opcode":"ret","type":"ret"}],"retaddr":194,"size":8}]
EOF
RUN
@ -252,28 +252,28 @@ e asm.bits=32
EOF
EXPECT=<<EOF
0x000000b4 cd80 int 0x80
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 15
0x000000b5 80b801000000b9 cmp byte [eax + 1], 0xb9
0x000000b5 80b801000000b9 cmp byte [eax+0x01], 0xb9
0x000000bc 0000 add byte [eax], al
0x000000be 0000 add byte [eax], al
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 14
0x000000b6 b801000000 mov eax, 1
0x000000bb b900000000 mov ecx, 0
0x000000b6 b801000000 mov eax, 0x01
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 13
0x000000b7 0100 add dword [eax], eax
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 12
@ -285,7 +285,7 @@ Gadget size: 12
Gadget size: 11
0x000000b9 0000 add byte [eax], al
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 10
@ -295,7 +295,7 @@ Gadget size: 10
0x000000c2 c3 ret
Gadget size: 9
0x000000bb b900000000 mov ecx, 0
0x000000bb b900000000 mov ecx, 0x00
0x000000c0 cd80 int 0x80
0x000000c2 c3 ret
Gadget size: 8

13
test/db/cmd/cmd_search
View file

@ -366,19 +366,19 @@ e scr.color=false
q
EOF
EXPECT=<<EOF
0x00000000 83c408 add esp, 8
0x00000000 83c408 add esp, 0x08
0x00000003 5b pop ebx
0x00000004 5d pop ebp
0x00000005 c3 ret
Gadget size: 6
0x00000001 c408 les ecx, [eax]
0x00000001 c408 les ecx, fword [eax]
0x00000003 5b pop ebx
0x00000004 5d pop ebp
0x00000005 c3 ret
Gadget size: 5
0x00000002 085b5d or byte [ebx + 0x5d], bl
0x00000002 085b5d or byte [ebx+0x5d], bl
0x00000005 c3 ret
Gadget size: 4
@ -409,7 +409,7 @@ e scr.color=false
q
EOF
EXPECT=<<EOF
0x00000002 085b5d or byte [ebx + 0x5d], bl
0x00000002 085b5d or byte [ebx+0x5d], bl
0x00000005 c3 ret
Gadget size: 4
@ -492,7 +492,7 @@ q
EOF
EXPECT=<<EOF
0x004019d2 # 2: ror esp, cl
0x004019d5 # 2: ror bh, 1
0x004019d5 # 2: ror bh, 0x01
0x004019da # 3: ror ebp, 0xe5
EOF
RUN
@ -653,7 +653,8 @@ e search.from=0x100
e search.to=0x103
/x 41424344
EOF
EXPECT=
EXPECT=<<EOF
EOF
RUN
NAME=search range hex @(A..B)

18
test/db/cmd/cmd_search_g
View file

@ -11,24 +11,24 @@ echo --Follow calls--
EOF
EXPECT=<<EOF
/ entry.fini0();
| 0x08048380 cmp byte [section..bss], 0 ; [0x8049648:1]=0
| ,=< 0x08048387 jne 0x804839c
| 0x08048380 cmp byte [section..bss], 0x00 ; [0x8049648:1]=0
| ,=< 0x08048387 jnz 0x804839c
| | 0x08048389 push ebp
| | 0x0804838a mov ebp, esp
| | 0x0804838c sub esp, 8
| | 0x0804838c sub esp, 0x08
| | 0x0804838f call fcn.08048310
| | 0x08048394 mov byte [section..bss], 1 ; [0x8049648:1]=0
| | 0x08048394 mov byte [section..bss], 0x01 ; [0x8049648:1]=0
| | 0x0804839b leave
\ `-> 0x0804839c repz ret
\ `-> 0x0804839c ret
; CALL XREF from entry.fini0 @ 0x804838f
/ fcn.08048310();
| 0x08048310 mov eax, data.0804964b ; 0x804964b
| 0x08048315 sub eax, section..bss ; 0x8049648
| 0x0804831a cmp eax, 6 ; 6
| 0x0804831a cmp eax, 0x06 ; 6
| ,=< 0x0804831d jbe 0x8048339
| | 0x0804831f mov eax, 0
| | 0x0804831f mov eax, 0x00
| | 0x08048324 test eax, eax
| ,==< 0x08048326 je 0x8048339
| ,==< 0x08048326 jz 0x8048339
| || 0x08048328 push ebp
| || 0x08048329 mov ebp, esp
| || 0x0804832b sub esp, 0x14
@ -36,7 +36,7 @@ EXPECT=<<EOF
| || 0x08048333 call eax
| || 0x08048335 add esp, 0x10
| || 0x08048338 leave
\ ``-> 0x08048339 repz ret
\ ``-> 0x08048339 ret
--No calls--
pdb @@= 0x08048380 0x0804839c
pdb @@= 0x08048380 0x08048389 0x0804839c

2
test/db/cmd/cmd_search_hit
View file

@ -108,7 +108,7 @@ wa "add esp,8;pop ebx; pop ebp; ret"
/a add esp, 8
EOF
EXPECT=<<EOF
add esp, 8
add esp, 0x08
pop ebx
pop ebp
ret

16
test/db/cmd/cmd_seek
View file

@ -235,30 +235,30 @@ EXPECT=<<EOF
--- From 0x560e7d ---
-- 1 --
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
0x560e7a
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
-- 2 --
0x00560e78 d41b aam 0x1b
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
0x560e78
0x00560e78 d41b aam 0x1b
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
--- From 0x560e7c ---
-- 1 --
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
0x560e7a
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
-- 2 --
0x00560e78 d41b aam 0x1b
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
0x560e78
0x00560e78 d41b aam 0x1b
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
--- From 0x560e7a ---

30
test/db/cmd/cmd_signature
View file

@ -20,7 +20,7 @@ Found 1 FLIRT signatures via bins/other/sigs/libc-v7.sig
| ; arg int64_t arg_8h @ stack + 0x8
| 0x004e2420 push r14
| 0x004e2422 push r13
| 0x004e2424 mov eax, 0
| 0x004e2424 mov eax, 0x00
| 0x004e2429 push r12
| 0x004e242b push rbp
| 0x004e242c mov r12, r8 ; arg5
@ -420,26 +420,26 @@ EXPECT=<<EOF
| 0x004011bd mov qword [var_10h], rax
| 0x004011c1 xor eax, eax
| 0x004011c3 mov rax, qword [var_78h]
| 0x004011c7 add rax, 8
| 0x004011c7 add rax, 0x08
| 0x004011cb mov rax, qword [rax]
| 0x004011ce mov rdi, rax
| 0x004011d1 call flirt.atoi
| 0x004011d6 mov edx, eax
| 0x004011d8 lea rax, [var_68h]
| 0x004011d8 lea rax, qword [var_68h]
| 0x004011dc mov ecx, edx
| 0x004011de lea rdx, str.Hello__d ; segment.LOAD2
| 0x004011de lea rdx, qword str.Hello__d ; segment.LOAD2
| ; 0x404000 ; "Hello %d\n"
| 0x004011e5 mov esi, 0x50 ; 'P' ; 80
| 0x004011ea mov rdi, rax
| 0x004011ed mov eax, 0
| 0x004011ed mov eax, 0x00
| 0x004011f2 call flirt.snprintf
| 0x004011f7 lea rax, [var_68h]
| 0x004011f7 lea rax, qword [var_68h]
| 0x004011fb mov rdi, rax
| 0x004011fe call flirt.puts
| 0x00401203 mov eax, 0
| 0x00401203 mov eax, 0x00
| 0x00401208 mov rdx, qword [var_10h]
| 0x0040120c sub rdx, qword fs:[0x28]
| ,=< 0x00401215 je 0x40121c
| ,=< 0x00401215 jz 0x40121c
| | 0x00401217 call fcn.0040146f
| `-> 0x0040121c leave
\ 0x0040121d ret
@ -473,26 +473,26 @@ EXPECT=<<EOF
| 0x004011bd mov qword [var_10h], rax
| 0x004011c1 xor eax, eax
| 0x004011c3 mov rax, qword [var_78h]
| 0x004011c7 add rax, 8
| 0x004011c7 add rax, 0x08
| 0x004011cb mov rax, qword [rax]
| 0x004011ce mov rdi, rax
| 0x004011d1 call flirt.atoi
| 0x004011d6 mov edx, eax
| 0x004011d8 lea rax, [var_68h]
| 0x004011d8 lea rax, qword [var_68h]
| 0x004011dc mov ecx, edx
| 0x004011de lea rdx, str.Hello__d ; segment.LOAD2
| 0x004011de lea rdx, qword str.Hello__d ; segment.LOAD2
| ; 0x404000 ; "Hello %d\n"
| 0x004011e5 mov esi, 0x50 ; 'P' ; 80
| 0x004011ea mov rdi, rax
| 0x004011ed mov eax, 0
| 0x004011ed mov eax, 0x00
| 0x004011f2 call flirt.snprintf
| 0x004011f7 lea rax, [var_68h]
| 0x004011f7 lea rax, qword [var_68h]
| 0x004011fb mov rdi, rax
| 0x004011fe call flirt.puts
| 0x00401203 mov eax, 0
| 0x00401203 mov eax, 0x00
| 0x00401208 mov rdx, qword [var_10h]
| 0x0040120c sub rdx, qword fs:[0x28]
| ,=< 0x00401215 je 0x40121c
| ,=< 0x00401215 jz 0x40121c
| | 0x00401217 call fcn.0040146f
| `-> 0x0040121c leave
\ 0x0040121d ret

4
test/db/cmd/display_flag
View file

@ -13,7 +13,7 @@ f. loop1 @ 0000:0009
pd 1 @ 0000:000d
EOF
EXPECT=<<EOF
| `=< 0000:000d e2fa loop 9 ; fcn1.loop1
| `=< 0000:000d e2fa loop 0x9 ; fcn1.loop1
EOF
RUN
@ -32,7 +32,7 @@ pd 1 @ 9
EOF
EXPECT=<<EOF
| .loop1:
| 0000:0009 6683. cmp ebx, 2
| 0000:0009 6683. cmp ebx, 0x02
EOF
RUN

14
test/db/cmd/dwarf
View file

@ -569,7 +569,7 @@ global char [5] anonymous_var_0x59 @ 0x2010
global char [19] anonymous_var_0xb4 @ 0x2021
global const float qwe @ 0x2034
global char * bla @ 0x4088
dbg.fn2 0x11b4 [DATA] lea rax, obj.fn2.qwe
dbg.fn2 0x11b4 [DATA] lea rax, qword obj.fn2.qwe
dbg.fn1 0x116a [DATA] mov qword [obj.fn1.bla], rax
dbg.fn1 0x1171 [DATA] mov rsi, qword [obj.fn1.bla]
fn1
@ -3165,24 +3165,24 @@ EXPECT=<<EOF
| ; var SmallInt i @ stack - 0x1c
| 0x00401980 55 push rbp ; unit p$mozgkigyo palya(smallint,smallint)
| 0x00401981 4889e5 mov rbp, rsp
| 0x00401984 488d6424d0 lea rsp, [rsp - 0x30]
| 0x00401984 488d6424d0 lea rsp, qword [rsp-0x30]
| 0x00401989 48895dd8 mov qword [var_30h], rbx
| 0x0040198d 4c8965e0 mov qword [var_28h], r12
| 0x00401991 66897df8 mov word [mag], di
| 0x00401995 668975f0 mov word [szel], si
| 0x00401999 b801000000 mov eax, 1
| 0x0040199e bf01000000 mov edi, 1 ; int64_t arg2
| 0x00401999 b801000000 mov eax, 0x01
| 0x0040199e bf01000000 mov edi, 0x01 ; int64_t arg2
| 0x004019a3 89c6 mov esi, eax ; int64_t arg_8h
| 0x004019a5 e8b6a10200 call sym.unit_crt_gotoxy_tcrtcoord_tcrtcoord
| 0x004019aa 66448b65f0 mov r12w, word [szel]
| 0x004019af 66c745ec0100 mov word [i], 1
| 0x004019af 66c745ec0100 mov word [i], 0x01
| 0x004019b5 66443b65ec cmp r12w, word [i]
| ,=< 0x004019ba 7c45 jl 0x401a01
| | 0x004019bc 66816dec0100 sub word [i], 1
| | 0x004019bc 66816dec0100 sub word [i], 0x01
| | 0x004019c2 66666690 nop
| | 0x004019c6 6690 nop
| | ; CODE XREF from dbg.palya @ 0x4019ff
| | 0x004019c8 668145ec0100 add word [i], 1
| | 0x004019c8 668145ec0100 add word [i], 0x01
| | 0x004019ce e82d280200 call sym.fpc_get_output
EOF
RUN

4
test/db/cmd/feat_astabs
View file

@ -11,7 +11,7 @@ wx 410fb744245883f80c
pd 2
EOF
EXPECT=<<EOF
0x00000000 410fb7442458 movzx eax, word [r12 + 0x58]
0x00000006 83f80c cmp eax, 0xc
0x00000000 410fb7442458 movzx eax, word [r12+0x58]
0x00000006 83f80c cmp eax, 0x0c
EOF
RUN

4
test/db/cmd/feat_foreach
View file

@ -15,6 +15,8 @@ e search.in=bin.sections
%v $$ @@c:/ad fs:[ra
EOF
EXPECT=<<EOF
0x1000049d4
0x1000049d5
0x100005078
EOF
RUN
@ -26,6 +28,8 @@ e search.in=bin.sections
%v $$ @@c:/ao fs:[ra
EOF
EXPECT=<<EOF
0x1000049d4
0x1000049d5
0x100004cd7
0x100004d95
0x100004e1d

2
test/db/cmd/feat_grep
View file

@ -303,7 +303,7 @@ e asm.bytes=true
pd 40~0x004005fe
EOF
EXPECT=<<EOF
`-> 0x004005fe 4883c408 add rsp, 8
`-> 0x004005fe 4883c408 add rsp, 0x08
EOF
RUN

28
test/db/cmd/lea_intel
View file

@ -8,35 +8,35 @@ s 0x00402c43
pd 30
EOF
EXPECT=<<EOF
0x00402c43 lea rax, [rbp - 0xa0] ; ezpz.cpp:265
0x00402c43 lea rax, qword [rbp-0xa0] ; ezpz.cpp:265
0x00402c4a mov rdi, rax
0x00402c4d call sym.MD5_Init_MD5_CTX
0x00402c52 mov eax, dword [rbp - 0xb4] ; ezpz.cpp:266
0x00402c58 add eax, 1
0x00402c52 mov eax, dword [rbp-0xb4] ; ezpz.cpp:266
0x00402c58 add eax, 0x01
0x00402c5b movsxd rdx, eax
0x00402c5e lea rax, [rbp - 0xa0]
0x00402c5e lea rax, qword [rbp-0xa0]
0x00402c65 mov esi, obj.Password
0x00402c6a mov rdi, rax
0x00402c6d call sym.MD5_Update_MD5_CTX___void_const___unsigned_long
0x00402c72 lea rdx, [rbp - 0xa0] ; ezpz.cpp:267
0x00402c79 lea rax, [rbp - 0xb0]
0x00402c72 lea rdx, qword [rbp-0xa0] ; ezpz.cpp:267
0x00402c79 lea rax, qword [rbp-0xb0]
0x00402c80 mov rsi, rdx
0x00402c83 mov rdi, rax
0x00402c86 call sym.MD5_Final_unsigned_char___MD5_CTX
0x00402c8b mov eax, dword [rbp - 0xb4] ; ezpz.cpp:269
0x00402c8b mov eax, dword [rbp-0xb4] ; ezpz.cpp:269
0x00402c91 cdqe
0x00402c93 shl rax, 4
0x00402c97 lea rcx, [rax + obj.GoodHashes]
0x00402c9e lea rax, [rbp - 0xb0]
0x00402c93 shl rax, 0x04
0x00402c97 lea rcx, qword [rax+obj.GoodHashes]
0x00402c9e lea rax, qword [rbp-0xb0]
0x00402ca5 mov edx, 0x10
0x00402caa mov rsi, rcx
0x00402cad mov rdi, rax
0x00402cb0 call sym.imp.memcmp
0x00402cb5 test eax, eax
0x00402cb7 je 0x402cc2
0x00402cb9 mov byte [obj.DrawGoodWork], 0 ; ezpz.cpp:270
0x00402cb7 jz 0x402cc2
0x00402cb9 mov byte [obj.DrawGoodWork], 0x00 ; ezpz.cpp:270
0x00402cc0 jmp 0x402cdd
0x00402cc2 add dword [rbp - 0xb4], 1 ; ezpz.cpp:263
0x00402cc9 cmp dword [rbp - 0xb4], 0x14
0x00402cc2 add dword [rbp-0xb4], 0x01 ; ezpz.cpp:263
0x00402cc9 cmp dword [rbp-0xb4], 0x14
EOF
RUN

102
test/db/cmd/midbb
View file

@ -22,7 +22,7 @@ EXPECT=<<EOF
| 0x00560e75 push es
| 0x00560e76 cmp edx, esp
| 0x00560e78 aam 0x1b
| 0x00560e7a ~ add byte [ebp + 0x52505e96], al
| 0x00560e7a ~ add byte [ebp+0x52505e96], al
| `-> 0x00560e7d pop esi
| 0x00560e7e push eax
| 0x00560e7f push edx
@ -30,22 +30,22 @@ EXPECT=<<EOF
| 0x00560e85 mov ebx, 0x4fd160dd
| 0x00560e8a in al, dx
| 0x00560e8b mov esp, 0x60bdf441
| 0x00560e90 lodsd eax, dword [esi]
,==< 0x00560e91 ja 0x560ed9
| 0x00560e90 lodsd
,==< 0x00560e91 jnbe 0x560ed9
|| 0x00560e93 aaa
|| 0x00560e94 sahf
|| 0x00560e95 ~ mov edx, 0x14e9310f
| |`-> 0x00560e96 rdtsc
| | 0x00560e98 jmp 0x560eb1
| 0x00560e9d test al, 0x36
| 0x00560e9f fcom qword [edx + 0x64]
| 0x00560ea2 xlatb
| 0x00560e9f fcom qword [edx+0x64]
| 0x00560ea2 xlat
| 0x00560ea3 push 0x27
| 0x00560ea5 sub esp, edx
| 0x00560ea7 mov eax, dword [0xe8c1cf5d]
|,=< 0x00560eac jle 0x560f29
|| 0x00560eae inc ecx
|| 0x00560eaf ~ mov byte [eax + 0x5a], dl
|| 0x00560eaf ~ mov byte [eax+0x5a], dl
| || 0x00560eb1 pop edx
| || 0x00560eb2 pop eax
@ -58,25 +58,25 @@ EXPECT=<<EOF
| 0x00560e75 push es
| 0x00560e76 cmp edx, esp
| 0x00560e78 aam 0x1b
| 0x00560e7a add byte [ebp + 0x52505e96], al
| 0x00560e7a add byte [ebp+0x52505e96], al
| ,=< 0x00560e80 jmp 0x560e96
| 0x00560e85 mov ebx, 0x4fd160dd
| 0x00560e8a in al, dx
| 0x00560e8b mov esp, 0x60bdf441
| 0x00560e90 lodsd eax, dword [esi]
,==< 0x00560e91 ja 0x560ed9
| 0x00560e90 lodsd
,==< 0x00560e91 jnbe 0x560ed9
|| 0x00560e93 aaa
|| 0x00560e94 sahf
|| 0x00560e95 mov edx, 0x14e9310f
| | 0x00560e9a add byte [eax], al
| | 0x00560e9c add byte [eax + 0x6452dc36], ch
| 0x00560ea2 xlatb
| | 0x00560e9c add byte [eax+0x6452dc36], ch
| 0x00560ea2 xlat
| 0x00560ea3 push 0x27
| 0x00560ea5 sub esp, edx
| 0x00560ea7 mov eax, dword [0xe8c1cf5d]
|,=< 0x00560eac jle 0x560f29
|| 0x00560eae inc ecx
|| 0x00560eaf mov byte [eax + 0x5a], dl
|| 0x00560eaf mov byte [eax+0x5a], dl
| || 0x00560eb2 pop eax
EOF
RUN
@ -118,8 +118,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 16,
"size": 5,
"opcode": "nop dword [rax + rax]",
"disasm": "nop dword [rax + rax]",
"opcode": "nop dword [rax+rax*1], eax",
"disasm": "nop dword [rax+rax*1], eax",
"bytes": "0f1f440000",
"family": "cpu",
"type": "nop",
@ -154,9 +154,9 @@ EXPECT=<<EOF
},
{
"offset": 5,
"ptr": 3238002721,
"val": 3238002721,
"esil": "3238002721,rax,=",
"ptr": 18446744072652587041,
"val": 18446744072652587041,
"esil": "18446744072652587041,rax,=",
"refptr": false,
"fcn_addr": 0,
"fcn_last": 15,
@ -224,8 +224,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 3",
"disasm": "jmp 3",
"opcode": "jmp 0x3",
"disasm": "jmp 0x3",
"bytes": "ebf0",
"family": "cpu",
"type": "jmp",
@ -252,8 +252,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 14,
"size": 5,
"opcode": "nop dword [rax + rax]",
"disasm": "nop dword [rax + rax]",
"opcode": "nop dword [rax+rax*1], eax",
"disasm": "nop dword [rax+rax*1], eax",
"bytes": "0f1f440000",
"family": "cpu",
"type": "nop",
@ -266,9 +266,9 @@ EXPECT=<<EOF
},
{
"offset": 5,
"ptr": 3238002721,
"val": 3238002721,
"esil": "3238002721,rax,=",
"ptr": 18446744072652587041,
"val": 18446744072652587041,
"esil": "18446744072652587041,rax,=",
"refptr": false,
"fcn_addr": 0,
"fcn_last": 14,
@ -289,8 +289,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 9",
"disasm": "jmp 9",
"opcode": "jmp 0x9",
"disasm": "jmp 0x9",
"bytes": "ebfd",
"family": "cpu",
"type": "jmp",
@ -336,8 +336,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 3",
"disasm": "jmp 3",
"opcode": "jmp 0x3",
"disasm": "jmp 0x3",
"bytes": "ebf0",
"family": "cpu",
"type": "jmp",
@ -368,8 +368,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 14,
"size": 5,
"opcode": "nop dword [rax + rax]",
"disasm": "nop dword [rax + rax]",
"opcode": "nop dword [rax+rax*1], eax",
"disasm": "nop dword [rax+rax*1], eax",
"bytes": "0f1f440000",
"family": "cpu",
"type": "nop",
@ -404,9 +404,9 @@ EXPECT=<<EOF
},
{
"offset": 5,
"ptr": 3238002721,
"val": 3238002721,
"esil": "3238002721,rax,=",
"ptr": 18446744072652587041,
"val": 18446744072652587041,
"esil": "18446744072652587041,rax,=",
"refptr": false,
"fcn_addr": 0,
"fcn_last": 14,
@ -427,8 +427,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 9",
"disasm": "jmp 9",
"opcode": "jmp 0x9",
"disasm": "jmp 0x9",
"bytes": "ebfd",
"family": "cpu",
"type": "jmp",
@ -497,8 +497,8 @@ EXPECT=<<EOF
"fcn_addr": 0,
"fcn_last": 17,
"size": 2,
"opcode": "jmp 3",
"disasm": "jmp 3",
"opcode": "jmp 0x3",
"disasm": "jmp 0x3",
"bytes": "ebf0",
"family": "cpu",
"type": "jmp",
@ -536,19 +536,19 @@ pdq 6
EOF
EXPECT=<<EOF
0x00000000 fcn.00000000:
0x00000000 0f1f440000 nop dword [rax + rax]
0x00000000 0f1f440000 nop dword [rax+rax*1], eax
0x00000003 0000 add byte [rax], al
0x00000005 b8210000c1 mov eax, 0xc1000021
0x00000009 c1ebfd shr ebx, 0xfd
0x0000000c bb2c000000 mov ebx, 0x2c
0x00000011 ebf0 jmp 3
0x00000011 ebf0 jmp 0x3
0x00000000 fcn.00000000:
0x00000000 0f1f440000 nop dword [rax + rax]
0x00000000 0f1f440000 nop dword [rax+rax*1], eax
0x00000005 b8210000c1 mov eax, 0xc1000021
0x0000000a ebfd jmp 9
0x0000000a ebfd jmp 0x9
0x0000000c bb2c000000 mov ebx, 0x2c
0x00000011 ebf0 jmp 3
0x00000011 ebf0 jmp 0x3
0x00000013 0000 add byte [rax], al
EOF
RUN
@ -569,18 +569,18 @@ e asm.bb.middle=false
pif
EOF
EXPECT=<<EOF
nop dword [rax + rax]
nop dword [rax+rax*1], eax
add byte [rax], al
mov eax, 0xc1000021
shr ebx, 0xfd
mov ebx, 0x2c
jmp 3
jmp 0x3
nop dword [rax + rax]
nop dword [rax+rax*1], eax
mov eax, 0xc1000021
jmp 9
jmp 0x9
mov ebx, 0x2c
jmp 3
jmp 0x3
EOF
RUN
@ -612,11 +612,11 @@ echo
pd 3 @ 0x560e95 @e:scr.color=1
EOF
EXPECT=<<EOF
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
| ;-- sym.dummy:
| 0x00560e7d 5e pop esi
0x00560e7a ~ 0085965e5052 add byte [ebp + 0x52505e96], al
0x00560e7a ~ 0085965e5052 add byte [ebp+0x52505e96], al
;-- sym.dummy:
0x00560e7c 96 xchg esi, eax
| 0x00560e7d 5e pop esi
@ -634,12 +634,12 @@ EXPECT=<<EOF
| ;-- (0x00560e97) sym.dummy:
0x00560e95 ~ ba0f31e914 mov edx, 0x14e9310f
| 0x00560e9a 0000 add byte [eax], al
| 0x00560e9c 00a836dc5264 add byte [eax + 0x6452dc36], ch
| 0x00560e9c 00a836dc5264 add byte [eax+0x6452dc36], ch
;-- sym.real:
| ;-- (0x00560e97) sym.dummy:
0x00560e95 ~ ba0f31e914 mov edx, 0x14e9310f
| 0x00560e9a 0000 add byte [eax], al
| 0x00560e9c 00a836dc5264 add byte [eax + 0x6452dc36], ch
| 0x00560e9c 00a836dc5264 add byte [eax+0x6452dc36], ch
EOF
RUN

8
test/db/cmd/midflags
View file

@ -367,7 +367,7 @@ EXPECT=<<EOF
0x00000002 49 dec ecx
0x00000003 ~ 89d1 mov ecx, edx
;-- mid.flag:
0x00000004 d15e48 rcr dword [esi + 0x48], 1
0x00000004 d15e48 rcr dword [esi+0x48], 0x01
EOF
RUN
@ -389,8 +389,8 @@ EXPECT=<<EOF
;-- mid.flag:
0x00000002 eb05 jmp mid.flag2
0x00000004 31c0 xor eax, eax
0x00000006 74f9 je 1
0x00000008 ~ e890909090 call 0x9090909d
0x00000006 74f9 jz 0x1
0x00000008 ~ e890909090 call 0xffffffff9090909d
;-- mid.flag2:
0x00000009 90 nop
EOF
@ -413,7 +413,7 @@ EXPECT=<<EOF
| ; CODE XREF from fcn.00000003 @ 0x5
| ;-- (0x00000003) fcn.00000003:
| 0x00000000 ~ b821c10010 mov eax, 0x1000c121
| 0x00000005 ebf9 jmp 0
| 0x00000005 ebf9 jmp 0x0
0x00000007 ~ b8210011c1 mov eax, 0xc1110021 ; '!'
;-- sym.dummy:
0x00000009 0011 add byte [rcx], dl

8
test/db/cmd/noreturn
View file

@ -97,13 +97,13 @@ EXPECT=<<EOF
| 0x00400566 55 push rbp
| 0x00400567 4889e5 mov rbp, rsp
| 0x0040056a 4883ec10 sub rsp, 0x10
| 0x0040056e 837dfc00 cmp dword [var_ch], 0
| ,=< 0x00400572 740a je 0x40057e
| | 0x00400574 bf00000000 mov edi, 0
| 0x0040056e 837dfc00 cmp dword [var_ch], 0x00
| ,=< 0x00400572 740a jz 0x40057e
| | 0x00400574 bf00000000 mov edi, 0x00
| | 0x00400579 e8d2feffff call sym.imp.exit ; void exit(int status)
| `-> 0x0040057e bf20064000 mov edi, str.hello ; 0x400620 ; "hello"
| 0x00400583 e8a8feffff call sym.imp.puts ; int puts(const char *s)
| 0x00400588 b800000000 mov eax, 0
| 0x00400588 b800000000 mov eax, 0x00
| 0x0040058d c9 leave
\ 0x0040058e c3 ret
EOF

14
test/db/cmd/print_bug
View file

@ -10,8 +10,8 @@ pi 1
pdq 1
EOF
EXPECT=<<EOF
movabs rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c movabs rcx, 'ld.lldtn'
mov rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c mov rcx, 'ld.lldtn'
EOF
RUN
@ -33,10 +33,10 @@ ia > /dev/null
pdq 1
EOF
EXPECT=<<EOF
movabs rcx, 110.116.100.108
movabs rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c movabs rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c movabs rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c movabs rcx, 'ld.lldtn'
mov rcx, 110.116.100.108
mov rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c mov rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c mov rcx, 'ld.lldtn'
0x00000000 48b96e74646c6c2e646c mov rcx, 'ld.lldtn'
EOF
RUN

2
test/db/cmd/simple-elf
View file

@ -25,7 +25,7 @@ EXPECT=<<EOF
;-- section..text:
0x08048060 call 0x8048065 ; [00] -r-x section size 18 named .text
0x08048065 pop ebx
0x08048066 mov eax, 1
0x08048066 mov eax, 0x01
0x0804806b mov ebx, 0x2a ; '*' ; 42
0x08048070 int 0x80
EOF

32
test/db/cmd/structures
View file

@ -38,15 +38,15 @@ afvt s1 "struct S1"
pi 4 @ 0x004004be
EOF
EXPECT=<<EOF
mov dword [s1], 1
mov dword [var_114h], 2
mov dword [var_110h], 3
lea rax, [s1]
mov dword [s1], 0x01
mov dword [var_114h], 0x02
mov dword [var_110h], 0x03
lea rax, qword [s1]
---
mov dword [s1.a], 1
mov dword [s1.b], 2
mov dword [s1.c], 3
lea rax, [s1.a]
mov dword [s1.a], 0x01
mov dword [s1.b], 0x02
mov dword [s1.c], 0x03
lea rax, qword [s1.a]
EOF
RUN
@ -65,13 +65,13 @@ td "struct S1 { int x; int y; int c; char d[256]; short e; }"
pi 4 @ 0x004004be
EOF
EXPECT=<<EOF
mov dword [s1.a], 1
mov dword [s1.b], 2
mov dword [s1.c], 3
lea rax, [s1.a]
mov dword [s1.x], 1
mov dword [s1.y], 2
mov dword [s1.c], 3
lea rax, [s1.x]
mov dword [s1.a], 0x01
mov dword [s1.b], 0x02
mov dword [s1.c], 0x03
lea rax, qword [s1.a]
mov dword [s1.x], 0x01
mov dword [s1.y], 0x02
mov dword [s1.c], 0x03
lea rax, qword [s1.x]
EOF
RUN

56
test/db/cmd/types
View file

@ -1161,15 +1161,15 @@ echo ---
pd 4
EOF
EXPECT=<<EOF
mov eax, dword [eax + foo.b]
mov dword [ecx + foo.b], edx
lea edx, [eax + foo.c]
cmp dword [eax + foo.c], 0
mov eax, dword [eax+foo.b]
mov dword [ecx+foo.b], edx
lea edx, dword [eax+foo.c]
cmp dword [eax+foo.c], 0x00
---
0x00000000 8b4004 mov eax, dword [eax + foo.b]
0x00000003 895104 mov dword [ecx + foo.b], edx
0x00000006 8d5008 lea edx, [eax + foo.c]
0x00000009 83780800 cmp dword [eax + foo.c], 0
0x00000000 8b4004 mov eax, dword [eax+foo.b]
0x00000003 895104 mov dword [ecx+foo.b], edx
0x00000006 8d5008 lea edx, dword [eax+foo.c]
0x00000009 83780800 cmp dword [eax+foo.c], 0x00
EOF
RUN
@ -1188,10 +1188,10 @@ aat
pdf~bar.
EOF
EXPECT=<<EOF
| 0x00000007 488b5004 mov rdx, qword [rax + bar.b]
| 0x0000000b 488b4808 mov rcx, qword [rax + bar.c]
| 0x0000000f 483b5004 cmp rdx, qword [rax + bar.b]
| 0x0000001d 48895808 mov qword [rax + bar.c], rbx
| 0x00000007 488b5004 mov rdx, qword [rax+bar.b]
| 0x0000000b 488b4808 mov rcx, qword [rax+bar.c]
| 0x0000000f 483b5004 cmp rdx, qword [rax+bar.b]
| 0x0000001d 48895808 mov qword [rax+bar.c], rbx
EOF
RUN
@ -1212,10 +1212,10 @@ pdf~bar.
EOF
EXPECT=<<EOF
| 0x00000007 488b5004 mov rdx, qword [rax + bar.b]
| 0x0000000b 488b4808 mov rcx, qword [rax + bar.c]
| 0x0000000f 483b5004 cmp rdx, qword [rax + bar.b]
| 0x0000001d 48895808 mov qword [rax + bar.c], rbx
| 0x00000007 488b5004 mov rdx, qword [rax+bar.b]
| 0x0000000b 488b4808 mov rcx, qword [rax+bar.c]
| 0x0000000f 483b5004 cmp rdx, qword [rax+bar.b]
| 0x0000001d 48895808 mov qword [rax+bar.c], rbx
EOF
RUN
@ -1239,11 +1239,11 @@ EOF
EXPECT=<<EOF
/ fcn.00000000();
| 0x00000000 48c7c0000100. mov rax, 0x100
| 0x00000007 488b5008 mov rdx, qword [rax + foo.c]
| 0x0000000b 488b4804 mov rcx, qword [rax + foo.b]
| 0x00000007 488b5008 mov rdx, qword [rax+foo.c]
| 0x0000000b 488b4804 mov rcx, qword [rax+foo.b]
| 0x0000000f 48c7c0000200. mov rax, 0x200
| 0x00000016 488b5008 mov rdx, qword [rax + bar.z]
| 0x0000001a 488b4804 mov rcx, qword [rax + bar.y]
| 0x00000016 488b5008 mov rdx, qword [rax+bar.z]
| 0x0000001a 488b4804 mov rcx, qword [rax+bar.y]
| 0x0000001e 90 nop
| 0x0000001f 90 nop
\ 0x00000020 c3 ret
@ -1263,14 +1263,14 @@ pdf~Books
EOF
EXPECT=<<EOF
| ; var struct Books Books @ stack - 0xe8
| 0x00000684 488d8520ffff. lea rax, [Books.title]
| 0x00000684 488d8520ffff. lea rax, qword [Books.title]
| 0x00000695 488910 mov qword [rax], rdx ; Books.title[0]
| 0x00000698 488d8520ffff. lea rax, [Books.title]
| 0x00000698 488d8520ffff. lea rax, qword [Books.title]
| 0x000006ad 488908 mov qword [rax], rcx ; Books.author[0]
| 0x000006b0 488d8520ffff. lea rax, [Books.title]
| 0x000006b0 488d8520ffff. lea rax, qword [Books.title]
| 0x000006c5 488930 mov qword [rax], rsi ; Books.subject[0]
| 0x000006c8 66c740086700 mov word [rax + Books.subject[8]], 0x67 ; 'g'
| 0x000006d5 b800000000 mov eax, 0 ; Books.subject[0]
| 0x000006c8 66c740086700 mov word [rax+Books.subject[8]], 0x67 ; 'g'
| 0x000006d5 b800000000 mov eax, 0x00 ; Books.subject[0]
EOF
RUN
@ -1288,9 +1288,9 @@ s 0x000005a8
pd 3
EOF
EXPECT=<<EOF
| 0x000005a8 c70206000000 mov dword [edx], 6 ; Test.a
| 0x000005a8 c70206000000 mov dword [edx], 0x06 ; Test.a
| 0x000005ae 8b55f4 mov edx, dword [Test.a] ; Test.a
| 0x000005b1 c74204070000. mov dword [edx + Test.b], 7
| 0x000005b1 c74204070000. mov dword [edx+Test.b], 0x07
EOF
RUN
@ -1311,7 +1311,7 @@ EOF
EXPECT=<<EOF
pf "0[50]c[50]c[100]c title author subject"
var union Books books @ stack - 0x78
| 0x000006d2 488d4590 lea rax, [books.title]
| 0x000006d2 488d4590 lea rax, qword [books.title]
EOF
RUN

32
test/db/cmd/write
View file

@ -94,7 +94,7 @@ wa "je 0x33" @ 0x10
pi 1 @ 0x10
EOF
EXPECT=<<EOF
je 0x33
jz 0x33
EOF
RUN
@ -503,7 +503,7 @@ EOF
EXPECT=<<EOF
/ fcn.00000000();
| 0x00000000 0000 add byte [rax], al
| 0x00000002 7502 jne 6
| 0x00000002 7502 jnz 0x6
| ----------- true: 0x00000006 false: 0x00000004
| 0x00000004 0000 add byte [rax], al
| ----------- true: 0x00000006
@ -512,9 +512,9 @@ EXPECT=<<EOF
/ fcn.00000000();
| 0x00000000 0000 add byte [rax], al
| 0x00000002 7502 jne 6
| 0x00000002 7502 jnz 0x6
| ----------- true: 0x00000006 false: 0x00000004
| 0x00000004 7502 jne 8
| 0x00000004 7502 jnz 0x8
| ----------- true: 0x00000008 false: 0x00000006
| 0x00000006 0000 add byte [rax], al
| ----------- true: 0x00000008
@ -523,7 +523,7 @@ EXPECT=<<EOF
/ fcn.00000000();
| ; var int64_t var_4h @ stack - 0x4
| 0x00000000 488b45fc mov rax, qword [var_4h]
| 0x00000004 7502 jne 8
| 0x00000004 7502 jnz 0x8
| ----------- true: 0x00000008 false: 0x00000006
| 0x00000006 0000 add byte [rax], al
| ----------- true: 0x00000008
@ -532,7 +532,7 @@ EXPECT=<<EOF
/ fcn.00000000();
| ; var int64_t test @ stack - 0x4
| 0x00000000 488b45fc mov rax, qword [test]
| 0x00000004 75fa jne fcn.00000000
| 0x00000004 75fa jnz fcn.00000000
| ----------- true: 0x00000000 false: 0x00000006
| 0x00000006 0000 add byte [rax], al
\ 0x00000008 c3 ret
@ -555,8 +555,8 @@ pdr
EOF
EXPECT=<<EOF
/ fcn.00000000();
| 0x00000000 e802000000 call 7
| 0x00000005 7502 jne 9
| 0x00000000 e802000000 call 0x7
| 0x00000005 7502 jnz 0x9
| ----------- true: 0x00000009 false: 0x00000007
| ; CALL XREF from fcn.00000000 @
| 0x00000007 0000 add byte [rax], al
@ -565,7 +565,7 @@ EXPECT=<<EOF
/ fcn.00000000(int64_t arg_2h);
| ; arg int64_t arg_2h @ stack + 0x2
| 0x00000000 7507 jne 9
| 0x00000000 7507 jnz 0x9
| ----------- true: 0x00000009 false: 0x00000002
| 0x00000002 0000 add byte [rax], al
| 0x00000004 007502 add byte [arg_2h], dh
@ -576,8 +576,8 @@ EXPECT=<<EOF
/ fcn.00000000(int64_t arg_2h);
| ; arg int64_t arg_2h @ stack + 0x2
| 0x00000000 e802000000 call 7
| 0x00000005 7502 jne 9
| 0x00000000 e802000000 call 0x7
| 0x00000005 7502 jnz 0x9
| ----------- true: 0x00000009 false: 0x00000007
| ; CALL XREF from fcn.00000000 @
| 0x00000007 0000 add byte [rax], al
@ -632,17 +632,17 @@ pdr
EOF
EXPECT=<<EOF
/ fcn.00000000();
| 0x00000000 eb04 jmp 6
| 0x00000000 eb04 jmp 0x6
| ----------- true: 0x00000006
| 0x00000002 eb02 jmp 6
| 0x00000002 eb02 jmp 0x6
| ----------- true: 0x00000006
| ; CODE XREFS from fcn.00000000 @ , 0x2
| 0x00000006 75fa jne 2
| 0x00000006 75fa jnz 0x2
| ----------- true: 0x00000002 false: 0x00000008
\ 0x00000008 c3 ret
/ fcn.00000000();
| 0x00000000 eb02 jmp 4
| 0x00000000 eb02 jmp 0x4
| ----------- true: 0x00000004
| ; CODE XREF from fcn.00000000 @
| 0x00000004 eb04 jmp 0xa
@ -654,7 +654,7 @@ EXPECT=<<EOF
| 0x00000008 eb02 jmp 0xc
| ----------- true: 0x0000000c
| ; CODE XREF from fcn.00000000 @ 0x4
| 0x0000000a 75fa jne 6
| 0x0000000a 75fa jnz 0x6
| ----------- true: 0x00000006 false: 0x0000000c
| ; CODE XREF from fcn.00000000 @ 0x8
\ 0x0000000c c3 ret

10
test/db/esil/x86_32
View file

@ -1203,9 +1203,9 @@ pd 1 @ 0x11c0
pd 1 @ 0x1523
EOF
EXPECT=<<EOF
0x00001557 lea eax, [esi - 0x220c] ; " fwhibbit{" str.fwhibbit
0x000011c0 lea eax, [ebx - 0x2448] ; " -os--/sosdmmNNMMNy .+// " str.os___sosdmmNNMMNy_________.
0x00001523 lea eax, [esi - 0x2218] ; "\n Red Pill" str.Red_Pill
0x00001557 lea eax, dword [esi-0x220c] ; " fwhibbit{" str.fwhibbit
0x000011c0 lea eax, dword [ebx-0x2448] ; " -os--/sosdmmNNMMNy .+// " str.os___sosdmmNNMMNy_________.
0x00001523 lea eax, dword [esi-0x2218] ; "\n Red Pill" str.Red_Pill
EOF
RUN
@ -1220,8 +1220,8 @@ pd 1 @ 0x1557
pd 1 @ 0x1523
EOF
EXPECT=<<EOF
| 0x00001557 lea eax, str.fwhibbit ; 0x1df4 ; " fwhibbit{"
| 0x00001523 lea eax, str.Red_Pill ; 0x1de8 ; "\n Red Pill"
| 0x00001557 lea eax, dword str.fwhibbit ; 0x1df4 ; " fwhibbit{"
| 0x00001523 lea eax, dword str.Red_Pill ; 0x1de8 ; "\n Red Pill"
EOF
RUN

22
test/db/esil/x86_64
View file

@ -146,8 +146,8 @@ ar rax
ar rbx
EOF
EXPECT=<<EOF
mov rax, 4
mov rbx, 5
mov rax, 0x04
mov rbx, 0x05
rax = 0x0000000000000004
rbx = 0x0000000000000005
EOF
@ -166,8 +166,8 @@ ar rax
ar rbx
EOF
EXPECT=<<EOF
mov rax, 4
mov rbx, 5
mov rax, 0x04
mov rbx, 0x05
rax = 0x0000000000000004
rbx = 0x0000000000000005
EOF
@ -186,8 +186,8 @@ ar rax
ar rbx
EOF
EXPECT=<<EOF
mov rax, 4
mov rbx, 5
mov rax, 0x04
mov rbx, 0x05
rax = 0x0000000000000004
rbx = 0x0000000000000005
EOF
@ -204,7 +204,7 @@ ao~opcode,esil
EOF
EXPECT=<<EOF
opcode: lea rsi, [rdi + 0x68]
opcode: lea rsi, qword [rdi+0x68]
esilcost: 0
esil: 0x68,rdi,+,rsi,=
EOF
@ -221,7 +221,7 @@ ao~opcode,esil
EOF
EXPECT=<<EOF
opcode: lea rdi, [rbp - 0x440]
opcode: lea rdi, qword [rbp-0x440]
esilcost: 0
esil: 0x440,rbp,-,rdi,=
EOF
@ -238,7 +238,7 @@ ao~opcode,esil
EOF
EXPECT=<<EOF
opcode: mov dword [rip + 0x40dd], 1
opcode: mov dword [rip+0x40dd], 0x01
esilcost: 12
esil: 1,0x40dd,rip,+,=[4]
EOF
@ -327,7 +327,7 @@ wx 4a8d04ef
ao~esil,opcode
EOF
EXPECT=<<EOF
opcode: lea rax, [rdi + r13*8]
opcode: lea rax, qword [rdi+r13*8]
esilcost: 0
esil: r13,8,*,rdi,+,rax,=
EOF
@ -342,7 +342,7 @@ wx 488d1c10
ao~opcode,esil
EOF
EXPECT=<<EOF
opcode: lea rbx, [rax + rdx]
opcode: lea rbx, qword [rax+rdx*1]
esilcost: 0
esil: rdx,rax,+,rbx,=
EOF

4
test/db/formats/coff
View file

@ -158,7 +158,7 @@ e asm.bytes=true
pd 2 @ sym.main+6
EOF
EXPECT=<<EOF
0x00000006 4c8d05230000. lea r8, [0x00000030] ; sym..data ; "Win64 assembly"; RELOC 32 .data @ 0x00000030
0x0000000d 488d152b0000. lea rdx, [0x0000003f] ; str.Coffee_time ; "Coffee time!"; RELOC 32 .data @ 0x00000030 + 0xf
0x00000006 4c8d05230000. lea r8, qword [0x00000030] ; sym..data ; "Win64 assembly"; RELOC 32 .data @ 0x00000030
0x0000000d 488d152b0000. lea rdx, qword [0x0000003f] ; str.Coffee_time ; "Coffee time!"; RELOC 32 .data @ 0x00000030 + 0xf
EOF
RUN

4
test/db/formats/demangling_bin
View file

@ -259,14 +259,14 @@ EXPECT=<<EOF
; CALL XREF from sym.std::__cxx11::basic_string_char__std::char_traits_char___std::allocator_char___::basic_string_char___void__char___char___std::allocator_char__const @ +0x66
; CALL XREF from sym.void_std::__cxx11::basic_string_char__std::char_traits_char___std::allocator_char___::_M_construct_char___char___char___std::forward_iterator_tag @ +0x116
/ sym.imp._Unwind_Resume();
\ 0x00000f10 jmp dword [ebx + 0x70]
\ 0x00000f10 jmp dword [ebx+0x70]
; CALL XREF from main @ +0x222
; CALL XREF from fcn.00001717 @ +0xbb
; CALL XREF from sym.std::__cxx11::basic_string_char__std::char_traits_char___std::allocator_char___::basic_string_char___void__char___char___std::allocator_char__const @ +0x66
; CALL XREF from sym.void_std::__cxx11::basic_string_char__std::char_traits_char___std::allocator_char___::_M_construct_char___char___char___std::forward_iterator_tag @ +0x116
/ sym.imp._Unwind_Resume();
\ 0x00000f10 jmp dword [ebx + 0x70]
\ 0x00000f10 jmp dword [ebx+0x70]
EOF
RUN

8
test/db/formats/dmp/dmp
View file

@ -184,10 +184,10 @@ r13 = 0xffff850429891ee8
r14 = 0xffff850429891560
r15 = 0xfffff8047ba00000
rip = 0xfffff8047bdf5a80
mov qword [rsp + 8], rcx
mov qword [rsp + 0x10], rdx
mov qword [rsp + 0x18], r8
mov qword [rsp + 0x20], r9
mov qword [rsp+0x08], rcx
mov qword [rsp+0x10], rdx
mov qword [rsp+0x18], r8
mov qword [rsp+0x20], r9
0 0xfffff8047bdf5a80 sp: 0xffff850429890ee8 0 [??] pdb.ntkrnlmp.KeBugCheckEx
1 0xfffff8047be0f4e1 sp: 0xffff850429890ef0 56 [??] pdb.ntkrnlmp.string_::3655334267::_Kernel_MUI_Lang_::1575215452+5649
2 0xfffff8047bdcc052 sp: 0xffff850429890f30 104 [??] pdb.ntkrnlmp.__C_specific_handler+162

4
test/db/formats/elf/core
View file

@ -52,11 +52,11 @@ pd 1 @ 0x7ffe70f68000
EOF
EXPECT=<<EOF
;-- segment.LOAD14:
,=< 0x7ffe70f68000 7f45 jg 0x7ffe70f68047 ; [15] -r-x segment size 8192 named LOAD14
,=< 0x7ffe70f68000 7f45 jnle 0x7ffe70f68047 ; [15] -r-x segment size 8192 named LOAD14
; [15] -r-x segment size 8192 named LOAD14
;-- segment.LOAD14:
,=< 0x7ffe70f68000 7f45 jg 0x7ffe70f68047
,=< 0x7ffe70f68000 7f45 jnle 0x7ffe70f68047
EOF
RUN

2
test/db/formats/elf/overlapped-segment
View file

@ -26,7 +26,7 @@ EXPECT=<<EOF
;-- segment.GNU_STACK:
;-- segment.ehdr:
0x00000000 endbr64
0x00000004 sub rsp, 8
0x00000004 sub rsp, 0x08
0x00000008 mov rax, qword [0x00002fe8] ; [0x2fe8:8]=-1
EOF
RUN

28
test/db/formats/elf/reloc
View file

@ -27,13 +27,13 @@ EOF
EXPECT=<<EOF
0x00004e98 31c0 xor eax, eax
0x00004e9a e8a1e60000 call 0x13540
0x00004e9f 488d351e4a0100 lea rsi, [rip + 0x14a1e]
0x00004ea6 bf06000000 mov edi, 6
0x00004e9f 488d351e4a0100 lea rsi, qword [rip+0x14a1e]
0x00004ea6 bf06000000 mov edi, 0x06
0x00004eab e8b0fdffff call sym.imp.setlocale
0x00004eb0 488d35584b0100 lea rsi, [rip + 0x14b58]
0x00004eb7 488d3d374b0100 lea rdi, [rip + 0x14b37]
0x00004eb0 488d35584b0100 lea rsi, qword [rip+0x14b58]
0x00004eb7 488d3d374b0100 lea rdi, qword [rip+0x14b37]
0x00004ebe e81dfaffff call sym.imp.bindtextdomain
0x00004ec3 488d3d2b4b0100 lea rdi, [rip + 0x14b2b]
0x00004ec3 488d3d2b4b0100 lea rdi, qword [rip+0x14b2b]
0x00004eca e8d1f9ffff call sym.imp.textdomain
EOF
RUN
@ -316,12 +316,12 @@ EXPECT=<<EOF
| ; arg int64_t arg1 @ rdi
| 0x08000040 movzx eax, byte [rdi] ; RELOC TARGET 32 .text @ 0x08000040 - 0x8004d08 ; arg1 ; [01] -r-x section size 6641 named .text
| 0x08000043 and eax, 0x7f ; 127
| 0x08000046 sub eax, 4
| 0x08000046 sub eax, 0x04
| 0x08000049 cmp al, 0x73 ; 115
| ,=< 0x0800004b ja case.0x800005e.5
| | 0x0800004d lea rdx, reloc.target..rodata ; 0x8001a34 ; "4\xe6\xff\xff,\xe6\xff\xff4\xe6\xff\xff,\xe6\xff\xff4\xe6\xff\xffD\xe6\xff\xff4\xe6\xff\xffD\xe6\xff\xff4\xe6\xff\xff,\xe6\xff\x"; RELOC 32 .rodata @ 0x08001a34 - 0x8000054
| ,=< 0x0800004b jnbe case.0x800005e.5
| | 0x0800004d lea rdx, qword reloc.target..rodata ; 0x8001a34 ; "4\xe6\xff\xff,\xe6\xff\xff4\xe6\xff\xff,\xe6\xff\xff4\xe6\xff\xffD\xe6\xff\xff4\xe6\xff\xffD\xe6\xff\xff4\xe6\xff\xff,\xe6\xff\x"; RELOC 32 .rodata @ 0x08001a34 - 0x8000054
| | 0x08000054 movzx eax, al
| | 0x08000057 movsxd rax, dword [rdx + rax*4]
| | 0x08000057 movsxd rax, dword [rdx+rax*4]
| | 0x0800005b add rax, rdx
| | ;-- switch
| | 0x0800005e jmp rax ; switch table (116 cases) at 0x8001a34
@ -351,7 +351,7 @@ EXPECT=<<EOF
| ;-- case 26: ; from 0x800005e
| ;-- case 33: ; from 0x800005e
| 0x08000068 mov rsi, rdi ; arg1
| 0x0800006b mov edi, 1
| 0x0800006b mov edi, 0x01
| ,=< 0x08000070 jmp reloc.target.getPageLengthNV ; RELOC 32 getPageLengthNV
..
| | ; CODE XREF from sym.owGetPageLength.constprop.0 @ 0x800005e
@ -359,25 +359,25 @@ EXPECT=<<EOF
| | ;-- case 15: ; from 0x800005e
| | ;-- case 19: ; from 0x800005e
| | 0x08000078 mov rsi, rdi ; arg1
| | 0x0800007b mov edi, 1
| | 0x0800007b mov edi, 0x01
| ,==< 0x08000080 jmp reloc.target.getPageLengthEPROM ; RELOC 32 getPageLengthEPROM
..
| || ; CODE XREF from sym.owGetPageLength.constprop.0 @ 0x800005e
| || ;-- case 51: ; from 0x800005e
| || 0x08000088 mov rsi, rdi ; arg1
| || 0x0800008b mov edi, 1
| || 0x0800008b mov edi, 0x01
| ,===< 0x08000090 jmp reloc.target.getPageLengthSHAEE ; RELOC 32 getPageLengthSHAEE
..
| ||| ; CODE XREF from sym.owGetPageLength.constprop.0 @ 0x800005e
| ||| ;-- case 55: ; from 0x800005e
| ||| 0x08000098 mov rsi, rdi ; arg1
| ||| 0x0800009b mov edi, 1
| ||| 0x0800009b mov edi, 0x01
| ,====< 0x080000a0 jmp reloc.target.getPageLengthEE77 ; RELOC 32 getPageLengthEE77
..
| |||| ; CODE XREF from sym.owGetPageLength.constprop.0 @ 0x800005e
| |||| ;-- case 20: ; from 0x800005e
| |||| 0x080000a8 mov rsi, rdi ; arg1
| |||| 0x080000ab mov edi, 1
| |||| 0x080000ab mov edi, 0x01
\ ,=====< 0x080000b0 jmp reloc.target.getPageLengthEE ; RELOC 32 getPageLengthEE
EOF
RUN

4
test/db/formats/elf/serial
View file

@ -12,7 +12,7 @@ af @ 0x0040073d
pd 1
EOF
EXPECT=<<EOF
0x00400b35 lea rax, [0x0040073d]
0x00400b35 lea rax, [fcn.0040073d]
0x00400b35 lea rax, qword [0x0040073d]
0x00400b35 lea rax, qword [fcn.0040073d]
EOF
RUN

6
test/db/formats/elf/simple
View file

@ -16,9 +16,9 @@ EOF
EXPECT=<<EOF
0x08000060 section..text:
0x08000060 b990000008 mov ecx, 0x8000090
0x08000065 ba0d000000 mov edx, 0xd
0x0800006a bb01000000 mov ebx, 1
0x0800006f b804000000 mov eax, 4
0x08000065 ba0d000000 mov edx, 0x0d
0x0800006a bb01000000 mov ebx, 0x01
0x0800006f b804000000 mov eax, 0x04
EOF
RUN

16
test/db/formats/firmware
View file

@ -18,7 +18,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_64k.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -64,7 +64,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_128k.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -88,7 +88,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_256k.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -112,7 +112,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_512k.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -136,7 +136,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_1M.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -160,7 +160,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_2M.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -184,7 +184,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_4M.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN
@ -208,7 +208,7 @@ NAME=corrupted section data
FILE=bins/firmware/bios_8M.bin
CMDS=pi 1
EXPECT=<<EOF
ljmp 0xf000:0xffaa
jmp far 0xf000:0xffaa
EOF
RUN

2
test/db/formats/mach0/objc
View file

@ -120,7 +120,7 @@ axl~?
axl~selref
EOF
EXPECT=<<EOF
94
92
section.0.__TEXT.__text+20 0x100000db4 -> DATA -> 0x100001150 section.14.__DATA.__objc_selrefs
main+15 0x100000e5f -> DATA -> 0x100001158 section.14.__DATA.__objc_selrefs+8
main+45 0x100000e7d -> DATA -> 0x100001160 section.14.__DATA.__objc_selrefs+16

14
test/db/formats/pdb
View file

@ -173,11 +173,11 @@ global void * __guard_dispatch_icall_fptr @ 0x140015020
global void * __guard_xfg_dispatch_icall_fptr @ 0x140015030
global void * __guard_xfg_table_dispatch_icall_fptr @ 0x140015040
---
(nofunc) 0x140007344 [DATA] lea rcx, pdb.exceptions_test.__guard_check_icall_fptr
0x140007344 lea rcx, pdb.exceptions_test.__guard_check_icall_fptr ; 0x140015000
(nofunc) 0x140007344 [DATA] lea rcx, qword pdb.exceptions_test.__guard_check_icall_fptr
0x140007344 lea rcx, qword pdb.exceptions_test.__guard_check_icall_fptr ; 0x140015000
0x14000734b call fcn.1400011db
0x140007350 lea rcx, [0x14000101e]
fcn.140001366 0x140006a64 [DATA] mov dword [pdb.exceptions_test.__scrt_debugger_hook_flag], 0
0x140007350 lea rcx, qword [0x14000101e]
fcn.140001366 0x140006a64 [DATA] mov dword [pdb.exceptions_test.__scrt_debugger_hook_flag], 0x00
; CALL XREFS from fcn.140001398 @ 0x140006aab, 0x140006c04
/ fcn.140001366(int64_t arg1);
| ; arg int64_t arg1 @ rcx
@ -187,17 +187,17 @@ fcn.140001366 0x140006a64 [DATA] mov dword [pdb.exceptions_test.__scrt_debugger_
| ; CODE XREF from fcn.140001366 @ 0x140001366
| ;-- __crt_debugger_hook:
| 0x140006a60 mov dword [var_8h], ecx ; arg1
| 0x140006a64 mov dword [pdb.exceptions_test.__scrt_debugger_hook_flag], 0 ; [0x140011ba4:4]=0
| 0x140006a64 mov dword [pdb.exceptions_test.__scrt_debugger_hook_flag], 0x00 ; [0x140011ba4:4]=0
\ 0x140006a6e ret
fcn.140001316 0x140006a40 [DATA] lea rax, pdb.exceptions_test.__dyn_tls_init_callback
fcn.140001316 0x140006a40 [DATA] lea rax, qword pdb.exceptions_test.__dyn_tls_init_callback
; CALL XREF from fcn.1400049a0 @ 0x140004a44
/ fcn.140001316();
| 0x140001316 jmp pdb.exceptions_test.__scrt_get_dyn_tls_init_callback
| ----------- true: 0x140006a40
| ; CODE XREF from fcn.140001316 @ 0x140001316
| ;-- __scrt_get_dyn_tls_init_callback:
| 0x140006a40 lea rax, pdb.exceptions_test.__dyn_tls_init_callback ; 0x140011be0
| 0x140006a40 lea rax, qword pdb.exceptions_test.__dyn_tls_init_callback ; 0x140011be0
\ 0x140006a47 ret
EOF

2
test/db/formats/pe/aslr
View file

@ -28,6 +28,6 @@ NAME=PE: corkami aslr.dll - pi 1
FILE=bins/pe/aslr.dll
CMDS=pi 1
EXPECT=<<EOF
mov eax, 1
mov eax, 0x01
EOF
RUN

2
test/db/formats/pe/ctxt
View file

@ -27,6 +27,6 @@ e asm.sub.names=false
pi 1
EOF
EXPECT=<<EOF
cmp dword [esp + 8], 1
cmp dword [esp+0x08], 0x01
EOF
RUN

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