Commit graph

16 commits

Author SHA1 Message Date
brightprogrammer
16e722cffc
Replace rz_core_cmd0 calls in tui/panels.c and port cmd_help commands to RzShell as cmd_math (#3421) 2023-03-30 18:36:48 +08:00
Florian Märkl
01a82490d7 Raise timeout for some aez tests
On some platforms, the rizin startup itself takes multiple seconds,
which can make these tests timeout even if they would otherwise work.
2023-01-09 10:26:30 +08:00
wargio
2b3c6b5102 Updated all tests 2022-11-01 10:58:16 +08:00
Riccardo Schirone
9ba89d8116 core/cmd: rewrite rz_cmd_macro API 2022-08-26 07:53:43 +08:00
Khairul Azhar Kasmiran
45bf3677b2
Add double aezi test (#2372) 2022-02-28 22:48:03 +08:00
Khairul Azhar Kasmiran
f3c77de061
aezsu: Fix outdated pc when checking for completion (#2367)
* aezsu: Fix outdated `pc` when checking for completion
* Check reg pc after stepping as well
2022-02-27 22:04:45 +08:00
Anton Kochkov
2f638cad1e Convert f commands to rzshell
* Changed behavior of `f` to only add flag if there is none
* Changed behavior of `f+` to add flag in any case
* Moved listing subcommands from `f` to `fl`
* Moved listing subcommands from `f.` to `f.l`
* Added subcommand `f.l*` to list all local flags in all functions
* Listing flags at the current offset became `fl.`
* Moved `f=` to `fl=`
* Old `fl` (flag length) now became `fL`
* Removed original `fe` commands
* Old `f?` (check if flag exists) now became `fe`
* Removed `fV` commands
* Removed `fn` commands in favor of `fl` and `asm.flags.real=true`
* Removed `fS` commands (`fSo` and `fSn`)
* `fo` became `fortune` and moved from "flags" to "shell" category
* Removed oldshell handlers of the `z` commands
2022-02-03 21:46:42 +08:00
Florian Märkl
f9e01ba07d [RzIL] Rewrite RzAnalysisRzil as RzAnalysisILVM with config
RzAnalysisILVM wraps around the low-level RzILVM and enables emulation
of real code from disassembly, rather than raw IL.
Analysis plugins now don't actively initialize the vm anymore, but
return a fully declarative description RzAnalysisILConfig of how to set
up the vm and optionally its initial state.
This also enables multiple IL vms to exist at the same time as plugins
can not mess with the global vm anymore. See the added integration test
for an example.
2022-01-17 16:50:40 +01:00
Florian Märkl
65efe6699c [RzIL] Make aezs and aezse stop on error 2022-01-17 16:50:40 +01:00
Florian Märkl
6ba0f3a091 [RzIL] Make aezsu stop on invalid ops 2022-01-14 17:24:35 +08:00
Florian Märkl
5be9fa2f0f [RzIL] Update flags on init and step 2022-01-14 17:24:35 +08:00
Florian Märkl
b338949dd4 [RzIL] Fix PC initialization and instruction fetch
Intruction was fetched from possibly outdated RzIL PC.
2022-01-03 17:18:33 +01:00
Florian Märkl
9938a85c4b
[RzIL] Add RzReg/Variable Binding (#2155)
Plugins do not create register-based variables themselves anymore, but
they are derived from the register profile. However not all registers
may be bound and not all variables may be actual registers. The concrete
relations between an RzILVM and registers is described by an
RzILRegBinding object. It is simply a list of register names and
variables are created of the same names. When stepping with aezs, the
registers are synchronized automatically. From now on, aezv is primarily
useful for debugging, but interacting with emulation from the user side
should be done with ar.
2022-01-02 17:56:19 +00:00
Giovanni
5963da2bba
[RzIL] Add loadw/storew and bind memories against RzBuffer (#2105)
* [RzIL] Load/Store via RzIO and RzBuffer
* [RzIL] LoadW/StorWe via RzIO and RzBuffer
Co-authored-by: Florian Märkl <info@florianmaerkl.de>
2021-12-24 16:53:20 +01:00
wargio
5dafbf7e67 [core] aezv - modify variables in RzIL VM 2021-12-21 19:50:17 +01:00
wargio
869a36d55b [core] Add aezsu - RzIL step until addr 2021-12-21 19:50:17 +01:00