* Support ARM ELF THM_PC22 / THM_JUMP24 relocs
This revision adds proper support for the following ARM ELF relocations:
- RZ_ARM_THM_PC22
- RZ_ARM_THM_JUMP24
These require a rather special encoding as some bits of the relative
offset are encoded in a non-common fashion.
* Fix memory leaks in debug path
* Fix memory leaks in mach and mdmp format
* Update the fix for mach
* Add support for aarch64 tcache parsing
* Test case fix
* Comment update
---------
Co-authored-by: Giridhar Prasath R <giridh1337@gmail.com>
* Use local variables in methods using `EXEC_WITH_RMODE` instead of
`DUP`ing the values. Do the same for ST register stack popping.
This leads to lesser code in the IL since the same long expression
does not get repeated in the IL everytime (since we don't `DUP`
anymore).
The only place where this field was set to a non-zero value was the now
removed fb command, and it was never used for anything sensible. Thus it
is safe to remove.
The fb command can modify the offset of a flag, but does not update the
skiplist they are stored in, leading to a corrupted flag database. This
can be seen for example when executing
f test @ 0x4; fb 0x10 test; fl; pd 0x8 @ 0
* Increase timeout for OpenBSD
* Reset all members of a packet.
* Replace calloc with Rizin macros
* Add returns after fatal logs
* Init time structs with 0.
* Use monotonic clock to set last access timestamps.
Because instruction packets get pushed out of the buffer based in their last access,
using the real-time clock leads to problems. On Windows the real time clock seems to
not always give ascending values with multiple calls
(real-time clock = best bet of machine of current day time, which can fluctuate).
Using the monotonic clock will always give strictly ascending timestamps.
Due to the use of the real-clock, the instruction packets got
sometimes pushed out of the buffer non-deterministically.
Uplift Hexagon architecture to RzIL
The general structure is, that every (sub-)instruction has a getter for it's RzIL code.
Calling the getter will return the RzIL operation.
If RzIL for an instruction is requested, the plugin makes a decision. Because Hexagon only executes whole instruction packets. If the instruction is not the last instruction in a packet, it will simply return `EMPTY()`. If the RzIL for the last instruction in a packet is requested, it will get the RzIL operations for all instructions in the packet, shuffles them into the correct execution order (according to some rules) and returns the complete operation for the packet.
The RzIL code was entirely generated with the [rzil-compiler](https://github.com/Rot127/rzil-compiler/), using the semantic definition of the [QEMU Hexagon module](https://github.com/qemu/qemu/tree/master/target/hexagon).
Currently successful compile instructions (and tested):
```
[*] 1581/1733 standard instructions compiled.
[*] 431/643 HVX instructions compiled.
[*] In total: 2012/2376 instructions compiled.
```
It was tested with:
- (Semantic tests) `rz-tracetest` against the execution trace of the QEMU Hexagon test binaries.
- (Bug free and semi-semtantic test) Adding tests which simply execute the test binaries to ensure leak and segfault free execution. Also it is executed until a certain instruction is reached (end of `main` or `loc.pass` symbol), partially testing it executes correctly.
For the uplifting several changes and modernization had to be made:
- Enhance consistency of decoding
- Allow to disassemble an instruction without copying the result. This is used if the given buffer of instruction bytes is larger than one instruction width. In this case, as many instructions as the buffer can hold are disassembled and buffered for later.
- Generally enhance buffering of instructions.
- Allow to mark a packet as valid before it is completely decoded (in case we know it must be valid, e.g. if it is a jump target of a valid packet).
- Fix (hopefully) all memory leaks of the Hexagon plugin.
- Changes to register getters, because RzIL needs finer control to translate alias or explicit register names to their real register.
- Getter for register name is now done by table, so for future distinction between DSP version we can just select another table.
- Translation functions from register alias or explicit name to their real register.
- Each operand contains now it's variable ID (e.g. `d` for register `Rd`) as in the ISA (for mapping in the RzIL code).
- Ease debugging by tracking in more precision, if an instruction is added to a stale, active or new packet.
- Add registers `C20` - `C29` (not yet present in LLVM)
- Some renaming to make the code more readable.
* Create `il_fp_ops.inc`, for floating-point instructions' IL ops
* Add IL implementation for `FABS`
* Also add `x86_il_{get,set}_st_reg` helper functions
* Add IL implementation for `FNINIT` and `FLDCW`
* Add IL implementations for `FNSTCW` and `FNSTSW`
* Add IL implementation for `FNCLEX`
* Add ST push and pop functions
* Fix clang formatting
* Add fucntions for updating FPSW TOP pointer
* Add `FLD` instruction lifitng, FPSW flag support, FP operand support
* Remove `x86_bool_to_bv` and use the standard `BOOL_TO_BV`
* Add implementation for `FST{P}`, and rounding mode support
* Add `FLD` variants for constants
* Fix formatting and build
* Add IL lifting for `FXCH`
* Add width checks to avoid redundant rounding
* Implement IL lifting for `FILD`, `FIST{P}`
* Add helper functions to inter-convert floating point values and
integers using the rounding mode in the control word
* FPU stack regs are 80-bit, not 64-bit
* Add RzIL lifting for `FBLD`
* Add RzIL implementation for `FBSTP`
* An invalid-arithmetic-operand (#IA) exception may occurr if the
value being converted to the BCD integer cannot fit in an 18-bit
BCD integer. For the IL's purpose, we just jump to the "int" label
(stands for interrupt) using `GOTO`.
* Remove all the `EMPTY()` ops after `GOTO()` ops
* On second thought, using `EMPTY()` ops after `GOTO()` ops is not
the best idea to indicate end of analysis. Maybe the hooks can
signal that analysis needs to be restarted.
* Also, clean up the comments of a bunch of unimplemented ops
* Moved some code around
* Rename "rmode" local variable to "_rmode"
* Add some TODOs for deffered work
* Fix failing asm tests
* Caused due to the removal of the [empty] opcode
* Implement IL lifting for `FADD` (and some other minor refactoring)
* Implement the IL lifting for `FADD`: This is not entirely correct
as of now, because we don't handle setting C1 based on rounding
up/down, but I think it should be fine for now. Need to tackle
setting the control word bits later
* Start using `RzFloatFormat` to describe the float's width instead
of using an unsigned integer. Provide and expose conversion
functions between the two
* Use a global to denote when RMode needs to be init, implement FIADD
* Other minor refactor which fixes the CI (hopefully)
* Implement `FMUL` and `FIMUL`
* Extract the common code into a C macro
* Implement RzIL for `FSUB` and `FISUB`
* Also add `x86_il_fsub_with_rmode` helper
* Implement RzIL for `FSUBR` and `FISUBR`
* Reuse the implementation of `x86_il_fsub_with_rmode` and just pass
the arguments in the opposite order
* Add RzIL implementation for `FDIV`, `FIDIV`, `FDIVR`, `FIDIVR`
* Add pop versions of floating point arithmetic instuctions
* Add a new macro `X86_ARITHMETIC_POP_IL` macro for the same
* Fix a typo
* Add a note for using `X86_INS_PFADD` for FADDP instruction on
Capstone version newer than 4
* Add RzIL implementations for `FCOM`, `FCOMP` and `FCOMPP`
* Add RzIL lifting for `FUCOM` and `FCOMI` families of instructions
* Implement RzIL lifting for `FCHS` and `FTST`
* Add RzIL implementation for `FRNDINT` and `FSQRT`
* Add RzIL implementation for `FNOP` and `FISTTP`
* Remove global variable `use_rmode` and use pass around a context instead
* Define a new `X86ILContext` struct to pass around information
whether we need to intitialize the rouding mode or not
* Remove the global variable which was previously responsible for
doing so
* Add RzIL for `FICOM` and `FICOMP`, add register bindings and fix bugs
* Make `rz-test` more robust against IL outputs with newlines in them
* Add RzIL tests in db/asm for x86 FPU instructions
* Fix the bug when using `FADDP` with Capstone version > 4
* Fix remaining db tests
* Remove tests for `FSTSW` or `FSTCW` instructions
* We already test `WAIT` (in `db/asm/x86_32`) and `FSTSW` (or
`FSTCW`) (in `db/asm/x86_64`)
* Remove the newline replacement code in `rz-test` as well, since we
wouldn't need that functionality anymore
* Add asm tests for math constant push instructions
* Add `RZ_IPI` annotation for all the functions exposed through the header
* Add `RZ_OWN`, `RZ_BORROW` and `RZ_NONNULL` annotations
* Add Doxygen doc for `ctx` argument
* Add description for the `EXEC_WITH_RMODE` macro
* Move the non-null check for `ctx` inside the valid branch
* When we pop the FPU stack we pass in a `NULL` context since no
resizing would be needed, which causes a failure if the non-null
check for the `ctx` is outside the branch
* Fixes failing tests in `db/asm`
* Minor bug fixes + make the annotations less strict than they need to be
* Minor bug fixes
* Incorrect implementation for `RET` and `CALL`
* Swapped arguments for shift right
* Fix asm tests for `JMP` and `RET` instructions
* Fix indexing error for `FXCH`
* Review changes
* Move all unimplemented instructions to the end
* Remove support for Capstone version less than 4
* Basic framework of rx implemented
* Add match and parse flow
* Add part of description for RxV1 instruction set
* Add datasheet for rxv1
* Implement stringify op for rx
* Add missing TST instruction in datasheet
* Test to div instruction and fix bugs
* Test known rxv1 instruction set
* Fix bugs in rx disasm plugin and add SPDX
* Add rz_analysis for renesas rx
* Fix rz_analysis bug for renesas rx
* Add rz_asm test and fix bug in datasheet
* Add analysis test and fix bugs for renesas rx
