* Chane HexInsn -> HexInsnContainer in asm plugin.
* Make HexInsn -> HexInsnContainer in hexagon_disas.c
* Add function to set concatinate textual disassembly parts.
* Switch expressions, fix segfault.
* Print number of unhandle ops, if they can not be added to RzAnalysisOp.
* Add lookup function to determine sub-instructions for duplex iclass.
* Fix asm tests.
* Add memcpy for instruction containers
* Fix off by one.
* Fix segfault if the packet held only the instruction which is currently resolved. `hic->bin.insn` would be NULL in this case.
* Remove duplicate index name.
* Set instruction address.
* Clean up hic->parse_bits use
* Fix: .new registers were not resolved dur to too early return.
* Fix rebase mistakes.
* Add missing code
* Fix build error: Use sizeof(`text_infix`) since it is way smaller than `text`
* Initialize `HexInsn` inside `setup_new_hic`. Fixes NULL access.
* Mark RzAsm/RzAnalysis members as deprecated and fix typo.
Although the reg profile was not really used yet it will be relevant for the RZIL uplifting.
Introduces:
* Double/quadruple registers now properly overlap with their counterparts.
* Registers have correct types assigned (vec, ctr, sys etc. Before, all regs were of type gbr)
* Consistent register names (asm name style: c3:2, r31 etc, alias style: lc1:sa1, lr etc.)
* Adds _tmp registers in the profile. Later used by uplifted instructions (think of .new registers).
* Add function to add config node to config by `RzConfigNode*`
* Move `SET<NODE>` macros to `rz_config.h`
* Add un/set functions for plugin specific configs.
* Add RzConfig and node setter to hexagon plugin.
* Use plugins RzConfig to determine sdk syntax setting.
* Use plugins RzConfig to determine if numbers should be signed.
* Use plugins RzConfig to determine if immediate hash should be printed.
* Remove unused parameter `rz_asm`.
* Remove unused variable.
* Remove unused callback.
* Remove unused flags from `RzAsm`
* Fix asm tests: Add NULL check; Set correct sign in asm test.
* Add option to print instruction packets syntax in objdump style.
* Add the config `plugins.hexagon.sdk` to toggle syntax.
* Remove unused trimming.
* Trim only newlines from the assembly string.
* Add new trim functions to allow trimming of certain chars.
Also new in this commit:
- Uses system registers as defined in LLVM definitions.
- Several new Hexagon v69 (HVX) instructions.
- File header now has the LLVM commit and timestamps of the source file generation.
* Add support for: v5-v68+HVX, System instructions/register; Change plugin design to monolithic; Basic ELF-reloc patching.
- Update instruction set to v5-v67 + HVX.
- Introduce monolithic plugin architecture to reverse opcodes in the same functions.
- Analysis and Asm functionality was previously seperated and let to inconsistensies and incorrectly reversed opcodes.
- Add missing system instructions and registers.
- Enable search for immediates.
- Mark packets of instructions.
- Set more analysis data in RzAnalysisOp.
- Add basic ELF-reloc patching.
- Fix several disassembly and analysis bugs.
- Jumps were not aligned to packet begin.
- Endloop packets were not marked as such.
- Rs.New registers were incorrectly disassembled.
- Calling convention was out of date.
- Add several formatting configs for the produced disassembly.
- Dis/Enable UTF-8.
- Print or omit # prefix of immediates.
- Print signed immediates as signed or unsigned integers.
