* Basic framework of rx implemented
* Add match and parse flow
* Add part of description for RxV1 instruction set
* Add datasheet for rxv1
* Implement stringify op for rx
* Add missing TST instruction in datasheet
* Test to div instruction and fix bugs
* Test known rxv1 instruction set
* Fix bugs in rx disasm plugin and add SPDX
* Add rz_analysis for renesas rx
* Fix rz_analysis bug for renesas rx
* Add rz_asm test and fix bug in datasheet
* Add analysis test and fix bugs for renesas rx
* Extract major and minor from python version string instead of converting it to double
The patch fixes 3.10 version extraction (3.10 == 3.1)
* update latest python magic version to 3491 in get_code_object
* opcodes for python3.10
* PYC: do not search for strings in code
* PYC python 3.10 tests
* Fixed typo in "pyc 3.9 sections" test
* pyc: refactored string search
* pyc: removed parse_version_major_minor
use "magic_int_within" to check python version
- Introduce the following new methods:
* `rz_analysis_similarity_basic_block()`
* `rz_analysis_similarity_function()`
* `rz_analysis_similarity_basic_block_2()`
* `rz_analysis_similarity_function_2()`
* `rz_analysis_match_basic_blocks()`
* `rz_analysis_match_functions()`
* `rz_analysis_match_basic_blocks_2()`
* `rz_analysis_match_functions_2()`
- Remove `RzAnalysisDiff` and its usages
- Remove `librz/analysis/diff.c` entirely to and adds `librz/analysis/similarity.c`
- Remove a lot of unused structures and simplified the code by a lot
- Fix typo in levenshtein
- Remove `librz/core/gdiff.c` and `gdiff` functions since they were unused or only used in rz-diff
- Remove `difftype` (or "color") from `RzANode` which lead to dead code
- Decrease serialized data in projects.
- Add `RzAnalysisVarKind` and `RzAnalysisVarType` and replaces all the hardcoded values
- Remove command `agd`
- Remove all `rz_core_gdiff` usages from `rz_core.h`
- Refactor `rz_analysis_var_list` and `rz_analysis_var_count` due unused argument (`RzAnalysis` was not used)
- Add new method `rz_analysis_var_count_total` to simplify some usages
- Remove `rz_core_graph_diff`
- Add `typedef RzAnalysisFcnType` on `enum``used for function types
- Remove unused `RZ_ANALYSIS_FCN_VARKIND_LOCAL`
- Remove from `RzAnalysisFunction` the following variables:
* `fingerprint`
* `fingerprint_size`
* `diff`
* `diff_ops`
* `diff_thbb`
* `diff_thfcn`
- Remove from `RzAnalysisBlock` the following variables:
* `fingerprint`
* `diff`
- Remove `RZ_ANALYSIS_THRESHOLDBB` and `RZ_ANALYSIS_THRESHOLDFCN`
- Remove the following callbacks from `RzAnalysisPlugin`
* `RzAnalysisDiffBBCallback`
* `RzAnalysisDiffFcnCallback`
* `RzAnalysisDiffEvalCallback`
- Fix fancy table columns/rows when a color string is in a cell
- Bumped project version to 9
Duplicated code for pkg-config and cmake configuration is avoided by
letting every rizin module register itself in a global dictionary
called "modules" which is then iterated in one place to perform any
shared logic, inspired by how qemu handles multiple targets in its meson
build system.
This is an almost pure refactor, so the resulting .pc/.cmake files
should be identical with the following exceptions:
- rz_reg.pc does not have plugindir anymore as rz_reg has no plugins.
- Some other modules have their dependencies in .pc files altered to be
consistent with cmake.
* Print a warning if config for VM was NULL.
* Add warning if register is not added to VM due to overlap.
* Update PPC register profile.
* Add vector and float registers. As well as some control and system registers.
* Enable to write values 4bit registers.
* PPC: Uplift most common instructions.
* Print warning if reserved SPR instruction is encountered.
* Update PC/LR addresses and add ca32 writes.
* Write cache needs to get flushed so load and store tests don't share the same memory.
* Add missing T/F branch mnemonics.
* Add Move to/from CR/CR0-7
* Fix TA address calculation for branch instructions.
* Add branch tests for branch mnemonics.
* Add XNOP
* NOP cache touch instructions.
* Add undocumented ATTN instruction to the not_implemented group.
* Add isel instruction.
* Implement CRCLR, CRSET, CROR.
* Add CNTLZ instructions.
* Add mcrf instructions.
* Add inacive test for cmpb.
* Add Load bytes reverse instructions.
* Add test and add address alignment to dcbz.
* Add eqv test
* Correct DIV and MUL operations
* Add div tests.
* Add tests and correct MT/MFXER
* Remove register ca32, ov32
* Remove explici setting of cr register because QEMU does not do it. Otherwise we get a mismatch in the trace
* Simplify carry set for add and sub. Sub instructions are exclusivly defined with addition. Hence no sub case needed.
* Unify BD and fix branch instructions. Fix: Check the single bit not the cr reg
* Document Conditional branches and replace NOPs with EMPTY
* Add mulli instruction to double word instructions.
* Fix ca set for shift instructions:
* ca value had to be determined before the shift happened. The wrong ca value was calculated if the src and target reg were the same.
* Replace NOP wit EMPTY.
* Use MSB isntead of SLT.
* Brought fixup of ADD and SUB instructions: The add and sub instructions had several issues which let to incorrect execution.
* The carry was incorrectly if three add operations happened (only the last add were checked, not both).
* The carry was incorrectly set if the src and target register matched.
* Same applies for the CR bit.
* It was too complex. Several local variables were introduced for this.
* Set result in local var, since it would change if src and target reg are the same.
* Remove MTMSR and MFMSR since it is too complex and untestable currently.
* Use unsigned int for shift. Otherwise the 0x1c shift produces a runtime error since 0xf is int as default.
* Fix mtxer: Only write flag bits.
* Let NOT_IMPLEMENTED macro return NULL.
* Mark st[wd]cx and l[wd]cx as not implemented.
* Increase dcache_line_size to 128 bytes.
* Fix cntlz for ppc32. m was set incorrectly, since it is 0 not 32 for 32bit cpus.
* Fix isel: Use op.crx reg instead of imm.
* Unify helper function names: Prependnig `ppc_` mark as IPI
* Add more "Move to SPR" cases.
* MULLI opeartes only on double word on 64bit CPUs.
* Most registers are now assigned the control register type and no longer show up in the ar command.
* Fix xor if dest and src registers match by saving result in local var.
* Fix BE/LE issue for Load BRX instructions.
* Fix shifts: Use only lower 6bits of n.
* User Pure local variables for ROT macros.
* Fix rldimi instructions.
* n was not inverted.
* more than 6 bits of n could be used
* Add 32bit emulateme tests.
* Add 64bit emulateme tests.
* Determine lg(v) in inline function.
* Calculate CR bit in C not in the VM.
* Check if `~mask = 0` and skip mask calculation if yes.
* Check for `sh == 0` and skip rotations where possible.
* Remove `la` instruction. `la` is a mnemonic for `addi`.
* Remove SPR instructions which are not supported by QEMU or not traced yet. For most set/read SPR instructions QEMU segfaults.
In case of SPR 1 (xer), 8 (lr) and 9 (ctr) the assembler resolves them to their mnemonics (mtxer, mtlr etc.). This means the code here is never reached.
To test the get_xer code MFXER was added again. The rz-tracetests will fail for this instructions (due to missing ca32, ov32). But this case is covert in an issue.
RzAnalysisILVM wraps around the low-level RzILVM and enables emulation
of real code from disassembly, rather than raw IL.
Analysis plugins now don't actively initialize the vm anymore, but
return a fully declarative description RzAnalysisILConfig of how to set
up the vm and optionally its initial state.
This also enables multiple IL vms to exist at the same time as plugins
can not mess with the global vm anymore. See the added integration test
for an example.
* Move binrz meson directives to binrz/ dir
* Move rizin-shell-parser to a subproject
* Move bochs to a meson subproject
* Move rzqnx to meson subproject
* Move winkd to a meson subproject
* Move rzar to a meson subproject
* Move rzw32dbg_wrap to a meson subproject
* Move ptrace-wrap to a meson subproject
* Move rzgdb to a meson subproject
* Rename w32dbg_wrap to rzw32dbg_wrap
* Update CODEOWNERS
* Remove old references to shlr
* Move shlr/heap stuff in core and remove shlr/arm
* Move spp to a meson subproject
* Remove last references to shlr
* Remove use_webui option
* Move include files directives to librz/include/meson.build
* Move librz meson directives into librz/meson.build
* Handle d/ directories inside the specific module meson.build
* Move plugins listing to specific module meson.build
* Move rzheap to its own subproject
* Fix js linter and licenses
* Use meson.override_dependency for all rz_ modules
* Remove wrong librz.pc.in file
* Add plugindir variable to .pc files to allow easy plugin configuration
* Add CMake config files to find Rizin in CMake projects
* Add CI jobs to check cmake files
* Provide workaround for mesonbuild/meson#9702
* Use .lib suffix and no prefix on MSVC to make CMake files work
* Disable cmake files on static libraries build
ESIL Pins were an untested feature to run a command when emulation hit a
specific address. This can be solved in other ways, e.g. scripting.
Project version 7 has been introduced for this change.
* Add support for: v5-v68+HVX, System instructions/register; Change plugin design to monolithic; Basic ELF-reloc patching.
- Update instruction set to v5-v67 + HVX.
- Introduce monolithic plugin architecture to reverse opcodes in the same functions.
- Analysis and Asm functionality was previously seperated and let to inconsistensies and incorrectly reversed opcodes.
- Add missing system instructions and registers.
- Enable search for immediates.
- Mark packets of instructions.
- Set more analysis data in RzAnalysisOp.
- Add basic ELF-reloc patching.
- Fix several disassembly and analysis bugs.
- Jumps were not aligned to packet begin.
- Endloop packets were not marked as such.
- Rs.New registers were incorrectly disassembled.
- Calling convention was out of date.
- Add several formatting configs for the produced disassembly.
- Dis/Enable UTF-8.
- Print or omit # prefix of immediates.
- Print signed immediates as signed or unsigned integers.
The new intermediate language is based on the BAP (Binary Analysis Platform) Core Theory.
It operates on SMT-like bitvectors and their arrays to represent values and memory.
Apart from that, it has also representation for the data and code side effects.
* Add global var concept
* Doxygen & ownership & delete `delete_all` & argc check
* Use RBTree to manage the address of global variable
* Kill comment and access & use ht_pp_new
* Add unit test and regressions test
* Remove GlobalVarNode
* Implement global variable [de]serialization
* Moved `rz_cmd_state_output_array_start`
* Added complex type tests
* delete/get at or in address & convert type links to global variable & minor fix
* Remove `size` field
* Migration of typelinks to global var
* Use exists type parser
* Recover typelink unit test
- Removed oldshell version of `t` (types) commands
- Removed `tk` command because types storage switched to the hashtable
- Added `tfc` command to show the calling convention of the function or set it
- Added `tsl` (RZ_OUTPUT_MODE_LONG) to show structure members' sizes and offsets
- Added `tul` (RZ_OUTPUT_MODE_LONG) to show union members' sizes
- Switched the types storage to the hashtable instead of SDB
- Added load and export from/to SDB for standard type libraries and serialization for Projects
- Changed all `char *type` occurences to the proper `RzType`
- Added `RzCallable` type for the function/class method types
- Changed all function types API to use the `RzCallable` API
- Switched the function types (`RzCallable`) storage to the hashtable instead of SDB
- Added a connection between `RzAnalysisFunction` and `RzCallable` - `rz_analysis_function_derive_type()` API function to derive new `RzCallable` type from the `RzAnalysisFunction` even if it doesn't exist in the RzTypeDB.
- Moved type links to the RzAnalysis where they belong
- Removed TCC and MPC-based parsers
- Added Tree-Sitter-based parser for C grammar (see `librz/type/parser/*`)
- Reworked type databases in `librz/analysis/d/` to be consistent with C standard, libc, platform-specific definitions
- Switched the type links from `char *` to `RzType`
- Switched the type links from SDB to the hashtable
- Added concept of the "type paths", e.g. `a.b[20].c` where `b` is a member of `a` (`a` is either structure or a union) and `c` is a member of `b`, and `b` is an array where we take 20-th element.
- Added concept of the typeclasses (a bit similar to Haskell) for numerical types: `None` (the most generic one), `Num` (includes `Integral` and `Floating`), `Integral` (includes `Signed Integral` and `Unsigned Integral`), `Floating`.
- Added concept of type equality (`rz_types_equal(a, b)` API function)
- Added Doxygen documentation to every API function in the `librz/type/*`.
- Updated the project format from **V2** to **V3**, added migration.
* Remove the unnecessary `sdb` pointer of `RzArchTarget`
The SDB pointer in `RzArchTarget` is not needed as `sdb_load_arch_profile_by_path`
creates a new SDB pointer and takes care of our requirements.
* Introduce `RzArchPlatformTarget` and `RzArchPlatformItem` and the new APIs
Also define a new flagspace: `RZ_FLAGS_FS_PLATFORM_PORTS`
* Introduce a new configuration variable `asm.platform` to choose the
platform profile
* Define and call the APIs for platform profiles
* Add the SDB file for BCM 2835 and a unit test
* Check for NULL at various places and run `clang-format`
* Use `RZ_NONULL` for the parameters of `rz_arch_platform_init`
* Add `RZ_NONNULL` to all of the arguments which gets `rz_return[_val]_if()`-ed
* Let `platform` be NULLABLE and fix the ASAN tests
* Introduce `RzArchProfile` and add the CPU profiles
* Create `rz_arch.h` and `arch_profile.c`
* Add the CPU Profile's SDB files
* Add the `meson.build` for compiling SDB files
* Add the hashtables and the flagspaces
* Add a test and compare the `type` in `rz_sysreg_get`
* Update the list of AVR CPUs in `asm_avr`
* Run clang-format and include rz_arch.h in rz_analysis.h
* Fix the install directory of the compiled SDB files
* Introduce `RzArchTarget` which houses `RzArchProfile`
* Support for loading a new profile when `asm.cpu` is changed
* Change the variables names to lowercase and add tests
* Add a test for loading a new CPU profile when CPU is changed
* Add Doxygen documentation, run `clang-format` and correct the requested changes
* Remove unnecessary zero-initializations and other improvements
* Reversed a condition while creating the path in `rz_arch_profiles_init`
* Fixed four tests: three regarding printing the flagspaces and one from printing flags after analysis in AVR
* Free the required pointers and check for `NULL`
* Free the pointers that was allocated previously, before returning `NULL`
* Free the pointer in `rz_sysregs_db_new`
* Support for adding a fallback profile for unsupported CPUs
