188 lines
4 KiB
C
188 lines
4 KiB
C
// 64bit host debugging 64bit target
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return strdup (
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"=PC rip\n"
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"=SP rsp\n"
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"=BP rbp\n"
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"=R0 rax\n"
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"=A0 rdi\n"
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"=A1 rsi\n"
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"=A2 rdx\n"
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"=A3 rcx\n"
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"=A4 r8\n"
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"=A5 r9\n"
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"=SN orax\n"
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"# no profile defined for x86-64\n"
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"gpr rax .64 80 0\n"
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"gpr eax .32 80 0\n"
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"gpr ax .16 80 0\n"
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"gpr ah .8 81 0\n"
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"gpr al .8 80 0\n"
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"gpr rbx .64 40 0\n"
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"gpr ebx .32 40 0\n"
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"gpr bx .16 40 0\n"
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"gpr bh .8 41 0\n"
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"gpr bl .8 40 0\n"
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"gpr rcx .64 88 0\n"
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"gpr ecx .32 88 0\n"
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"gpr cx .16 88 0\n"
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"gpr ch .8 89 0\n"
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"gpr cl .8 88 0\n"
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"gpr rdx .64 96 0\n"
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"gpr edx .32 96 0\n"
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"gpr dx .16 96 0\n"
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"gpr dh .8 97 0\n"
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"gpr dl .8 96 0\n"
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"gpr r8 .64 72 0\n"
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"gpr r8d .32 72 0\n"
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"gpr r8w .16 72 0\n"
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"gpr r8b .8 72 0\n"
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"gpr r9 .64 64 0\n"
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"gpr r9d .32 64 0\n"
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"gpr r9w .16 64 0\n"
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"gpr r9b .8 64 0\n"
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"gpr r10 .64 56 0\n"
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"gpr r10d .32 56 0\n"
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"gpr r10w .16 56 0\n"
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"gpr r10b .8 56 0\n"
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"gpr r11 .64 48 0\n"
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"gpr r11d .32 48 0\n"
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"gpr r11w .16 48 0\n"
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"gpr r11b .8 48 0\n"
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"gpr r12 .64 24 0\n"
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"gpr r12d .32 24 0\n"
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"gpr r12w .16 24 0\n"
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"gpr r12b .8 24 0\n"
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"gpr r13 .64 16 0\n"
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"gpr r13d .32 16 0\n"
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"gpr r13w .16 16 0\n"
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"gpr r13b .8 16 0\n"
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"gpr r14 .64 8 0\n"
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"gpr r14d .32 8 0\n"
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"gpr r14w .16 8 0\n"
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"gpr r14b .8 8 0\n"
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"gpr r15 .64 0 0\n"
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"gpr r15d .32 0 0\n"
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"gpr r15w .16 0 0\n"
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"gpr r15b .8 0 0\n"
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"gpr rsi .64 104 0\n"
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"gpr esi .32 104 0\n"
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"gpr si .16 104 0\n"
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"gpr sil .8 104 0\n"
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"gpr rdi .64 112 0\n"
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"gpr edi .32 112 0\n"
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"gpr di .16 112 0\n"
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"gpr dil .8 112 0\n"
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"gpr rsp .64 152 0\n"
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"gpr esp .32 152 0\n"
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"gpr sp .16 152 0\n"
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"gpr spl .8 152 0\n"
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"gpr rbp .64 32 0\n"
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"gpr ebp .32 32 0\n"
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"gpr bp .16 32 0\n"
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"gpr bpl .8 32 0\n"
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"gpr rip .64 128 0\n"
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"seg@gpr cs .64 136 0\n"
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"gpr rflags .64 144 0 c1p.a.zstido.n.rv\n"
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"gpr eflags .32 144 0 c1p.a.zstido.n.rv\n"
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"gpr cf .1 .1152 0 carry\n"
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"gpr pf .1 .1154 0 parity\n"
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"gpr af .1 .1156 0 adjust\n"
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"gpr zf .1 .1158 0 zero\n"
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"gpr sf .1 .1159 0 sign\n"
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"gpr tf .1 .1160 0 trap\n"
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"gpr if .1 .1161 0 interrupt\n"
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"gpr df .1 .1162 0 direction\n"
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"gpr of .1 .1163 0 overflow\n"
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"gpr orax .64 120 0\n"
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"seg@gpr ss .64 160 0\n"
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"seg@gpr fs_base .64 168 0\n"
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"seg@gpr gs_base .64 176 0\n"
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"seg@gpr ds .64 184 0\n"
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"seg@gpr es .64 192 0\n"
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"seg@gpr fs .64 200 0\n"
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"seg@gpr gs .64 208 0\n"
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"drx dr0 .64 0 0\n"
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"drx dr1 .64 8 0\n"
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"drx dr2 .64 16 0\n"
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"drx dr3 .64 24 0\n"
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// dr4 32
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// dr5 40
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"drx dr6 .64 48 0\n"
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"drx dr7 .64 56 0\n"
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/*0030 struct user_fpregs_struct
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0031 {
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0032 __uint16_t cwd;
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0033 __uint16_t swd;
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0034 __uint16_t ftw;
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0035 __uint16_t fop;
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0036 __uint64_t rip;
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0037 __uint64_t rdp;
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0038 __uint32_t mxcsr;
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0039 __uint32_t mxcr_mask;
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0040 __uint32_t st_space[32]; // 8*16 bytes for each FP-reg = 128 bytes
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0041 __uint32_t xmm_space[64]; // 16*16 bytes for each XMM-reg = 256 bytes
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0042 __uint32_t padding[24];
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0043 };
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*/
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"fpu cwd .16 0 0\n"
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"fpu swd .16 2 0\n"
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"fpu ftw .16 4 0\n"
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"fpu fop .16 6 0\n"
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"fpu frip .64 8 0\n"
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"fpu frdp .64 16 0\n"
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"fpu mxcsr .32 24 0\n"
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"fpu mxcr_mask .32 28 0\n"
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"fpu st0 .80 32 0\n"
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"fpu st1 .80 48 0\n"
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"fpu st2 .80 64 0\n"
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"fpu st3 .80 80 0\n"
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"fpu st4 .80 96 0\n"
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"fpu st5 .80 112 0\n"
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"fpu st6 .80 128 0\n"
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"fpu st7 .80 144 0\n"
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"mmx@fpu mm0 .64 32 8\n"
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"mmx@fpu mm1 .64 48 8\n"
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"mmx@fpu mm2 .64 64 8\n"
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"mmx@fpu mm3 .64 80 8\n"
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"mmx@fpu mm4 .64 96 8\n"
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"mmx@fpu mm5 .64 112 8\n"
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"mmx@fpu mm6 .64 128 8\n"
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"mmx@fpu mm7 .64 144 8\n"
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"fpu xmm0 .64 160 16\n"
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"fpu xmm0h .64 160 8\n"
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"fpu xmm0l .64 168 8\n"
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"fpu xmm1 .64 176 16\n"
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"fpu xmm1h .64 176 8\n"
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"fpu xmm1l .64 184 8\n"
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"fpu xmm2 .64 192 16\n"
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"fpu xmm2h .64 192 8\n"
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"fpu xmm2l .64 200 8\n"
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"fpu xmm3 .64 208 16\n"
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"fpu xmm3h .64 208 8\n"
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"fpu xmm3l .64 216 8\n"
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"fpu xmm4 .64 224 16\n"
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"fpu xmm4h .64 224 8\n"
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"fpu xmm4l .64 232 8\n"
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"fpu xmm5 .64 240 16\n"
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"fpu xmm5h .64 240 8\n"
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"fpu xmm5l .64 248 8\n"
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"fpu xmm6 .64 256 16\n"
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"fpu xmm6h .64 256 8\n"
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"fpu xmm6l .64 264 8\n"
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"fpu xmm7 .64 272 16\n"
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"fpu xmm7h .64 272 8\n"
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"fpu xmm7l .64 280 8\n"
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"fpu x64 .64 288 0\n"
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);
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