10bedc2b00
Although the reg profile was not really used yet it will be relevant for the RZIL uplifting. Introduces: * Double/quadruple registers now properly overlap with their counterparts. * Registers have correct types assigned (vec, ctr, sys etc. Before, all regs were of type gbr) * Consistent register names (asm name style: c3:2, r31 etc, alias style: lc1:sa1, lr etc.) * Adds _tmp registers in the profile. Later used by uplifted instructions (think of .new registers).
106 lines
892 B
Text
106 lines
892 B
Text
NAME=ara swap
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara+
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ar rax=33
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ar rax
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aras
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ar rax
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EOF
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EXPECT=<<EOF
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rax = 0x00000021
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rax = 0x00000000
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EOF
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RUN
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NAME=ara swap 2
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara+
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ar rax=33
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ar rax
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aras
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ar rax
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aras
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ar rax
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EOF
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EXPECT=<<EOF
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rax = 0x00000021
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rax = 0x00000000
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rax = 0x00000021
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EOF
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RUN
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NAME=ara push
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara~?
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ara+
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ara~?
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EOF
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EXPECT=<<EOF
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26
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39
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EOF
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RUN
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NAME=ara pop
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara~?
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ara+
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ara~?
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ara-
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ara~?
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ara-
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ara~?
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ara-
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ara~?
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EOF
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EXPECT=<<EOF
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26
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39
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26
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13
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13
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EOF
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RUN
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NAME=arcc+tcc
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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afcl
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e asm.arch=arm
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e asm.bits=32
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arcc
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e asm.arch=x86
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e asm.bits=64
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arcc
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tcc `arcc`
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afcl
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EOF
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EXPECT=<<EOF
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amd64
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amd64syscall
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ms
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reg
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swift
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r0 reg(r0, r1, r2, r3)
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rdi reg(rdi, rsi, rdx, rcx)
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amd64
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amd64syscall
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ms
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reg
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swift
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EOF
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RUN
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