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Use CONFIG_ variables instead of configuration definitions

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This commit is contained in:
Adrian Danis 2017-05-29 17:00:34 +10:00
parent 1930cf2e44
commit 1f2f6b98bb
6 changed files with 22 additions and 21 deletions
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18
include/arch/arm/arch/32/mode/machine.h
View file

@ -254,7 +254,7 @@ void lockTLBEntry(vptr_t vaddr);
static inline void cleanByVA(vptr_t vaddr, paddr_t paddr)
{
#ifdef ARM_CORTEX_A8
#ifdef CONFIG_ARM_CORTEX_A8
/* Erratum 586324 -- perform a dummy cached load before flushing. */
asm volatile("ldr r0, [sp]" : : : "r0");
/* Erratum 586320 -- clean twice with interrupts disabled. */
@ -270,21 +270,21 @@ static inline void cleanByVA(vptr_t vaddr, paddr_t paddr)
/* D-Cache clean to PoU (L2 cache) (v6/v7 common) */
static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr)
{
#ifdef ARM_CORTEX_A8
#ifdef CONFIG_ARM_CORTEX_A8
/* Erratum 586324 -- perform a dummy cached load before flushing. */
asm volatile("ldr r0, [sp]" : : : "r0");
asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr));
#elif defined(CONFIG_ARCH_ARM_V6)
/* V6 doesn't distinguish PoU and PoC, so use the basic flush. */
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(PLAT_EXYNOS5)
#elif defined(CONFIG_PLAT_EXYNOS5)
/* Flush to coherency for table walks... Why? */
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(PLAT_IMX7)
#elif defined(CONFIG_PLAT_IMX7)
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(CONFIG_PLAT_TK1)
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(ARM_CORTEX_A53)
#elif defined(CONFIG_ARM_CORTEX_A53)
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#else
asm volatile("mcr p15, 0, %0, c7, c11, 1" : : "r"(vaddr));
@ -296,7 +296,7 @@ static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr)
/* D-Cache invalidate to PoC (v6/v7 common) */
static inline void invalidateByVA(vptr_t vaddr, paddr_t paddr)
{
#ifdef ARM_CORTEX_A8
#ifdef CONFIG_ARM_CORTEX_A8
/* Erratum 586324 -- perform a dummy cached load before flushing. */
asm volatile("ldr r0, [sp]" : : : "r0");
asm volatile("mcr p15, 0, %0, c7, c6, 1" : : "r"(vaddr));
@ -309,7 +309,7 @@ static inline void invalidateByVA(vptr_t vaddr, paddr_t paddr)
/* I-Cache invalidate to PoU (L2 cache) (v6/v7 common) */
static inline void invalidateByVA_I(vptr_t vaddr, paddr_t paddr)
{
#ifdef ARM_CORTEX_A8
#ifdef CONFIG_ARM_CORTEX_A8
/* On A8, we just invalidate the lot. */
asm volatile("mcr p15, 0, %0, c7, c5, 0" : : "r"(0));
#else
@ -321,7 +321,7 @@ static inline void invalidateByVA_I(vptr_t vaddr, paddr_t paddr)
/* I-Cache invalidate all to PoU (L2 cache) (v6/v7 common) */
static inline void invalidate_I_PoU(void)
{
#ifdef ARM_CORTEX_A8
#ifdef CONFIG_ARM_CORTEX_A8
/* Erratum 586324 -- perform a dummy cached load before flushing. */
asm volatile("ldr r0, [sp]" : : : "r0");
#endif
@ -332,7 +332,7 @@ static inline void invalidate_I_PoU(void)
/* D-Cache clean & invalidate to PoC (v6/v7 common) */
static inline void cleanInvalByVA(vptr_t vaddr, paddr_t paddr)
{
#ifdef ARM_CORTEX_A8
#ifdef CONFIG_ARM_CORTEX_A8
/* Erratum 586324 -- perform a dummy cached load before flushing. */
asm volatile("ldr r0, [sp]" : : : "r0");
/* Erratum 586320 -- clean twice with interrupts disabled. */

10
include/arch/arm/arch/32/mode/machine/hardware.h
View file

@ -21,19 +21,19 @@
#if defined(CONFIG_ARM1136JF_S)
#define L1_CACHE_LINE_SIZE_BITS 5 /* 32 bytes */
#elif defined(ARM_CORTEX_A8)
#elif defined(CONFIG_ARM_CORTEX_A8)
#define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */
#elif defined(ARM_CORTEX_A9)
#elif defined(CONFIG_ARM_CORTEX_A9)
#define L1_CACHE_LINE_SIZE_BITS 5 /* 32 bytes */
#elif defined(ARM_CORTEX_A7)
#elif defined(CONFIG_ARM_CORTEX_A7)
#define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */
#elif defined(ARM_CORTEX_A15)
#elif defined(CONFIG_ARM_CORTEX_A15)
#define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */
#elif defined(ARM_CORTEX_A53)
#elif defined(CONFIG_ARM_CORTEX_A53)
#define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */
#endif

4
include/arch/arm/arch/64/mode/machine/hardware.h
View file

@ -18,11 +18,11 @@
#define PAGE_BITS seL4_PageBits
#if defined(ARM_CORTEX_A53)
#if defined(CONFIG_ARM_CORTEX_A53)
#define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */
#endif
#if defined(ARM_CORTEX_A57)
#if defined(CONFIG_ARM_CORTEX_A57)
#define L1_CACHE_LINE_SIZE_BITS 6 /* 64 bytes */
#endif

4
include/plat/exynos5/plat/machine.h
View file

@ -81,9 +81,9 @@ enum IRQConstants {
INTERRUPT_INTG30 = 62,
INTERRUPT_INTG31 = 63,
INTERRUPT_EINT16_31 = 64,
#if defined(PLAT_EXYNOS5250)
#if defined(CONFIG_PLAT_EXYNOS5250)
INTERRUPT_MDMA0_CORE = 65,
#elif defined(PLAT_EXYNOS5410)
#elif defined(CONFIG_PLAT_EXYNOS5410)
INTERRUPT_TMU_CPU0 = 65,
#else
#endif

4
include/plat/exynos5/plat/machine/devices.h
View file

@ -259,13 +259,13 @@
#define AUDSS_PADDR 0x03810000
/* SoC specific devices */
#if defined(PLAT_EXYNOS5250) /* Arndale */
#if defined(CONFIG_PLAT_EXYNOS5250) /* Arndale */
#define GPIO_LEFT_PADDR 0x11400000
#define GPIO_RIGHT_PADDR 0x13400000
#define C2C_GPIO_PADDR 0x10D10000
#define AUDIO_GPIO_PADDR 0x03860000
#elif defined(PLAT_EXYNOS54XX) /* Odroid XU and XU3 */
#elif defined(CONFIG_PLAT_EXYNOS54XX) /* Odroid XU and XU3 */
#define GPIO_LEFT_PADDR 0x14000000
#define GPIO_RIGHT_PADDR 0x13400000
#define C2C_GPIO_PADDR 0x10D10000

3
src/arch/arm/armv/armv8-a/32/machine_asm.S
View file

@ -8,9 +8,10 @@
* @TAG(GD_GPL)
*/
#include <config.h>
#include <machine/assembler.h>
#if defined(ARM_CORTEX_A53)
#if defined(CONFIG_ARM_CORTEX_A53)
/* A53 hardware does not support TLB locking */
BEGIN_FUNC(lockTLBEntry)