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spike: Refactor into clearer subplatforms

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For now we keep the RISC-V platforms under the spike kernel platform
name. Splitting the different platform definitions into different header
files will help maintainability as we add different device layouts and
kernel device drivers.
This commit is contained in:
Kent McLeod 2019-05-22 20:41:50 +10:00
parent 8dc90b559f
commit 2865d6b61b
5 changed files with 88 additions and 13 deletions
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27
include/plat/spike/plat/instance/hifive/hardware.h Normal file
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@ -0,0 +1,27 @@
/*
* Copyright 2019, Data61
* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
* ABN 41 687 119 230.
*
* This software may be distributed and modified according to the terms of
* the GNU General Public License version 2. Note that NO WARRANTY is provided.
* See "LICENSE_GPLv2.txt" for details.
*
* @TAG(DATA61_GPL)
*/
#ifndef __PLAT_INSTANCE_HARDWARE_H
#define __PLAT_INSTANCE_HARDWARE_H
/* Available physical memory regions on platform (RAM minus kernel image). */
/* NOTE: Regions are not allowed to be adjacent! */
static p_region_t BOOT_DATA avail_p_regs[] = {
/* The first 2MB are reserved for the SBI in the BBL */
#if defined(CONFIG_ARCH_RISCV64)
{ /*.start = */ 0x80200000, /* .end = */ 0x17FF00000}
#elif defined(CONFIG_ARCH_RISCV32)
{ /*.start = */ 0x80200000, /* .end = */ 0xFD000000}
#endif
};
#endif

27
include/plat/spike/plat/instance/qemu/hardware.h Normal file
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@ -0,0 +1,27 @@
/*
* Copyright 2019, Data61
* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
* ABN 41 687 119 230.
*
* This software may be distributed and modified according to the terms of
* the GNU General Public License version 2. Note that NO WARRANTY is provided.
* See "LICENSE_GPLv2.txt" for details.
*
* @TAG(DATA61_GPL)
*/
#ifndef __PLAT_INSTANCE_HARDWARE_H
#define __PLAT_INSTANCE_HARDWARE_H
/* Available physical memory regions on platform (RAM minus kernel image). */
/* NOTE: Regions are not allowed to be adjacent! */
static p_region_t BOOT_DATA avail_p_regs[] = {
/* The first 2MB are reserved for the SBI in the BBL */
#if defined(CONFIG_ARCH_RISCV64)
{ /*.start = */ 0x80200000, /* .end = */ 0x17FF00000}
#elif defined(CONFIG_ARCH_RISCV32)
{ /*.start = */ 0x80200000, /* .end = */ 0xFD000000}
#endif
};
#endif

23
include/plat/spike/plat/instance/rocket-chip/hardware.h Normal file
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@ -0,0 +1,23 @@
/*
* Copyright 2019, Data61
* Commonwealth Scientific and Industrial Research Organisation (CSIRO)
* ABN 41 687 119 230.
*
* This software may be distributed and modified according to the terms of
* the GNU General Public License version 2. Note that NO WARRANTY is provided.
* See "LICENSE_GPLv2.txt" for details.
*
* @TAG(DATA61_GPL)
*/
#ifndef __PLAT_INSTANCE_HARDWARE_H
#define __PLAT_INSTANCE_HARDWARE_H
/* Available physical memory regions on platform (RAM minus kernel image). */
/* NOTE: Regions are not allowed to be adjacent! */
static p_region_t BOOT_DATA avail_p_regs[] = {
/* The first 2MB are reserved for the SBI in the BBL */
{ /*.start = */ 0x0, /* .end = */ 0x10000000}
};
#endif

11
include/plat/spike/plat/machine.h
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@ -20,6 +20,17 @@
#define __PLAT_MACHINE_H
#ifndef __ASSEMBLER__
#if defined(CONFIG_BUILD_SPIKE_QEMU)
#include <plat/instance/qemu/hardware.h>
#elif defined(CONFIG_BUILD_ROCKET_CHIP_ZEDBOARD)
#include <plat/instance/rocket-chip/hardware.h>
#elif defined(CONFIG_BUILD_HI_FIVE_UNLEASHED)
#include <plat/instance/hifive/hardware.h>
#else
#error "Unsupported spike platform chosen"
#endif
enum IRQConstants {
INTERRUPT_SW = 0,
INTERRUPT_TIMER = 5,

13
src/plat/spike/machine/hardware.c
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@ -39,19 +39,6 @@
#define RESET_CYCLES ((CONFIG_SPIKE_CLOCK_FREQ / MS_IN_S) * CONFIG_TIMER_TICK_MS)
/* Available physical memory regions on platform (RAM minus kernel image). */
/* NOTE: Regions are not allowed to be adjacent! */
static p_region_t BOOT_DATA avail_p_regs[] = {
/* The first 2MB are reserved for the SBI in the BBL */
#if defined(CONFIG_BUILD_ROCKET_CHIP_ZEDBOARD)
{ /*.start = */ 0x0, /* .end = */ 0x10000000}
#elif defined(CONFIG_ARCH_RISCV64)
{ /*.start = */ 0x80200000, /* .end = */ 0x17FF00000}
#elif defined(CONFIG_ARCH_RISCV32)
{ /*.start = */ 0x80200000, /* .end = */ 0xFD000000}
#endif
};
BOOT_CODE int get_num_avail_p_regs(void)
{