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aarch32: Allow compilation for cortex-a72

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cortex-A72 can be run in aarch32 mode similar to cortex-a53.

Signed-off-by: Kent McLeod <kent@kry10.com>
This commit is contained in:
Kent McLeod 2023-03-01 17:02:43 +11:00 committed by Gerwin Klein
parent 0f497ab3a0
commit 9746e27615
2 changed files with 3 additions and 3 deletions
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2
include/arch/arm/arch/32/mode/machine.h
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@ -365,7 +365,7 @@ static inline void cleanByVA_PoU(vptr_t vaddr, paddr_t paddr)
/* V6 doesn't distinguish PoU and PoC, so use the basic flush. */
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#elif defined(CONFIG_ARM_CORTEX_A7) || defined(CONFIG_ARM_CORTEX_A15) || \
defined(CONFIG_ARM_CORTEX_A53)
defined(CONFIG_ARM_CORTEX_A53) || defined(CONFIG_ARM_CORTEX_A72)
/* Flush to coherency for table walks... Why? */
asm volatile("mcr p15, 0, %0, c7, c10, 1" : : "r"(vaddr));
#else

4
src/arch/arm/armv/armv8-a/32/machine_asm.S
View file

@ -7,9 +7,9 @@
#include <config.h>
#include <machine/assembler.h>
#if defined(CONFIG_ARM_CORTEX_A53)
#if defined(CONFIG_ARM_CORTEX_A53) || defined(CONFIG_ARM_CORTEX_A72)
/* A53 hardware does not support TLB locking */
/* A53,A72 hardware does not support TLB locking */
BEGIN_FUNC(lockTLBEntry)
bx lr
END_FUNC(lockTLBEntry)