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ARM: Fix hardcoded CPSR value for the idle thread

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This commit is contained in:
akroh 2015-03-23 10:34:08 +11:00
parent 092b2c1f35
commit a5f61c7166
2 changed files with 5 additions and 1 deletions
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4
include/arch/arm/arch/machine/registerset.h
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@ -33,6 +33,10 @@
| PMODE_SUPERVISOR \
| CPSR_EXTRA_FLAGS )
#define CPSR_IDLETHREAD ( PMASK_FIRQ \
| PMODE_SUPERVISOR \
| CPSR_EXTRA_FLAGS )
#ifdef __ASSEMBLER__
/* Offsets within the user context, these need to match the order in

2
src/arch/arm/kernel/thread.c
View file

@ -26,7 +26,7 @@ Arch_switchToThread(tcb_t *tcb)
BOOT_CODE void
Arch_configureIdleThread(tcb_t *tcb)
{
setRegister(tcb, CPSR, 0x1f);
setRegister(tcb, CPSR, CPSR_IDLETHREAD);
setRegister(tcb, LR_svc, (word_t)idleThreadStart);
}